From nobody Thu Apr 2 02:40:46 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13BFB36A013 for ; Tue, 31 Mar 2026 02:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774923332; cv=none; b=TxpJaJiNb0gYmdrl/DSiy8k54HDsUVI/E9y++KBQISvyKftFjRUc76fMGu0MzTF++jWX5ZGytDn9rLJY/M+OwQ+5GmPkuZZr+DThtPD0jYXmc6TJow7iamW7g45SlL77zTcGH1t5C4VL061KeTd8Z8jddPkMfyXUIawuR3Jx1Bk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774923332; c=relaxed/simple; bh=2GpCiZfU6WmNzDqR8CNiGs0Ar8OXPA4pk1VSGr1xYKM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M6WafcMheOvDzr2Ig2CRSF3bJLdRwzHgLuyuuM/XIDzSXaVAp98tWB0BlZM+OUBPvcVZwxJK6i0YDdwArm2LqnS/9PQBaW/q5a4WEUzFbHZgnVWdSKTkGXalY8pquZ23K7YYbaNDWxbY+rlVvrvX31HfqNx1azCAdA/e0pqXfD8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ctOzFm2k; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ctOzFm2k" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774923331; x=1806459331; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2GpCiZfU6WmNzDqR8CNiGs0Ar8OXPA4pk1VSGr1xYKM=; b=ctOzFm2kDu/RPhbwu3deAZOO/yfyFywpHq6Z/YIKKN/ilqp275H9fDmL EpCGYuvVsfMiDqfEbfB/46/Xwg6GVtVx2Fyv0dmfvIi2QB/ERsZu0URrE kt2D0beXB9bOtQoWZKjs0/PvZQ4yWJQuf9UnQez1r7o6Y8oPt9EP8YuPJ QYd1QWs3S8Qh7CsiHS3j9Qmf5Yfeyc9nOoPORNA4bW1CsUqDK05kVdbDf 7F7oIis/ogH0adBOAA91rnZqGsfDp59w3T2h8f6ok6faFG7/+LMTjejji ntBRjYNJQOg4tINxfQKFaBvwMX/iwbp3kjD6wWFFdAQjGeatLk6moxtIN A==; X-CSE-ConnectionGUID: fGx5sJAIQdGJfe+urcuxcw== X-CSE-MsgGUID: SZbyAopiQDW3B2vgoQM/eA== X-IronPort-AV: E=McAfee;i="6800,10657,11744"; a="93508180" X-IronPort-AV: E=Sophos;i="6.23,151,1770624000"; d="scan'208";a="93508180" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2026 19:07:58 -0700 X-CSE-ConnectionGUID: ycdmb2VNTB6BAMrDEfrLQg== X-CSE-MsgGUID: fA52ps0IQuW1UlHX4U8BfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,151,1770624000"; d="scan'208";a="221358728" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa006.fm.intel.com with ESMTP; 30 Mar 2026 19:07:54 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH v2 11/11] x86/microcode: Remove microcode_nmi_handler_enable Date: Tue, 31 Mar 2026 01:42:49 +0000 Message-ID: <20260331014251.86353-12-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260331014251.86353-1-chang.seok.bae@intel.com> References: <20260331014251.86353-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove it, as there is no more user. Signed-off-by: Chang S. Bae --- arch/x86/include/asm/microcode.h | 10 ---------- arch/x86/kernel/cpu/microcode/core.c | 8 ++------ 2 files changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 62d10c43da9c..a250a8849168 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -81,14 +81,4 @@ static inline u32 intel_get_microcode_revision(void) =20 void microcode_offline_nmi_handler(void); =20 -#ifdef CONFIG_MICROCODE_LATE_LOADING -DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); -static __always_inline bool microcode_nmi_handler_enabled(void) -{ - return static_branch_unlikely(µcode_nmi_handler_enable); -} -#else -static __always_inline bool microcode_nmi_handler_enabled(void) { return f= alse; } -#endif - #endif /* _ASM_X86_MICROCODE_H */ diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index ebcc73e67af1..775233c069c7 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -324,7 +324,6 @@ struct microcode_ctrl { bool nmi_enabled; }; =20 -DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); static atomic_t late_cpus_in, offline_in_nmi; static unsigned int loops_per_usec; @@ -601,13 +600,10 @@ static int load_late_stop_cpus(bool is_safe) */ store_cpu_caps(&prev_info); =20 - if (microcode_ops->use_nmi) { - static_branch_enable_cpuslocked(µcode_nmi_handler_enable); + if (microcode_ops->use_nmi) stop_machine_nmi_cpuslocked(microcode_nmi_handler, NULL, cpu_online_mask= ); - static_branch_disable_cpuslocked(µcode_nmi_handler_enable); - } else { + else stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); - } =20 /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { --=20 2.51.0