From nobody Thu Apr 2 02:40:48 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D0EA271A71 for ; Tue, 31 Mar 2026 02:15:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774923329; cv=none; b=CGX9+uNCf5PWsQa+UvqOCJYlaf9lPveOn3qbMH7Tolk4ubdiV37sCDvO3c5x+fU7l4iS0QyBFgSNDZST5zDB60Soh4lNTchPGbTRnPLlt1gK2bQ8T3M56bQELcxcrfqB+vCDECvxXFEzMd661xTer3lQ/P+9TqIitKYM0g/Wses= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774923329; c=relaxed/simple; bh=Yt3P3BSNSYGhqiOGU8DHhre+e+biKLJ/omkG6TP4WFQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KOSDnfnQ0dKZBqdpfILxpFk9teDBOg70Etmc+AZUrdA9bdDjrmB10prSyBeiLERYLPLau97LIyJW8CmJg4Z6/a2K72WK+5YHKG0Ys2EANOXfxL1SUSIPYlKR7EBb4SEPU3JRn6Ue/AKWqvMaChDkf6+PniiXzjHl64jJ9BnfF3U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OaI22pIr; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OaI22pIr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774923328; x=1806459328; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Yt3P3BSNSYGhqiOGU8DHhre+e+biKLJ/omkG6TP4WFQ=; b=OaI22pIrFWXjSCx30E1V/qzNE46JgQTea7P2pFseQQnye5vUWBVVb2wQ znrnKeZrqytwoNSRCm8/vPYAfbaVfHfoNO57ki8HhAMQ0rZR6NojIE7S+ 0tTv4PexVrAIDl0Xjgwlt5povmUH4b/GJbBlV5a1BYFlNZVc4HfhE3w7t ajo+37YE4wVvPnUWntmWVLN1TVMegtrEOhxhvLYVJB9Gy0vfaGHg5aj9q 3i05LK9yGgv+h4Dvxu6yCKt4YN8wiGc8VLPiViXNaB8qXelvpVuG8usSK eMfhXYvHul1xPE69DZ1kNMDB2Vw6AKlvtew9Q0n4xvtsQqA1tms5VVYDA A==; X-CSE-ConnectionGUID: ZiqF3P1XSkOHH2S0nWF+Ag== X-CSE-MsgGUID: SPtNssMDSEOA8kHXAOglkg== X-IronPort-AV: E=McAfee;i="6800,10657,11744"; a="93508145" X-IronPort-AV: E=Sophos;i="6.23,151,1770624000"; d="scan'208";a="93508145" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2026 19:07:52 -0700 X-CSE-ConnectionGUID: QmyqTaBQS4qhAojc8JWowA== X-CSE-MsgGUID: 7oAwMREMTQWMBF6CubiO0A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,151,1770624000"; d="scan'208";a="221358718" Received: from chang-linux-3.sc.intel.com (HELO chang-linux-3) ([172.25.66.172]) by fmviesa006.fm.intel.com with ESMTP; 30 Mar 2026 19:07:50 -0700 From: "Chang S. Bae" To: linux-kernel@vger.kernel.org Cc: x86@kernel.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, peterz@infradead.org, david.kaplan@amd.com, chang.seok.bae@intel.com Subject: [PATCH v2 09/11] x86/microcode: Use stop-machine NMI facility Date: Tue, 31 Mar 2026 01:42:47 +0000 Message-ID: <20260331014251.86353-10-chang.seok.bae@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260331014251.86353-1-chang.seok.bae@intel.com> References: <20260331014251.86353-1-chang.seok.bae@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The existing NMI-based loading logic explicitly sends NMIs to online CPUs and invokes microcode_update_handler() from the NMI context. The stop-machine NMI variant already provides the mechanism on x86. Replace the custom NMI control logic with stop_machine_nmi_cpuslocked(). Signed-off-by: Chang S. Bae --- V1 -> V2: Select that stop-machine build option --- arch/x86/Kconfig | 1 + arch/x86/include/asm/microcode.h | 1 - arch/x86/kernel/cpu/microcode/core.c | 19 +++---------------- arch/x86/kernel/nmi.c | 3 --- 4 files changed, 4 insertions(+), 20 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0b5f30d769ff..0f7e88ba7433 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1338,6 +1338,7 @@ config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n depends on MICROCODE && SMP + select STOP_MACHINE_NMI help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequen= ce diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 3c317d155771..62d10c43da9c 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -79,7 +79,6 @@ static inline u32 intel_get_microcode_revision(void) } #endif /* !CONFIG_CPU_SUP_INTEL */ =20 -bool microcode_nmi_handler(void); void microcode_offline_nmi_handler(void); =20 #ifdef CONFIG_MICROCODE_LATE_LOADING diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index abd640b1d286..ebcc73e67af1 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -563,22 +563,9 @@ static noinstr int microcode_update_handler(void *unus= ed) * path which must be NMI safe until the primary thread completed the * update. */ -bool noinstr microcode_nmi_handler(void) +static noinstr int microcode_nmi_handler(void *data) { - if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) - return false; - - raw_cpu_write(ucode_ctrl.nmi_enabled, false); - return microcode_update_handler(NULL) =3D=3D 0; -} - -static int stop_cpu_in_nmi(void *unused) -{ - /* Enable the NMI handler and raise NMI */ - this_cpu_write(ucode_ctrl.nmi_enabled, true); - apic->send_IPI(smp_processor_id(), NMI_VECTOR); - - return 0; + return microcode_update_handler(data); } =20 static int load_late_stop_cpus(bool is_safe) @@ -616,7 +603,7 @@ static int load_late_stop_cpus(bool is_safe) =20 if (microcode_ops->use_nmi) { static_branch_enable_cpuslocked(µcode_nmi_handler_enable); - stop_machine_cpuslocked(stop_cpu_in_nmi, NULL, cpu_online_mask); + stop_machine_nmi_cpuslocked(microcode_nmi_handler, NULL, cpu_online_mask= ); static_branch_disable_cpuslocked(µcode_nmi_handler_enable); } else { stop_machine_cpuslocked(microcode_update_handler, NULL, cpu_online_mask); diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c index b7ea2907142c..324f4353be88 100644 --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -386,9 +386,6 @@ static noinstr void default_do_nmi(struct pt_regs *regs) if (stop_machine_nmi_handler()) goto out; =20 - if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) - goto out; - /* * CPU-specific NMI must be processed before non-CPU-specific * NMI, otherwise we may lose it, because the CPU-specific --=20 2.51.0