From nobody Wed Apr 1 13:43:33 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BB2E3C3C1E; Tue, 31 Mar 2026 07:31:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942320; cv=none; b=Gt7XRvBeSKUBK8JWBqn+tSnlLhKwp4Pj5Y+viL95jHqcWD3zB3/6IQLvmAER1mnPZo8YW5jiKMEEoXwX3K4sT1yFYuImsdCvry+dOPZekbF3JlQxbXRUcaTdm95u8VJQkDv9a03W8KNHrmgxPHrpaD3rezFD7qrKSL+pA/VOhCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942320; c=relaxed/simple; bh=e8lq+jY2HQ8zkEhRGvXd0EB5NimGHYNLx+RsdCMXlGY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=tYC4lN1hr3aNfPDvFX8KqknwgN2wZX2yllCH/ausgU5EUisoGQ6alJbOUTWbp7yNmpTZCa5MQmXThStD+/9d8fbiH/ANZZ4ye33Do4i+vqOQuJQILYpx4RlNvZglTFizNLZGtcof+CajEdLsurB4bOkqaS+aY3W+bsH40ihwglg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar 2026 15:31:46 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 31 Mar 2026 15:31:46 +0800 From: Billy Tsai Date: Tue, 31 Mar 2026 15:31:17 +0800 Subject: [PATCH v5 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com> References: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> In-Reply-To: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> To: Lee Jones , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Joel Stanley" , Andrew Jeffery , "Linus Walleij" , Billy Tsai , "Bartosz Golaszewski" , Ryan Chen CC: Andrew Jeffery , , , , , , , X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774942306; l=5430; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=e8lq+jY2HQ8zkEhRGvXd0EB5NimGHYNLx+RsdCMXlGY=; b=U6PvlIaG6lQgky0Cd+1D873t79J5YadAVzAkpw/hYzf/1pEAbOoJr6JobnLw7SGZf/5sZvDw7 om5Tqd2kJM0Ckvw4eClyvtL0bhcJ/KOtvDn2QucSBCLPPxW4FNg3bND X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= AST2700 consists of two interconnected SoC instances, each with its own System Control Unit (SCU). The SCU0 provides pin control, interrupt controllers, clocks, resets, and address-space mappings for the Secondary and Tertiary Service Processors (SSP and TSP). Describe the SSP/TSP address mappings using the standard memory-region and memory-region-names properties. Disallow legacy child nodes that are not present on AST2700, including p2a-control and smp-memram. The latter is unnecessary as software can access the scratch registers via the SCU syscon. Also allow the AST2700 SoC0 pin controller to be described as a child node of the SCU0, and add an example illustrating the SCU0 layout, including reserved-memory, interrupt controllers, and pinctrl. Signed-off-by: Billy Tsai --- .../bindings/mfd/aspeed,ast2x00-scu.yaml | 117 +++++++++++++++++= ++++ 1 file changed, 117 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml = b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index a87f31fce019..86d51389689c 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -46,6 +46,9 @@ properties: '#reset-cells': const: 1 =20 + memory-region: true + memory-region-names: true + patternProperties: '^p2a-control@[0-9a-f]+$': description: > @@ -87,6 +90,7 @@ patternProperties: - aspeed,ast2400-pinctrl - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl + - aspeed,ast2700-soc0-pinctrl =20 required: - compatible @@ -156,6 +160,42 @@ required: - '#clock-cells' - '#reset-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + anyOf: + - const: aspeed,ast2700-scu0 + - const: aspeed,ast2700-scu1 + then: + patternProperties: + '^p2a-control@[0-9a-f]+$': false + '^smp-memram@[0-9a-f]+$': false + + - if: + properties: + compatible: + contains: + const: aspeed,ast2700-scu0 + then: + properties: + memory-region: + items: + - description: Region mapped through the first SSP address win= dow. + - description: Region mapped through the second SSP address wi= ndow. + - description: Region mapped through the TSP address window. + + memory-region-names: + items: + - const: ssp-0 + - const: ssp-1 + - const: tsp + else: + properties: + memory-region: false + memory-region-names: false + additionalProperties: false =20 examples: @@ -180,4 +220,81 @@ examples: reg =3D <0x7c 0x4>, <0x150 0x8>; }; }; + + - | + / { + #address-cells =3D <2>; + #size-cells =3D <2>; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ssp_region_0: memory@400000000 { + reg =3D <0x4 0x00000000 0x0 0x01000000>; + no-map; + }; + + ssp_region_1: memory@401000000 { + reg =3D <0x4 0x01000000 0x0 0x01000000>; + no-map; + }; + + tsp_region: memory@402000000 { + reg =3D <0x4 0x02000000 0x0 0x01000000>; + no-map; + }; + }; + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mf= d"; + reg =3D <0 0x12c02000 0 0x1000>; + ranges =3D <0x0 0x0 0x12c02000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + memory-region =3D <&ssp_region_0>, <&ssp_region_1>, + <&tsp_region>; + memory-region-names =3D "ssp-0", "ssp-1", "tsp"; + + silicon-id@0 { + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,si= licon-id"; + reg =3D <0x0 0x4>; + }; + + interrupt-controller@1b0 { + compatible =3D "aspeed,ast2700-scu-ic0"; + reg =3D <0x1b0 0x4>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc0 97>; + interrupt-controller; + }; + + interrupt-controller@1e0 { + compatible =3D "aspeed,ast2700-scu-ic1"; + reg =3D <0x1e0 0x4>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc0 98>; + interrupt-controller; + }; + + pinctrl@400 { + compatible =3D "aspeed,ast2700-soc0-pinctrl"; + reg =3D <0x400 0x318>; + emmc-state { + function =3D "EMMC"; + groups =3D "EMMCG1"; + }; + }; + }; + }; + }; + ... --=20 2.34.1