From nobody Wed Apr 1 12:32:18 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55BD33C2773; Tue, 31 Mar 2026 07:31:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942319; cv=none; b=CGvM+xBZ8mz1+m6gBafAOgzYYGrUFVdhM2gBCWe7R4hX3Bzc/eCEuNXUkwqJJx0/NOPVU2trryVQmA0WCYJojataKmmhUTf3ncBp18UBC7kINtR09X+iMUS4THVXX9xqH0rZVBxVxa+KRR1m3VFzd3X4in+0Jp+oTZKHDz7EThM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942319; c=relaxed/simple; bh=bWZGEQzcis93YyG/nQE6y8IHuUh8wkmOSEqhb3z4vfk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gqxidq5qBbCXeyhDbCcyx6WExGrnHUWvH9A9d9FV/yQjbWt4aMIRFBQ0iwrDc6HuugWOCinxkzpXzWpxT+dn0wnsnE7us+AFDWzi6Q9/QLAvUQSnEWAQ2lPk0rkatbIKOy6yOf+9L5dGKxsL07pB3ZA8s56THWe2bR3PKmtO7Ww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 31 Mar 2026 15:31:46 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 31 Mar 2026 15:31:46 +0800 From: Billy Tsai Date: Tue, 31 Mar 2026 15:31:16 +0800 Subject: [PATCH v5 1/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260331-upstream_pinctrl-v5-1-8994f59ff367@aspeedtech.com> References: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> In-Reply-To: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> To: Lee Jones , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Joel Stanley" , Andrew Jeffery , "Linus Walleij" , Billy Tsai , "Bartosz Golaszewski" , Ryan Chen CC: Andrew Jeffery , , , , , , , X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774942306; l=4551; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=bWZGEQzcis93YyG/nQE6y8IHuUh8wkmOSEqhb3z4vfk=; b=EQ6XwXrEWYIZRVjFhEGY/pl4CxXxlSAhJ+JUgdapBUUC24eLxq4zkN+j404Nyya/EC4CI70C7 UyYXjt3SoajDGQTFI/s4J2IWc/FgxNGq1rvmPGWRHFZxmRoJMIMyuQT X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add a device tree binding for the pin controller found in the ASPEED AST2700 SoC0. The controller manages various peripheral functions such as eMMC, USB, VGA DDC, JTAG, and PCIe root complex signals. Describe the AST2700 SoC0 pin controller using standard pin multiplexing and configuration properties. Signed-off-by: Billy Tsai --- .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 161 +++++++++++++++++= ++++ 1 file changed, 161 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-= pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc= 0-pinctrl.yaml new file mode 100644 index 000000000000..e43a658fe02b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl= .yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC0 Pin Controller + +maintainers: + - Billy Tsai + +description: + The AST2700 features a dual-SoC architecture with two interconnected SoC= s, + each having its own System Control Unit (SCU) for independent pin contro= l. + This pin controller manages the pin multiplexing for SoC0. + + The SoC0 pin controller manages pin functions including eMMC, VGA DDC, + dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces. + +properties: + compatible: + const: aspeed,ast2700-soc0-pinctrl + reg: + maxItems: 1 + +patternProperties: + '-state$': + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + additionalProperties: false + + properties: + function: + enum: + - EMMC + - JTAGDDR + - JTAGM0 + - JTAGPCIEA + - JTAGPCIEB + - JTAGPSP + - JTAGSSP + - JTAGTSP + - JTAGUSB3A + - JTAGUSB3B + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2AD0 + - USB2AD1 + - USB2AH + - USB2AHP + - USB2AHPD0 + - USB2AXH + - USB2AXH2B + - USB2AXHD1 + - USB2AXHP + - USB2AXHP2B + - USB2AXHPD1 + - USB2BD0 + - USB2BD1 + - USB2BH + - USB2BHP + - USB2BHPD0 + - USB2BXH + - USB2BXH2A + - USB2BXHD1 + - USB2BXHP + - USB2BXHP2A + - USB2BXHPD1 + - USB3AXH + - USB3AXH2B + - USB3AXHD + - USB3AXHP + - USB3AXHP2B + - USB3AXHPD + - USB3BXH + - USB3BXH2A + - USB3BXHD + - USB3BXHP + - USB3BXHP2A + - USB3BXHPD + - VB + - VGADDC + + groups: + enum: + - EMMCCDN + - EMMCG1 + - EMMCG4 + - EMMCG8 + - EMMCWPN + - JTAG0 + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2A + - USB2AAP + - USB2ABP + - USB2ADAP + - USB2AH + - USB2AHAP + - USB2B + - USB2BAP + - USB2BBP + - USB2BDBP + - USB2BH + - USB2BHBP + - USB3A + - USB3AAP + - USB3ABP + - USB3B + - USB3BAP + - USB3BBP + - VB0 + - VB1 + - VGADDC + pins: + enum: + - AB13 + - AB14 + - AC13 + - AC14 + - AD13 + - AD14 + - AE13 + - AE14 + - AE15 + - AF13 + - AF14 + - AF15 + + drive-strength: + enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible =3D "aspeed,ast2700-soc0-pinctrl"; + reg =3D <0x400 0x318>; + emmc-state { + function =3D "EMMC"; + groups =3D "EMMCG1"; + }; + }; --=20 2.34.1 From nobody Wed Apr 1 12:32:18 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BB2E3C3C1E; Tue, 31 Mar 2026 07:31:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942320; cv=none; b=Gt7XRvBeSKUBK8JWBqn+tSnlLhKwp4Pj5Y+viL95jHqcWD3zB3/6IQLvmAER1mnPZo8YW5jiKMEEoXwX3K4sT1yFYuImsdCvry+dOPZekbF3JlQxbXRUcaTdm95u8VJQkDv9a03W8KNHrmgxPHrpaD3rezFD7qrKSL+pA/VOhCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942320; c=relaxed/simple; bh=e8lq+jY2HQ8zkEhRGvXd0EB5NimGHYNLx+RsdCMXlGY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260331-upstream_pinctrl-v5-2-8994f59ff367@aspeedtech.com> References: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> In-Reply-To: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> To: Lee Jones , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Joel Stanley" , Andrew Jeffery , "Linus Walleij" , Billy Tsai , "Bartosz Golaszewski" , Ryan Chen CC: Andrew Jeffery , , , , , , , X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774942306; l=5430; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=e8lq+jY2HQ8zkEhRGvXd0EB5NimGHYNLx+RsdCMXlGY=; b=U6PvlIaG6lQgky0Cd+1D873t79J5YadAVzAkpw/hYzf/1pEAbOoJr6JobnLw7SGZf/5sZvDw7 om5Tqd2kJM0Ckvw4eClyvtL0bhcJ/KOtvDn2QucSBCLPPxW4FNg3bND X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= AST2700 consists of two interconnected SoC instances, each with its own System Control Unit (SCU). The SCU0 provides pin control, interrupt controllers, clocks, resets, and address-space mappings for the Secondary and Tertiary Service Processors (SSP and TSP). Describe the SSP/TSP address mappings using the standard memory-region and memory-region-names properties. Disallow legacy child nodes that are not present on AST2700, including p2a-control and smp-memram. The latter is unnecessary as software can access the scratch registers via the SCU syscon. Also allow the AST2700 SoC0 pin controller to be described as a child node of the SCU0, and add an example illustrating the SCU0 layout, including reserved-memory, interrupt controllers, and pinctrl. Signed-off-by: Billy Tsai --- .../bindings/mfd/aspeed,ast2x00-scu.yaml | 117 +++++++++++++++++= ++++ 1 file changed, 117 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml = b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index a87f31fce019..86d51389689c 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -46,6 +46,9 @@ properties: '#reset-cells': const: 1 =20 + memory-region: true + memory-region-names: true + patternProperties: '^p2a-control@[0-9a-f]+$': description: > @@ -87,6 +90,7 @@ patternProperties: - aspeed,ast2400-pinctrl - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl + - aspeed,ast2700-soc0-pinctrl =20 required: - compatible @@ -156,6 +160,42 @@ required: - '#clock-cells' - '#reset-cells' =20 +allOf: + - if: + properties: + compatible: + contains: + anyOf: + - const: aspeed,ast2700-scu0 + - const: aspeed,ast2700-scu1 + then: + patternProperties: + '^p2a-control@[0-9a-f]+$': false + '^smp-memram@[0-9a-f]+$': false + + - if: + properties: + compatible: + contains: + const: aspeed,ast2700-scu0 + then: + properties: + memory-region: + items: + - description: Region mapped through the first SSP address win= dow. + - description: Region mapped through the second SSP address wi= ndow. + - description: Region mapped through the TSP address window. + + memory-region-names: + items: + - const: ssp-0 + - const: ssp-1 + - const: tsp + else: + properties: + memory-region: false + memory-region-names: false + additionalProperties: false =20 examples: @@ -180,4 +220,81 @@ examples: reg =3D <0x7c 0x4>, <0x150 0x8>; }; }; + + - | + / { + #address-cells =3D <2>; + #size-cells =3D <2>; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ssp_region_0: memory@400000000 { + reg =3D <0x4 0x00000000 0x0 0x01000000>; + no-map; + }; + + ssp_region_1: memory@401000000 { + reg =3D <0x4 0x01000000 0x0 0x01000000>; + no-map; + }; + + tsp_region: memory@402000000 { + reg =3D <0x4 0x02000000 0x0 0x01000000>; + no-map; + }; + }; + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + syscon@12c02000 { + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mf= d"; + reg =3D <0 0x12c02000 0 0x1000>; + ranges =3D <0x0 0x0 0x12c02000 0x1000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + + memory-region =3D <&ssp_region_0>, <&ssp_region_1>, + <&tsp_region>; + memory-region-names =3D "ssp-0", "ssp-1", "tsp"; + + silicon-id@0 { + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,si= licon-id"; + reg =3D <0x0 0x4>; + }; + + interrupt-controller@1b0 { + compatible =3D "aspeed,ast2700-scu-ic0"; + reg =3D <0x1b0 0x4>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc0 97>; + interrupt-controller; + }; + + interrupt-controller@1e0 { + compatible =3D "aspeed,ast2700-scu-ic1"; + reg =3D <0x1e0 0x4>; + #interrupt-cells =3D <1>; + interrupts-extended =3D <&intc0 98>; + interrupt-controller; + }; + + pinctrl@400 { + compatible =3D "aspeed,ast2700-soc0-pinctrl"; + reg =3D <0x400 0x318>; + emmc-state { + function =3D "EMMC"; + groups =3D "EMMCG1"; + }; + }; + }; + }; + }; + ... --=20 2.34.1 From nobody Wed Apr 1 12:32:18 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 162543C9431; Tue, 31 Mar 2026 07:32:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774942323; cv=none; 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Tue, 31 Mar 2026 15:31:46 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Tue, 31 Mar 2026 15:31:46 +0800 From: Billy Tsai Date: Tue, 31 Mar 2026 15:31:18 +0800 Subject: [PATCH v5 3/3] pinctrl: aspeed: Add AST2700 SoC0 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260331-upstream_pinctrl-v5-3-8994f59ff367@aspeedtech.com> References: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> In-Reply-To: <20260331-upstream_pinctrl-v5-0-8994f59ff367@aspeedtech.com> To: Lee Jones , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Joel Stanley" , Andrew Jeffery , "Linus Walleij" , Billy Tsai , "Bartosz Golaszewski" , Ryan Chen CC: Andrew Jeffery , , , , , , , X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774942306; l=32567; i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id; bh=HG077U9u5x9WY8NwfGaSNNsie08HwZMlYJDUDn5neCo=; b=kbz5R1LvqTV6q15G6ZgH2z/WasUcIRU7ibzv8vTVwtJRgxCDI0Q5UnzmjvkPieP3t1xSdruf8 5/MZp8eW0X4AHWDw+m1z3bhau0K1hryk60CyHvYsInPiR/K45NwqBvz X-Developer-Key: i=billy_tsai@aspeedtech.com; a=ed25519; pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ= Add pinctrl support for the SoC0 instance of the ASPEED AST2700. AST2700 consists of two interconnected SoC instances, each with its own pinctrl register block. The SoC0 pinctrl hardware closely follows the design found in previous ASPEED BMC generations, allowing the driver to build upon the common ASPEED pinctrl infrastructure. Signed-off-by: Billy Tsai --- drivers/pinctrl/aspeed/Kconfig | 9 + drivers/pinctrl/aspeed/Makefile | 1 + drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 710 ++++++++++++++++++++= ++++ 3 files changed, 720 insertions(+) diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 1a4e5b9ed471..f9672cca891e 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -31,3 +31,12 @@ config PINCTRL_ASPEED_G6 help Say Y here to enable pin controller support for Aspeed's 6th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G7_SOC0 + bool "Aspeed G7 SoC pin control" + depends on (ARCH_ASPEED || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for the SoC0 instance + of Aspeed's 7th generation SoCs. GPIO is provided by a separate + GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makef= ile index db2a7600ae2b..0de524ca2c72 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_ASPEED) +=3D pinctrl-aspeed.o pinmux-a= speed.o obj-$(CONFIG_PINCTRL_ASPEED_G4) +=3D pinctrl-aspeed-g4.o obj-$(CONFIG_PINCTRL_ASPEED_G5) +=3D pinctrl-aspeed-g5.o obj-$(CONFIG_PINCTRL_ASPEED_G6) +=3D pinctrl-aspeed-g6.o +obj-$(CONFIG_PINCTRL_ASPEED_G7_SOC0) +=3D pinctrl-aspeed-g7-soc0.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/drivers/pinc= trl/aspeed/pinctrl-aspeed-g7-soc0.c new file mode 100644 index 000000000000..b1a09db65635 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-aspeed.h" +#include "pinmux-aspeed.h" +#include "../pinctrl-utils.h" + +#define SCU200 0x200 /* System Reset Control #1 */ + +#define SCU010 0x010 /* Hardware Strap Register */ +#define SCU400 0x400 /* Multi-function Pin Control #1 */ +#define SCU404 0x404 /* Multi-function Pin Control #2 */ +#define SCU408 0x408 /* Multi-function Pin Control #3 */ +#define SCU40C 0x40C /* Multi-function Pin Control #3 */ +#define SCU410 0x410 /* USB Multi-function Control Register */ +#define SCU414 0x414 /* VGA Function Control Register */ + +#define SCU480 0x480 /* GPIO18A0 IO Control Register */ +#define SCU484 0x484 /* GPIO18A1 IO Control Register */ +#define SCU488 0x488 /* GPIO18A2 IO Control Register */ +#define SCU48C 0x48c /* GPIO18A3 IO Control Register */ +#define SCU490 0x490 /* GPIO18A4 IO Control Register */ +#define SCU494 0x494 /* GPIO18A5 IO Control Register */ +#define SCU498 0x498 /* GPIO18A6 IO Control Register */ +#define SCU49C 0x49c /* GPIO18A7 IO Control Register */ +#define SCU4A0 0x4A0 /* GPIO18B0 IO Control Register */ +#define SCU4A4 0x4A4 /* GPIO18B1 IO Control Register */ +#define SCU4A8 0x4A8 /* GPIO18B2 IO Control Register */ +#define SCU4AC 0x4AC /* GPIO18B3 IO Control Register */ + +enum { + AC14, + AE15, + AD14, + AE14, + AF14, + AB13, + AB14, + AF15, + AF13, + AC13, + AD13, + AE13, + JTAG_PORT, + PCIERC0_PERST, + PCIERC1_PERST, + PORTA_MODE, + PORTA_U2, + PORTB_MODE, + PORTB_U2, + PORTA_U2_PHY, + PORTB_U2_PHY, + PORTA_U3, + PORTB_U3, + PORTA_U3_PHY, + PORTB_U3_PHY, +}; + +SIG_EXPR_LIST_DECL_SEMG(AC14, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, = 0)); +SIG_EXPR_LIST_DECL_SESG(AC14, VB1CS, VB1, SIG_DESC_SET(SCU404, 0)); +PIN_DECL_2(AC14, GPIO18A0, EMMCCLK, VB1CS); + +SIG_EXPR_LIST_DECL_SEMG(AE15, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, = 1)); +SIG_EXPR_LIST_DECL_SESG(AE15, VB1CK, VB1, SIG_DESC_SET(SCU404, 1)); +PIN_DECL_2(AE15, GPIO18A1, EMMCCMD, VB1CK); + +SIG_EXPR_LIST_DECL_SEMG(AD14, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400,= 2)); +SIG_EXPR_LIST_DECL_SESG(AD14, VB1MOSI, VB1, SIG_DESC_SET(SCU404, 2)); +PIN_DECL_2(AD14, GPIO18A2, EMMCDAT0, VB1MOSI); + +SIG_EXPR_LIST_DECL_SEMG(AE14, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400,= 3)); +SIG_EXPR_LIST_DECL_SESG(AE14, VB1MISO, VB1, SIG_DESC_SET(SCU404, 3)); +PIN_DECL_2(AE14, GPIO18A3, EMMCDAT1, VB1MISO); + +SIG_EXPR_LIST_DECL_SEMG(AF14, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400,= 4)); +PIN_DECL_1(AF14, GPIO18A4, EMMCDAT2); + +SIG_EXPR_LIST_DECL_SEMG(AB13, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400,= 5)); +PIN_DECL_1(AB13, GPIO18A5, EMMCDAT3); + +SIG_EXPR_LIST_DECL_SEMG(AB14, EMMCCDN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, = 6)); +SIG_EXPR_LIST_DECL_SESG(AB14, VB0CS, VB0, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_2(AB14, GPIO18A6, EMMCCDN, VB0CS); + +SIG_EXPR_LIST_DECL_SEMG(AF15, EMMCWPN, EMMCG1, EMMC, SIG_DESC_SET(SCU400, = 7)); +SIG_EXPR_LIST_DECL_SESG(AF15, VB0CK, VB0, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_2(AF15, GPIO18A7, EMMCWPN, VB0CK); + +SIG_EXPR_LIST_DECL_SESG(AF13, TSPRSTN, TSPRSTN, SIG_DESC_SET(SCU010, 9)); +SIG_EXPR_LIST_DECL_SEMG(AF13, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU400,= 8)); +SIG_EXPR_LIST_DECL_SESG(AF13, VB0MOSI, VB0, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_3(AF13, GPIO18B0, TSPRSTN, EMMCDAT4, VB0MOSI); + +SIG_EXPR_LIST_DECL_SESG(AC13, UFSCLKI, UFSCLKI, SIG_DESC_SET(SCU010, 19)); +SIG_EXPR_LIST_DECL_SEMG(AC13, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU400,= 9)); +SIG_EXPR_LIST_DECL_SESG(AC13, VB0MISO, VB0, SIG_DESC_SET(SCU010, 17)); +PIN_DECL_3(AC13, GPIO18B1, UFSCLKI, EMMCDAT5, VB0MISO); + +SIG_EXPR_LIST_DECL_SEMG(AD13, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU400,= 10)); +SIG_EXPR_LIST_DECL_SESG(AD13, DDCCLK, VGADDC, SIG_DESC_SET(SCU404, 10)); +PIN_DECL_2(AD13, GPIO18B2, EMMCDAT6, DDCCLK); + +SIG_EXPR_LIST_DECL_SEMG(AE13, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU400,= 11)); +SIG_EXPR_LIST_DECL_SESG(AE13, DDCDAT, VGADDC, SIG_DESC_SET(SCU404, 11)); +PIN_DECL_2(AE13, GPIO18B3, EMMCDAT7, DDCDAT); + +GROUP_DECL(EMMCG1, AC14, AE15, AD14); +GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13); +GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD13, A= E13); +GROUP_DECL(EMMCWPN, AF15); +GROUP_DECL(EMMCCDN, AB14); +FUNC_DECL_(EMMC, "EMMCG1", "EMMCG4", "EMMCG8", "EMMCWPN", "EMMCCDN"); + +GROUP_DECL(VB1, AC14, AE15, AD14, AE14); +GROUP_DECL(VB0, AF15, AB14, AF13, AC13); +FUNC_DECL_2(VB, VB1, VB0); + +FUNC_GROUP_DECL(TSPRSTN, AF13); + +FUNC_GROUP_DECL(UFSCLKI, AC13); + +FUNC_GROUP_DECL(VGADDC, AD13, AE13); + +/* JTAG Port Selection */ +#define JTAG_PORT_PSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x0,= 0 } +#define JTAG_PORT_SSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x41= , 0 } +#define JTAG_PORT_TSP_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x42= , 0 } +#define JTAG_PORT_DDR_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x43= , 0 } +#define JTAG_PORT_USB3A_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x44= , 0 } +#define JTAG_PORT_USB3B_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x45= , 0 } +#define JTAG_PORT_PCIEA_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x46= , 0 } +#define JTAG_PORT_PCIEB_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x47= , 0 } +#define JTAG_PORT_JTAGM0_DESC { ASPEED_IP_SCU, SCU408, GENMASK(12, 5), 0x8= , 0 } + +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPSP, JTAG0, JTAGPSP, JTAG_PORT_PSP_= DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGSSP, JTAG0, JTAGSSP, JTAG_PORT_SSP_= DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGTSP, JTAG0, JTAGTSP, JTAG_PORT_TSP_= DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGDDR, JTAG0, JTAGDDR, JTAG_PORT_DDR_= DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3A, JTAG0, JTAGUSB3A, JTAG_PORT_= USB3A_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGUSB3B, JTAG0, JTAGUSB3B, JTAG_PORT_= USB3B_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEA, JTAG0, JTAGPCIEA, JTAG_PORT_= PCIEA_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGPCIEB, JTAG0, JTAGPCIEB, JTAG_PORT_= PCIEB_DESC); +SIG_EXPR_LIST_DECL_SEMG(JTAG_PORT, JTAGM0, JTAG0, JTAGM0, JTAG_PORT_JTAGM0= _DESC); +PIN_DECL_(JTAG_PORT, SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPSP), SIG_EXPR_LIST_= PTR(JTAG_PORT, JTAGSSP), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGTSP), SIG_EXPR_LIST_PTR(JTAG_PORT, JTA= GDDR), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGUSB3A), SIG_EXPR_LIST_PTR(JTAG_PORT, J= TAGUSB3B), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGPCIEA), SIG_EXPR_LIST_PTR(JTAG_PORT, J= TAGPCIEB), + SIG_EXPR_LIST_PTR(JTAG_PORT, JTAGM0)); + +GROUP_DECL(JTAG0, JTAG_PORT); + +FUNC_DECL_1(JTAGPSP, JTAG0); +FUNC_DECL_1(JTAGSSP, JTAG0); +FUNC_DECL_1(JTAGTSP, JTAG0); +FUNC_DECL_1(JTAGDDR, JTAG0); +FUNC_DECL_1(JTAGUSB3A, JTAG0); +FUNC_DECL_1(JTAGUSB3B, JTAG0); +FUNC_DECL_1(JTAGPCIEA, JTAG0); +FUNC_DECL_1(JTAGPCIEB, JTAG0); +FUNC_DECL_1(JTAGM0, JTAG0); + +/* PCIe Reset Control */ +SIG_EXPR_LIST_DECL_SESG(PCIERC0_PERST, PCIERC0PERST, PCIERC0PERST, SIG_DES= C_SET(SCU200, 21)); +PIN_DECL_(PCIERC0_PERST, SIG_EXPR_LIST_PTR(PCIERC0_PERST, PCIERC0PERST)); +FUNC_GROUP_DECL(PCIERC0PERST, PCIERC0_PERST); + +SIG_EXPR_LIST_DECL_SESG(PCIERC1_PERST, PCIERC1PERST, PCIERC1PERST, SIG_DES= C_SET(SCU200, 19)); +PIN_DECL_(PCIERC1_PERST, SIG_EXPR_LIST_PTR(PCIERC1_PERST, PCIERC1PERST)); +FUNC_GROUP_DECL(PCIERC1PERST, PCIERC1_PERST); + +#define PORTA_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 0, = 0 } +#define PORTA_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 1, = 0 } +#define PORTA_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 2, = 0 } +#define PORTA_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(25, 24), 3,= 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHPD0, USB2AH, USB2AHPD0, PORTA_MO= DE_HPD0_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AH, USB2AHAP, USB2AH, PORTA_MODE_H= _DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AHP, USB2AHAP, USB2AHP, PORTA_MODE= _HP_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTA_MODE, USB2AD0, USB2AHAP, USB2AD0, PORTA_MODE= _D0_DESC); +PIN_DECL_(PORTA_MODE, SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AHPD0), + SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AH), SIG_EXPR_LIST_PTR(PORTA_MODE, US= B2AHP), + SIG_EXPR_LIST_PTR(PORTA_MODE, USB2AD0)); + +#define PORTA_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 0, 0 } +#define PORTA_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 1, 0 } +#define PORTA_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 2, 0 } +#define PORTA_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(3, 2), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHD1, USB2A, USB2AXHD1, PORTA_U2_XH= D_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHPD1, USB2A, USB2AXHPD1, PORTA_U2_= XHD_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH, USB2AAP, USB2AXH, PORTA_U2_XH_D= ESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP, USB2AAP, USB2AXHP, PORTA_U2_XH= _DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXH2B, USB2ABP, USB2AXH2B, PORTA_U2_= XH2E_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AXHP2B, USB2ABP, USB2AXHP2B, PORTA_U= 2_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U2, USB2AD1, USB2ADAP, USB2AD1, PORTA_U2_D1_= DESC); +PIN_DECL_(PORTA_U2, SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXHD1), SIG_EXPR_LIST_= PTR(PORTA_U2, USB2AXHPD1), + SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH), SIG_EXPR_LIST_PTR(PORTA_U2, USB2A= XHP), + SIG_EXPR_LIST_PTR(PORTA_U2, USB2AXH2B), SIG_EXPR_LIST_PTR(PORTA_U2, USB= 2AXHP2B), + SIG_EXPR_LIST_PTR(PORTA_U2, USB2AD1)); + +#define PORTB_MODE_HPD0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 0, = 0 } +#define PORTB_MODE_D0_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 1, = 0 } +#define PORTB_MODE_H_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 2, = 0 } +#define PORTB_MODE_HP_DESC { ASPEED_IP_SCU, SCU410, GENMASK(29, 28), 3,= 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHPD0, USB2BH, USB2BHPD0, PORTB_MO= DE_HPD0_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BH, USB2BHBP, USB2BH, PORTB_MODE_H= _DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BHP, USB2BHBP, USB2BHP, PORTB_MODE= _HP_DESC); +SIG_EXPR_LIST_DECL_SEMG(PORTB_MODE, USB2BD0, USB2BHBP, USB2BD0, PORTB_MODE= _D0_DESC); +PIN_DECL_(PORTB_MODE, SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BHPD0), + SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BH), SIG_EXPR_LIST_PTR(PORTB_MODE, US= B2BHP), + SIG_EXPR_LIST_PTR(PORTB_MODE, USB2BD0)); + +#define PORTB_U2_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 0, 0 } +#define PORTB_U2_D1_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 1, 0 } +#define PORTB_U2_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 2, 0 } +#define PORTB_U2_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(7, 6), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHD1, USB2B, USB2BXHD1, PORTB_U2_XH= D_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHPD1, USB2B, USB2BXHPD1, PORTB_U2_= XHD_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH, USB2BBP, USB2BXH, PORTB_U2_XHD_= DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP, USB2BBP, USB2BXHP, PORTB_U2_XH= D_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXH2A, USB2BAP, USB2BXH2A, PORTB_U2_= XH2E_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BXHP2A, USB2BAP, USB2BXHP2A, PORTB_U= 2_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U2, USB2BD1, USB2BDBP, USB2BD1, PORTB_U2_D1_= DESC); +PIN_DECL_(PORTB_U2, SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXHD1), SIG_EXPR_LIST_= PTR(PORTB_U2, USB2BXHPD1), + SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH), SIG_EXPR_LIST_PTR(PORTB_U2, USB2B= XHP), + SIG_EXPR_LIST_PTR(PORTB_U2, USB2BXH2A), SIG_EXPR_LIST_PTR(PORTB_U2, USB= 2BXHP2A), + SIG_EXPR_LIST_PTR(PORTB_U2, USB2BD1)); +/* + * USB2 virtual PHY pins. + * + * PORTA_U2_PHY and PORTB_U2_PHY are logical endpoints, not package pins. + * They alias existing USB2 expressions so pin groups can model direct and + * cross-coupled routing for host and mode paths. + * + * - USB2AAP/USB2ADAP/USB2AHAP: use PORTA_U2_PHY + * - USB2ABP : use PORTB_U2_PHY + * - USB2BBP/USB2BDBP/USB2BHBP: use PORTB_U2_PHY + * - USB2BAP : use PORTA_U2_PHY + * + * They do not have any registers to configure this behaviour; the goal is + * simply for the driver to prevent conflicting selections. For example, + * selecting group USB2ABP and USB2BBP at the same time should not be + * allowed. + */ +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXH, USB2AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AXHP, USB2AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXH2A, USB2BAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2BXHP2A, USB2BAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD1, USB2ADAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AH, USB2AHAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AHP, USB2AHAP); +SIG_EXPR_LIST_ALIAS(PORTA_U2_PHY, USB2AD0, USB2AHAP); +PIN_DECL_(PORTA_U2_PHY, SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXH), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AXHP), SIG_EXPR_LIST_PTR(PORTA_U2_P= HY, USB2BXH2A), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2BXHP2A), SIG_EXPR_LIST_PTR(PORTA_U2= _PHY, USB2AD1), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AH), SIG_EXPR_LIST_PTR(PORTA_U2_PHY= , USB2AHP), + SIG_EXPR_LIST_PTR(PORTA_U2_PHY, USB2AD0)); + +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXH2B, USB2ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2AXHP2B, USB2ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXH, USB2BBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BXHP, USB2BBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD1, USB2BDBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BH, USB2BHBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BHP, USB2BHBP); +SIG_EXPR_LIST_ALIAS(PORTB_U2_PHY, USB2BD0, USB2BHBP); +PIN_DECL_(PORTB_U2_PHY, SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXH2B), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U2= _PHY, USB2BXH), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BXHP), SIG_EXPR_LIST_PTR(PORTB_U2_P= HY, USB2BD1), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BH), SIG_EXPR_LIST_PTR(PORTB_U2_PHY= , USB2BHP), + SIG_EXPR_LIST_PTR(PORTB_U2_PHY, USB2BD0)); + +GROUP_DECL(USB2A, PORTA_U2); +GROUP_DECL(USB2AAP, PORTA_U2, PORTA_U2_PHY); +GROUP_DECL(USB2ABP, PORTA_U2, PORTB_U2_PHY); +GROUP_DECL(USB2ADAP, PORTA_U2, PORTA_U2_PHY); +GROUP_DECL(USB2AH, PORTA_MODE); +GROUP_DECL(USB2AHAP, PORTA_MODE, PORTA_U2_PHY); + +FUNC_DECL_1(USB2AXHD1, USB2A); +FUNC_DECL_1(USB2AXHPD1, USB2A); +FUNC_DECL_1(USB2AXH, USB2AAP); +FUNC_DECL_1(USB2AXHP, USB2AAP); +FUNC_DECL_1(USB2AXH2B, USB2ABP); +FUNC_DECL_1(USB2AXHP2B, USB2ABP); +FUNC_DECL_1(USB2AD1, USB2ADAP); +FUNC_DECL_1(USB2AHPD0, USB2AH); +FUNC_DECL_1(USB2AH, USB2AHAP); +FUNC_DECL_1(USB2AHP, USB2AHAP); +FUNC_DECL_1(USB2AD0, USB2AHAP); + +GROUP_DECL(USB2B, PORTB_U2); +GROUP_DECL(USB2BBP, PORTB_U2, PORTB_U2_PHY); +GROUP_DECL(USB2BAP, PORTB_U2, PORTA_U2_PHY); +GROUP_DECL(USB2BDBP, PORTB_U2, PORTB_U2_PHY); +GROUP_DECL(USB2BH, PORTB_MODE); +GROUP_DECL(USB2BHBP, PORTB_MODE, PORTB_U2_PHY); + +FUNC_DECL_1(USB2BXHD1, USB2B); +FUNC_DECL_1(USB2BXHPD1, USB2B); +FUNC_DECL_1(USB2BXH, USB2BBP); +FUNC_DECL_1(USB2BXHP, USB2BBP); +FUNC_DECL_1(USB2BXH2A, USB2BAP); +FUNC_DECL_1(USB2BXHP2A, USB2BAP); +FUNC_DECL_1(USB2BD1, USB2BDBP); +FUNC_DECL_1(USB2BHPD0, USB2BH); +FUNC_DECL_1(USB2BH, USB2BHBP); +FUNC_DECL_1(USB2BHP, USB2BHBP); +FUNC_DECL_1(USB2BD0, USB2BHBP); + +#define PORTA_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 0, 0 } +#define PORTA_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 2, 0 } +#define PORTA_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(1, 0), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHD, USB3A, USB3AXHD, PORTA_U3_XHD_= DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHPD, USB3A, USB3AXHPD, PORTA_U3_XH= D_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH, USB3AAP, USB3AXH, PORTA_U3_XH_D= ESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP, USB3AAP, USB3AXHP, PORTA_U3_XH= _DESC, + SIG_DESC_CLEAR(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXH2B, USB3ABP, USB3AXH2B, PORTA_U3_= XH2E_DESC, + SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SEMG(PORTA_U3, USB3AXHP2B, USB3ABP, USB3AXHP2B, PORTA_U= 3_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 9)); +PIN_DECL_(PORTA_U3, SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXHD), SIG_EXPR_LIST_P= TR(PORTA_U3, USB3AXHPD), + SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH), SIG_EXPR_LIST_PTR(PORTA_U3, USB3A= XHP), + SIG_EXPR_LIST_PTR(PORTA_U3, USB3AXH2B), SIG_EXPR_LIST_PTR(PORTA_U3, USB= 3AXHP2B)); + +#define PORTB_U3_XHD_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 0, 0 } +#define PORTB_U3_XH_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 2, 0 } +#define PORTB_U3_XH2E_DESC { ASPEED_IP_SCU, SCU410, GENMASK(5, 4), 3, 0 } + +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHD, USB3B, USB3BXHD, PORTB_U3_XHD_= DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHPD, USB3B, USB3BXHPD, PORTB_U3_XH= D_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH, USB3BBP, USB3BXH, PORTB_U3_XH_D= ESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP, USB3BBP, USB3BXHP, PORTB_U3_XH= _DESC, + SIG_DESC_CLEAR(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXH2A, USB3BAP, USB3BXH2A, PORTB_U3_= XH2E_DESC, + SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SEMG(PORTB_U3, USB3BXHP2A, USB3BAP, USB3BXHP2A, PORTB_U= 3_XH2E_DESC, + SIG_DESC_CLEAR(SCU410, 10)); +PIN_DECL_(PORTB_U3, SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXHD), SIG_EXPR_LIST_P= TR(PORTB_U3, USB3BXHPD), + SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH), SIG_EXPR_LIST_PTR(PORTB_U3, USB3B= XHP), + SIG_EXPR_LIST_PTR(PORTB_U3, USB3BXH2A), SIG_EXPR_LIST_PTR(PORTB_U3, USB= 3BXHP2A)); + +/* + * USB3 virtual PHY pins. + * + * PORTA_U3_PHY and PORTB_U3_PHY are logical endpoints, not package pins. + * They alias existing USB3 expressions so pin groups can model both direc= t and + * cross-coupled routing to PHY A/B. + * + * - USB3AAP: PORTA_U3 + PORTA_U3_PHY (A -> PHY A) + * - USB3ABP: PORTA_U3 + PORTB_U3_PHY (A -> PHY B) + * - USB3BBP: PORTB_U3 + PORTB_U3_PHY (B -> PHY B) + * - USB3BAP: PORTB_U3 + PORTA_U3_PHY (B -> PHY A) + * + * They do not have any registers to configure this behavior; the goal is + * simply for the driver to prevent conflicting selections. For example, + * selecting group USB3ABP and USB3BBP at the same time should not be + * allowed. + */ +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXH, USB3AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3AXHP, USB3AAP); +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXH2A, USB3BAP); +SIG_EXPR_LIST_ALIAS(PORTA_U3_PHY, USB3BXHP2A, USB3BAP); +PIN_DECL_(PORTA_U3_PHY, SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXH), + SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3AXHP), SIG_EXPR_LIST_PTR(PORTA_U3_P= HY, USB3BXH2A), + SIG_EXPR_LIST_PTR(PORTA_U3_PHY, USB3BXHP2A)); + +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXH2B, USB3ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3AXHP2B, USB3ABP); +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXH, USB3BBP); +SIG_EXPR_LIST_ALIAS(PORTB_U3_PHY, USB3BXHP, USB3BBP); +PIN_DECL_(PORTB_U3_PHY, SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXH2B), + SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3AXHP2B), SIG_EXPR_LIST_PTR(PORTB_U3= _PHY, USB3BXH), + SIG_EXPR_LIST_PTR(PORTB_U3_PHY, USB3BXHP)); + +/* USB3A xHCI to vHUB */ +GROUP_DECL(USB3A, PORTA_U3); +/* USB3A xHCI to USB3A PHY */ +GROUP_DECL(USB3AAP, PORTA_U3, PORTA_U3_PHY); +/* USB3A xHCI to USB3B PHY */ +GROUP_DECL(USB3ABP, PORTA_U3, PORTB_U3_PHY); + +FUNC_DECL_1(USB3AXHD, USB3A); +FUNC_DECL_1(USB3AXHPD, USB3A); +FUNC_DECL_1(USB3AXH, USB3AAP); +FUNC_DECL_1(USB3AXHP, USB3AAP); +FUNC_DECL_1(USB3AXH2B, USB3ABP); +FUNC_DECL_1(USB3AXHP2B, USB3ABP); + +/* USB3B xHCI to vHUB */ +GROUP_DECL(USB3B, PORTB_U3); +/* USB3B xHCI to USB3A PHY */ +GROUP_DECL(USB3BAP, PORTB_U3, PORTA_U3_PHY); +/* USB3B xHCI to USB3B PHY */ +GROUP_DECL(USB3BBP, PORTB_U3, PORTB_U3_PHY); + +FUNC_DECL_1(USB3BXHD, USB3B); +FUNC_DECL_1(USB3BXHPD, USB3B); +FUNC_DECL_1(USB3BXH, USB3BBP); +FUNC_DECL_1(USB3BXHP, USB3BBP); +FUNC_DECL_1(USB3BXH2A, USB3BAP); +FUNC_DECL_1(USB3BXHP2A, USB3BAP); + +static const struct pinctrl_pin_desc aspeed_g7_soc0_pins[] =3D { + ASPEED_PINCTRL_PIN(AC14), + ASPEED_PINCTRL_PIN(AE15), + ASPEED_PINCTRL_PIN(AD14), + ASPEED_PINCTRL_PIN(AE14), + ASPEED_PINCTRL_PIN(AF14), + ASPEED_PINCTRL_PIN(AB13), + ASPEED_PINCTRL_PIN(AB14), + ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF13), + ASPEED_PINCTRL_PIN(AC13), + ASPEED_PINCTRL_PIN(AD13), + ASPEED_PINCTRL_PIN(AE13), + ASPEED_PINCTRL_PIN(JTAG_PORT), + ASPEED_PINCTRL_PIN(PCIERC0_PERST), + ASPEED_PINCTRL_PIN(PCIERC1_PERST), + ASPEED_PINCTRL_PIN(PORTA_MODE), + ASPEED_PINCTRL_PIN(PORTA_U2), + ASPEED_PINCTRL_PIN(PORTA_U3), + ASPEED_PINCTRL_PIN(PORTA_U2_PHY), + ASPEED_PINCTRL_PIN(PORTA_U3_PHY), + ASPEED_PINCTRL_PIN(PORTB_MODE), + ASPEED_PINCTRL_PIN(PORTB_U2), + ASPEED_PINCTRL_PIN(PORTB_U3), + ASPEED_PINCTRL_PIN(PORTB_U2_PHY), + ASPEED_PINCTRL_PIN(PORTB_U3_PHY), +}; + +static const struct aspeed_pin_group aspeed_g7_soc0_groups[] =3D { + ASPEED_PINCTRL_GROUP(EMMCCDN), + ASPEED_PINCTRL_GROUP(EMMCG1), + ASPEED_PINCTRL_GROUP(EMMCG4), + ASPEED_PINCTRL_GROUP(EMMCG8), + ASPEED_PINCTRL_GROUP(EMMCWPN), + ASPEED_PINCTRL_GROUP(TSPRSTN), + ASPEED_PINCTRL_GROUP(UFSCLKI), + ASPEED_PINCTRL_GROUP(VB0), + ASPEED_PINCTRL_GROUP(VB1), + ASPEED_PINCTRL_GROUP(VGADDC), + /* JTAG groups */ + ASPEED_PINCTRL_GROUP(JTAG0), + /* PCIE RC groups */ + ASPEED_PINCTRL_GROUP(PCIERC0PERST), + ASPEED_PINCTRL_GROUP(PCIERC1PERST), + /* USB3A groups */ + ASPEED_PINCTRL_GROUP(USB3A), + ASPEED_PINCTRL_GROUP(USB3AAP), + ASPEED_PINCTRL_GROUP(USB3ABP), + /* USB3B groups */ + ASPEED_PINCTRL_GROUP(USB3B), + ASPEED_PINCTRL_GROUP(USB3BAP), + ASPEED_PINCTRL_GROUP(USB3BBP), + /* USB2A groups */ + ASPEED_PINCTRL_GROUP(USB2A), + ASPEED_PINCTRL_GROUP(USB2AAP), + ASPEED_PINCTRL_GROUP(USB2ABP), + ASPEED_PINCTRL_GROUP(USB2ADAP), + ASPEED_PINCTRL_GROUP(USB2AH), + ASPEED_PINCTRL_GROUP(USB2AHAP), + /* USB2B groups */ + ASPEED_PINCTRL_GROUP(USB2B), + ASPEED_PINCTRL_GROUP(USB2BAP), + ASPEED_PINCTRL_GROUP(USB2BBP), + ASPEED_PINCTRL_GROUP(USB2BDBP), + ASPEED_PINCTRL_GROUP(USB2BH), + ASPEED_PINCTRL_GROUP(USB2BHBP), +}; + +static const struct aspeed_pin_function aspeed_g7_soc0_functions[] =3D { + ASPEED_PINCTRL_FUNC(EMMC), + ASPEED_PINCTRL_FUNC(TSPRSTN), + ASPEED_PINCTRL_FUNC(UFSCLKI), + ASPEED_PINCTRL_FUNC(VB), + ASPEED_PINCTRL_FUNC(VGADDC), + /* JTAG functions */ + ASPEED_PINCTRL_FUNC(JTAGDDR), + ASPEED_PINCTRL_FUNC(JTAGM0), + ASPEED_PINCTRL_FUNC(JTAGPCIEA), + ASPEED_PINCTRL_FUNC(JTAGPCIEB), + ASPEED_PINCTRL_FUNC(JTAGPSP), + ASPEED_PINCTRL_FUNC(JTAGSSP), + ASPEED_PINCTRL_FUNC(JTAGTSP), + ASPEED_PINCTRL_FUNC(JTAGUSB3A), + ASPEED_PINCTRL_FUNC(JTAGUSB3B), + /* PCIE RC functions */ + ASPEED_PINCTRL_FUNC(PCIERC0PERST), + ASPEED_PINCTRL_FUNC(PCIERC1PERST), + /* USB3A functions */ + ASPEED_PINCTRL_FUNC(USB3AXH), + ASPEED_PINCTRL_FUNC(USB3AXH2B), + ASPEED_PINCTRL_FUNC(USB3AXHD), + ASPEED_PINCTRL_FUNC(USB3AXHP), + ASPEED_PINCTRL_FUNC(USB3AXHP2B), + ASPEED_PINCTRL_FUNC(USB3AXHPD), + /* USB3B functions */ + ASPEED_PINCTRL_FUNC(USB3BXH), + ASPEED_PINCTRL_FUNC(USB3BXH2A), + ASPEED_PINCTRL_FUNC(USB3BXHD), + ASPEED_PINCTRL_FUNC(USB3BXHP), + ASPEED_PINCTRL_FUNC(USB3BXHP2A), + ASPEED_PINCTRL_FUNC(USB3BXHPD), + /* USB2A functions */ + ASPEED_PINCTRL_FUNC(USB2AD0), + ASPEED_PINCTRL_FUNC(USB2AD1), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2AHP), + ASPEED_PINCTRL_FUNC(USB2AHPD0), + ASPEED_PINCTRL_FUNC(USB2AXH), + ASPEED_PINCTRL_FUNC(USB2AXH2B), + ASPEED_PINCTRL_FUNC(USB2AXHD1), + ASPEED_PINCTRL_FUNC(USB2AXHP), + ASPEED_PINCTRL_FUNC(USB2AXHP2B), + ASPEED_PINCTRL_FUNC(USB2AXHPD1), + /* USB2B functions */ + ASPEED_PINCTRL_FUNC(USB2BD0), + ASPEED_PINCTRL_FUNC(USB2BD1), + ASPEED_PINCTRL_FUNC(USB2BH), + ASPEED_PINCTRL_FUNC(USB2BHP), + ASPEED_PINCTRL_FUNC(USB2BHPD0), + ASPEED_PINCTRL_FUNC(USB2BXH), + ASPEED_PINCTRL_FUNC(USB2BXH2A), + ASPEED_PINCTRL_FUNC(USB2BXHD1), + ASPEED_PINCTRL_FUNC(USB2BXHP), + ASPEED_PINCTRL_FUNC(USB2BXHP2A), + ASPEED_PINCTRL_FUNC(USB2BXHPD1), +}; + +static const struct pinmux_ops aspeed_g7_soc0_pinmux_ops =3D { + .get_functions_count =3D aspeed_pinmux_get_fn_count, + .get_function_name =3D aspeed_pinmux_get_fn_name, + .get_function_groups =3D aspeed_pinmux_get_fn_groups, + .set_mux =3D aspeed_pinmux_set_mux, + .gpio_request_enable =3D aspeed_gpio_request_enable, + .strict =3D true, +}; + +static const struct pinctrl_ops aspeed_g7_soc0_pinctrl_ops =3D { + .get_groups_count =3D aspeed_pinctrl_get_groups_count, + .get_group_name =3D aspeed_pinctrl_get_group_name, + .get_group_pins =3D aspeed_pinctrl_get_group_pins, + .pin_dbg_show =3D aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map =3D pinconf_generic_dt_node_to_map_all, + .dt_free_map =3D pinctrl_utils_free_map, +}; + +static const struct pinconf_ops aspeed_g7_soc0_pinconf_ops =3D { + .is_generic =3D true, + .pin_config_get =3D aspeed_pin_config_get, + .pin_config_set =3D aspeed_pin_config_set, + .pin_config_group_get =3D aspeed_pin_config_group_get, + .pin_config_group_set =3D aspeed_pin_config_group_set, +}; + +/* pinctrl_desc */ +static const struct pinctrl_desc aspeed_g7_soc0_pinctrl_desc =3D { + .name =3D "aspeed-g7-soc0-pinctrl", + .pins =3D aspeed_g7_soc0_pins, + .npins =3D ARRAY_SIZE(aspeed_g7_soc0_pins), + .pctlops =3D &aspeed_g7_soc0_pinctrl_ops, + .pmxops =3D &aspeed_g7_soc0_pinmux_ops, + .confops =3D &aspeed_g7_soc0_pinconf_ops, +}; + +static const struct aspeed_pin_config aspeed_g7_soc0_configs[] =3D { + /* GPIO18A */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC14, AC14 }, SCU480, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AE15, AE15 }, SCU484, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AD14, AD14 }, SCU488, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AE14, AE14 }, SCU48C, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AF14, AF14 }, SCU490, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AB13, AB13 }, SCU494, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AB14, AB14 }, SCU498, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AF15, AF15 }, SCU49C, GENMASK(3, 0) }, + /* GPIO18B */ + { PIN_CONFIG_DRIVE_STRENGTH, { AF13, AF13 }, SCU4A0, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AC13, AC13 }, SCU4A4, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AD13, AD13 }, SCU4A8, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, { AE13, AE13 }, SCU4AC, GENMASK(3, 0) }, +}; + +static const struct aspeed_pin_config_map aspeed_g7_soc0_pin_config_map[] = =3D { + { PIN_CONFIG_DRIVE_STRENGTH, 3, 0, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 6, 1, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 2, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 11, 3, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 4, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 18, 5, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 20, 6, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 23, 7, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 30, 8, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 32, 9, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 33, 10, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 35, 11, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 37, 12, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 38, 13, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 39, 14, GENMASK(3, 0) }, + { PIN_CONFIG_DRIVE_STRENGTH, 41, 15, GENMASK(3, 0) }, + +}; + +static int aspeed_g7_soc0_sig_expr_set(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, bool enable) +{ + int ret; + int i; + + for (i =3D 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc =3D &expr->descs[i]; + u32 pattern =3D enable ? desc->enable : desc->disable; + u32 val =3D (pattern << __ffs(desc->mask)); + + if (!ctx->maps[desc->ip]) + return -ENODEV; + + WARN_ON_ONCE(desc->ip !=3D ASPEED_IP_SCU); + + ret =3D regmap_update_bits(ctx->maps[desc->ip], desc->reg, + desc->mask, val); + if (ret) + return ret; + } + + ret =3D aspeed_sig_expr_eval(ctx, expr, enable); + if (ret < 0) + return ret; + + return ret ? 0 : -EPERM; +} + +static const struct aspeed_pinmux_ops aspeed_g7_soc0_ops =3D { + .set =3D aspeed_g7_soc0_sig_expr_set, +}; + +static struct aspeed_pinctrl_data aspeed_g7_soc0_pinctrl_data =3D { + .pins =3D aspeed_g7_soc0_pins, + .npins =3D ARRAY_SIZE(aspeed_g7_soc0_pins), + .pinmux =3D { + .ops =3D &aspeed_g7_soc0_ops, + .groups =3D aspeed_g7_soc0_groups, + .ngroups =3D ARRAY_SIZE(aspeed_g7_soc0_groups), + .functions =3D aspeed_g7_soc0_functions, + .nfunctions =3D ARRAY_SIZE(aspeed_g7_soc0_functions), + }, + .configs =3D aspeed_g7_soc0_configs, + .nconfigs =3D ARRAY_SIZE(aspeed_g7_soc0_configs), + .confmaps =3D aspeed_g7_soc0_pin_config_map, + .nconfmaps =3D ARRAY_SIZE(aspeed_g7_soc0_pin_config_map), +}; + +static int aspeed_g7_soc0_pinctrl_probe(struct platform_device *pdev) +{ + return aspeed_pinctrl_probe(pdev, &aspeed_g7_soc0_pinctrl_desc, + &aspeed_g7_soc0_pinctrl_data); +} + +static const struct of_device_id aspeed_g7_soc0_pinctrl_match[] =3D { + { .compatible =3D "aspeed,ast2700-soc0-pinctrl" }, + {} +}; +MODULE_DEVICE_TABLE(of, aspeed_g7_soc0_pinctrl_match); + +static struct platform_driver aspeed_g7_soc0_pinctrl_driver =3D { + .probe =3D aspeed_g7_soc0_pinctrl_probe, + .driver =3D { + .name =3D "aspeed-g7-soc0-pinctrl", + .of_match_table =3D aspeed_g7_soc0_pinctrl_match, + .suppress_bind_attrs =3D true, + }, +}; + +static int __init aspeed_g7_soc0_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g7_soc0_pinctrl_driver); +} +arch_initcall(aspeed_g7_soc0_pinctrl_init); --=20 2.34.1