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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260331-t264-pwm-v4-3-c041659677cf@nvidia.com> References: <20260331-t264-pwm-v4-0-c041659677cf@nvidia.com> In-Reply-To: <20260331-t264-pwm-v4-0-c041659677cf@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Thierry Reding , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TYCP286CA0213.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c5::19) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|CH3PR12MB8330:EE_ X-MS-Office365-Filtering-Correlation-Id: 9387fae2-b7b3-47a4-83f5-08de8ecafc75 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|10070799003|366016|56012099003|18002099003|22082099003; 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Update the pwm_readl/pwm_writel helper functions to take channel (as struct pwm_device *) and offset separately. Reviewed-by: Thierry Reding Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 8a330169d531..358c81cea05b 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -57,6 +57,8 @@ #define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 =20 +#define PWM_CSR_0 0 + struct tegra_pwm_soc { unsigned int num_channels; }; @@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(= struct pwm_chip *chip) return pwmchip_get_drvdata(chip); } =20 -static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) +static inline u32 pwm_readl(struct pwm_device *dev, unsigned int offset) { - return readl(pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip =3D to_tegra_pwm_chip(dev->chip); + + return readl(chip->regs + (dev->hwpwm * 16) + offset); } =20 -static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offs= et, u32 value) +static inline void pwm_writel(struct pwm_device *dev, unsigned int offset,= u32 value) { - writel(value, pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip =3D to_tegra_pwm_chip(dev->chip); + + writel(value, chip->regs + (dev->hwpwm * 16) + offset); } =20 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, } else val |=3D PWM_ENABLE; =20 - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 /* * If the PWM is not enabled, turn the clock off again to save power. @@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); int rc =3D 0; u32 val; =20 @@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, st= ruct pwm_device *pwm) if (rc) return rc; =20 - val =3D pwm_readl(pc, pwm->hwpwm); + val =3D pwm_readl(pwm, PWM_CSR_0); val |=3D PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 return 0; } =20 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pw= m) { - struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); u32 val; =20 - val =3D pwm_readl(pc, pwm->hwpwm); + val =3D pwm_readl(pwm, PWM_CSR_0); val &=3D ~PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 pm_runtime_put_sync(pwmchip_parent(chip)); } --=20 2.53.0