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The controller is similar to earlier generations but not compatible with them. Signed-off-by: Thierry Reding [mperttunen: Drop extra Tegra194 compatible string] Signed-off-by: Mikko Perttunen --- Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml = b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml index 41cea4979132..cb2f36e7b5d6 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.yaml @@ -16,6 +16,7 @@ properties: - enum: - nvidia,tegra20-pwm - nvidia,tegra186-pwm + - nvidia,tegra264-pwm =20 - items: - enum: --=20 2.53.0 From nobody Thu Apr 2 01:08:57 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012057.outbound.protection.outlook.com [52.101.43.57]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5316368269; 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Hence, let dev_pm_opp_set_rate() set the max clock rate based upon the current parent clock that can be specified via device-tree. After this, the Tegra194 SoC data becomes redundant, so get rid of it. Signed-off-by: Yi-Wei Wang Co-developed-by: Mikko Perttunen Signed-off-by: Mikko Perttunen Reviewed-by: Thierry Reding --- drivers/pwm/pwm-tegra.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 172063b51d44..8a330169d531 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -59,9 +59,6 @@ =20 struct tegra_pwm_soc { unsigned int num_channels; - - /* Maximum IP frequency for given SoCs */ - unsigned long max_frequency; }; =20 struct tegra_pwm_chip { @@ -303,7 +300,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) return ret; =20 /* Set maximum frequency of the IP */ - ret =3D dev_pm_opp_set_rate(&pdev->dev, pc->soc->max_frequency); + ret =3D dev_pm_opp_set_rate(&pdev->dev, ULONG_MAX); if (ret < 0) { dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret); goto put_pm; @@ -318,7 +315,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) =20 /* Set minimum limit of PWM period for the IP */ pc->min_period_ns =3D - (NSEC_PER_SEC / (pc->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1; =20 pc->rst =3D devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { @@ -397,23 +394,16 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) =20 static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, - .max_frequency =3D 48000000UL, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, - .max_frequency =3D 102000000UL, -}; - -static const struct tegra_pwm_soc tegra194_pwm_soc =3D { - .num_channels =3D 1, - .max_frequency =3D 408000000UL, }; =20 static const struct of_device_id tegra_pwm_of_match[] =3D { { .compatible =3D "nvidia,tegra20-pwm", .data =3D &tegra20_pwm_soc }, { .compatible =3D "nvidia,tegra186-pwm", .data =3D &tegra186_pwm_soc }, - { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra194_pwm_soc }, + { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra186_pwm_soc }, { } }; MODULE_DEVICE_TABLE(of, tegra_pwm_of_match); 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Update the pwm_readl/pwm_writel helper functions to take channel (as struct pwm_device *) and offset separately. Reviewed-by: Thierry Reding Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 8a330169d531..358c81cea05b 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -57,6 +57,8 @@ #define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 =20 +#define PWM_CSR_0 0 + struct tegra_pwm_soc { unsigned int num_channels; }; @@ -78,14 +80,18 @@ static inline struct tegra_pwm_chip *to_tegra_pwm_chip(= struct pwm_chip *chip) return pwmchip_get_drvdata(chip); } =20 -static inline u32 pwm_readl(struct tegra_pwm_chip *pc, unsigned int offset) +static inline u32 pwm_readl(struct pwm_device *dev, unsigned int offset) { - return readl(pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip =3D to_tegra_pwm_chip(dev->chip); + + return readl(chip->regs + (dev->hwpwm * 16) + offset); } =20 -static inline void pwm_writel(struct tegra_pwm_chip *pc, unsigned int offs= et, u32 value) +static inline void pwm_writel(struct pwm_device *dev, unsigned int offset,= u32 value) { - writel(value, pc->regs + (offset << 4)); + struct tegra_pwm_chip *chip =3D to_tegra_pwm_chip(dev->chip); + + writel(value, chip->regs + (dev->hwpwm * 16) + offset); } =20 static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -194,7 +200,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, } else val |=3D PWM_ENABLE; =20 - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); =20 /* * If the PWM is not enabled, turn the clock off again to save power. @@ -207,7 +213,6 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); int rc =3D 0; u32 val; =20 @@ -215,21 +220,20 @@ static int tegra_pwm_enable(struct pwm_chip *chip, st= ruct pwm_device *pwm) if (rc) return rc; =20 - val =3D pwm_readl(pc, pwm->hwpwm); + val =3D pwm_readl(pwm, PWM_CSR_0); val |=3D PWM_ENABLE; - pwm_writel(pc, pwm->hwpwm, val); + pwm_writel(pwm, PWM_CSR_0, val); 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Hence, introduce an enablement offset field in the tegra_pwm_soc structure to describe the offset of the register. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen Reviewed-by: Thierry Reding --- drivers/pwm/pwm-tegra.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 358c81cea05b..b925ef914411 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -61,6 +61,7 @@ =20 struct tegra_pwm_soc { unsigned int num_channels; + unsigned int enable_reg; }; =20 struct tegra_pwm_chip { @@ -197,8 +198,9 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, err =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); if (err) return err; - } else + } else if (pc->soc->enable_reg =3D=3D PWM_CSR_0) { val |=3D PWM_ENABLE; + } =20 pwm_writel(pwm, PWM_CSR_0, val); =20 @@ -213,6 +215,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); int rc =3D 0; u32 val; =20 @@ -220,20 +223,22 @@ static int tegra_pwm_enable(struct pwm_chip *chip, st= ruct pwm_device *pwm) if (rc) return rc; =20 - val =3D pwm_readl(pwm, PWM_CSR_0); + + val =3D pwm_readl(pwm, pc->soc->enable_reg); val |=3D PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); =20 return 0; } =20 static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pw= m) { + struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); u32 val; =20 - val =3D pwm_readl(pwm, PWM_CSR_0); + val =3D pwm_readl(pwm, pc->soc->enable_reg); val &=3D ~PWM_ENABLE; - pwm_writel(pwm, PWM_CSR_0, val); + pwm_writel(pwm, pc->soc->enable_reg, val); =20 pm_runtime_put_sync(pwmchip_parent(chip)); } @@ -398,10 +403,12 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) =20 static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, + .enable_reg =3D PWM_CSR_0, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, + .enable_reg =3D PWM_CSR_0, }; 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Parameterize the driver in preparation. The depth value also becomes disconnected from the width of the duty field, so define it separately. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Reviewed-by: Thierry Reding Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index b925ef914411..d7968521fbfd 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -52,16 +52,19 @@ #include =20 #define PWM_ENABLE (1 << 31) -#define PWM_DUTY_WIDTH 8 #define PWM_DUTY_SHIFT 16 -#define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 =20 #define PWM_CSR_0 0 =20 +#define PWM_DEPTH 256 + struct tegra_pwm_soc { unsigned int num_channels; unsigned int enable_reg; + + unsigned int duty_width; + unsigned int scale_width; }; =20 struct tegra_pwm_chip { @@ -106,22 +109,22 @@ static int tegra_pwm_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 /* * Convert from duty_ns / period_ns to a fixed number of duty ticks - * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the + * per PWM_DEPTH cycles and make sure to round to the * nearest integer during division. */ - c *=3D (1 << PWM_DUTY_WIDTH); + c *=3D PWM_DEPTH; c =3D DIV_ROUND_CLOSEST_ULL(c, period_ns); =20 val =3D (u32)c << PWM_DUTY_SHIFT; =20 /* - * min period =3D max clock limit >> PWM_DUTY_WIDTH + * min period =3D max clock limit / PWM_DEPTH */ if (period_ns < pc->min_period_ns) return -EINVAL; =20 /* - * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) + * Compute the prescaler value for which PWM_DEPTH * cycles at the PWM clock rate will take period_ns nanoseconds. * * num_channels: If single instance of PWM controller has multiple @@ -135,7 +138,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, */ if (pc->soc->num_channels =3D=3D 1) { /* - * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches + * Rate is multiplied with PWM_DEPTH so that it matches * with the maximum possible rate that the controller can * provide. Any further lower value can be derived by setting * PFM bits[0:12]. @@ -145,7 +148,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate =3D DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WID= TH, + required_clk_rate =3D DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * PWM_DEPTH, period_ns); =20 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) @@ -169,7 +172,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ rate =3D mul_u64_u64_div_u64(pc->clk_rate, period_ns, - (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); + (u64)NSEC_PER_SEC * PWM_DEPTH); =20 /* * Since the actual PWM divider is the register's frequency divider @@ -185,7 +188,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, * Make sure that the rate will fit in the register's frequency * divider field. */ - if (rate >> PWM_SCALE_WIDTH) + if (rate >> pc->soc->scale_width) return -EINVAL; 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Add SoC data and update top comment to describe register layout in more detail. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Signed-off-by: Mikko Perttunen Reviewed-by: Thierry Reding --- drivers/pwm/pwm-tegra.c | 75 ++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 61 insertions(+), 14 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index d7968521fbfd..c9d30724e339 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -7,22 +7,60 @@ * Copyright (c) 2010-2020, NVIDIA Corporation. * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer * - * Overview of Tegra Pulse Width Modulator Register: - * 1. 13-bit: Frequency division (SCALE) - * 2. 8-bit : Pulse division (DUTY) - * 3. 1-bit : Enable bit + * Overview of Tegra Pulse Width Modulator Register + * CSR_0 of Tegra20, Tegra186, and Tegra194: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31 | ENB | Enable Pulse width modulator. = | + * | | | 0 =3D DISABLE, 1 =3D ENABLE. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 30:16 | PWM_0 | Pulse width that needs to be programmed. = | + * | | | 0 =3D Always low. = | + * | | | 1 =3D 1 / 256 pulse high. = | + * | | | 2 =3D 2 / 256 pulse high. = | + * | | | N =3D N / 256 pulse high. = | + * | | | Only 8 bits are usable [23:16]. = | + * | | | Bit[24] can be programmed to 1 to achieve 100% duty = | + * | | | cycle. In this case the other bits [23:16] are set to= | + * | | | don=E2=80=99t care. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 12:0 | PFM_0 | Frequency divider that needs to be programmed, also k= nown | + * | | | as SCALE. Division by (1 + PFM_0). = | + * +-------+-------+------------------------------------------------------= -----+ * - * The PWM clock frequency is divided by 256 before subdividing it based - * on the programmable frequency division value to generate the required - * frequency for PWM output. The maximum output frequency that can be - * achieved is (max rate of source clock) / 256. - * e.g. if source clock rate is 408 MHz, maximum output frequency can be: - * 408 MHz/256 =3D 1.6 MHz. - * This 1.6 MHz frequency can further be divided using SCALE value in PWM. + * CSR_0 of Tegra264: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31:16 | PWM_0 | Pulse width that needs to be programmed. = | + * | | | 0 =3D Always low. = | + * | | | 1 =3D 1 / (1 + CSR_1.DEPTH) pulse high. = | + * | | | 2 =3D 2 / (1 + CSR_1.DEPTH) pulse high. = | + * | | | N =3D N / (1 + CSR_1.DEPTH) pulse high. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 15:0 | PFM_0 | Frequency divider that needs to be programmed, also k= nown | + * | | | as SCALE. Division by (1 + PFM_0). = | + * +-------+-------+------------------------------------------------------= -----+ + * + * CSR_1 of Tegra264: + * +-------+-------+------------------------------------------------------= -----+ + * | Bit | Field | Description = | + * +-------+-------+------------------------------------------------------= -----+ + * | 31 | ENB | Enable Pulse width modulator. = | + * | | | 0 =3D DISABLE, 1 =3D ENABLE. = | + * +-------+-------+------------------------------------------------------= -----+ + * | 30:15 | DEPTH | Depth for pulse width modulator. This controls the pu= lse | + * | | | time generated. Division by (1 + CSR_1.DEPTH). = | + * +-------+-------+------------------------------------------------------= -----+ * - * PWM pulse width: 8 bits are usable [23:16] for varying pulse width. - * To achieve 100% duty cycle, program Bit [24] of this register to - * 1=E2=80=99b1. In which case the other bits [23:16] are set to don't car= e. + * The PWM clock frequency is divided by DEPTH =3D (1 + CSR_1.DEPTH) befor= e subdividing it + * based on the programmable frequency division value to generate the requ= ired frequency + * for PWM output. DEPTH is fixed to 256 before Tegra264. The maximum outp= ut frequency + * that can be achieved is (max rate of source clock) / DEPTH. + * e.g. if source clock rate is 408 MHz, and DEPTH =3D 256, maximum output= frequency can be: + * 408 MHz / 256 ~=3D 1.6 MHz. + * This 1.6 MHz frequency can further be divided using SCALE value in PWM. * * Limitations: * - When PWM is disabled, the output is driven to inactive. @@ -56,6 +94,7 @@ #define PWM_SCALE_SHIFT 0 =20 #define PWM_CSR_0 0 +#define PWM_CSR_1 4 =20 #define PWM_DEPTH 256 =20 @@ -418,10 +457,18 @@ static const struct tegra_pwm_soc tegra186_pwm_soc = =3D { .scale_width =3D 13, }; =20 +static const struct tegra_pwm_soc tegra264_pwm_soc =3D { + .num_channels =3D 1, + .enable_reg =3D PWM_CSR_1, + .duty_width =3D 16, + .scale_width =3D 16, +}; + static const struct of_device_id tegra_pwm_of_match[] =3D { { .compatible =3D "nvidia,tegra20-pwm", .data =3D &tegra20_pwm_soc }, { .compatible =3D "nvidia,tegra186-pwm", .data =3D &tegra186_pwm_soc }, { .compatible =3D "nvidia,tegra194-pwm", .data =3D &tegra186_pwm_soc }, + { .compatible =3D "nvidia,tegra264-pwm", .data =3D &tegra264_pwm_soc }, { } }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260331-t264-pwm-v4-7-c041659677cf@nvidia.com> References: <20260331-t264-pwm-v4-0-c041659677cf@nvidia.com> In-Reply-To: <20260331-t264-pwm-v4-0-c041659677cf@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Thierry Reding , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: TY4P286CA0047.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:36e::16) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|CH3PR12MB8330:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a5af6af-ce54-41e1-c6b5-08de8ecb0975 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|10070799003|366016|56012099003|18002099003|22082099003; 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Signed-off-by: Thierry Reding [mperttunen: Adjust commit message] Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 72 ++++++++++++++++++++++++++++= ++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 7644a41d5f72..13fd04068016 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3336,6 +3336,18 @@ i2c3: i2c@c610000 { status =3D "disabled"; }; =20 + pwm4: pwm@c6a0000 { + compatible =3D "nvidia,tegra264-pwm"; + reg =3D <0x0 0xc6a0000 0x0 0x10000>; + status =3D "disabled"; + + clocks =3D <&bpmp TEGRA264_CLK_PWM4>; + resets =3D <&bpmp TEGRA264_RESET_PWM4>; + reset-names =3D "pwm"; + + #pwm-cells =3D <2>; + }; + pmc: pmc@c800000 { compatible =3D "nvidia,tegra264-pmc"; reg =3D <0x0 0x0c800000 0x0 0x100000>, @@ -3538,6 +3550,66 @@ i2c16: i2c@c430000 { status =3D "disabled"; }; =20 + pwm2: pwm@c5e0000 { + compatible =3D "nvidia,tegra264-pwm"; + reg =3D <0x0 0xc5e0000 0x0 0x10000>; + status =3D "disabled"; + + clocks =3D <&bpmp TEGRA264_CLK_PWM2>; + resets =3D <&bpmp TEGRA264_RESET_PWM2>; + reset-names =3D "pwm"; + + #pwm-cells =3D <2>; + }; + + pwm3: pwm@c5f0000 { + compatible =3D "nvidia,tegra264-pwm"; + reg =3D <0x0 0xc5f0000 0x0 0x10000>; + status =3D "disabled"; + + clocks =3D <&bpmp TEGRA264_CLK_PWM3>; + resets =3D <&bpmp TEGRA264_RESET_PWM3>; + reset-names =3D "pwm"; + + #pwm-cells =3D <2>; + }; + + pwm5: pwm@c600000 { + compatible =3D "nvidia,tegra264-pwm"; + reg =3D <0x0 0xc600000 0x0 0x10000>; + status =3D "disabled"; + + clocks =3D <&bpmp TEGRA264_CLK_PWM5>; + resets =3D <&bpmp TEGRA264_RESET_PWM5>; + reset-names =3D "pwm"; + + #pwm-cells =3D <2>; + }; + + pwm9: pwm@c610000 { + compatible =3D "nvidia,tegra264-pwm"; + reg =3D <0x0 0xc610000 0x0 0x10000>; + status =3D "disabled"; + + clocks =3D <&bpmp TEGRA264_CLK_PWM9>; + resets =3D <&bpmp TEGRA264_RESET_PWM9>; + reset-names =3D "pwm"; + + #pwm-cells =3D <2>; + }; + + pwm10: pwm@c620000 { + compatible =3D "nvidia,tegra264-pwm"; + reg =3D <0x0 0xc620000 0x0 0x10000>; + status =3D "disabled"; + + clocks =3D <&bpmp TEGRA264_CLK_PWM10>; + resets =3D <&bpmp TEGRA264_RESET_PWM10>; + reset-names =3D "pwm"; + + #pwm-cells =3D <2>; + }; + i2c0: i2c@c630000 { compatible =3D "nvidia,tegra264-i2c"; reg =3D <0x00 0x0c630000 0x0 0x10000>; --=20 2.53.0