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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12ab97f6994sm12027550c88.8.2026.03.31.23.35.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Mar 2026 23:35:36 -0700 (PDT) From: Qiang Yu Date: Tue, 31 Mar 2026 23:35:28 -0700 Subject: [PATCH RFC 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260331-qref_vote-v1-3-3fd7fbf87864@oss.qualcomm.com> References: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com> In-Reply-To: <20260331-qref_vote-v1-0-3fd7fbf87864@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio , johan@kernel.org Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775025332; l=11277; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=O/xzz3OyQHlZaY8PTjkJNEJgipL9OgU4S64AIcv/hgs=; b=qKO8FGxIRHZ/FW3wLzJyCUevJz5XtDyvZRBba7eoPWacGyFUxVLZQZfDvGf3+KRRT9ccY3OKS 6g4Vw2jjMDGAhHXEwGlzRW58FLQA8dgH5OE8GBJ8iNWdDvxNALN9d7R X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDA1NiBTYWx0ZWRfX91L6CZz2nT/u Xf4gj0XthS3EstqUbLTaFzBrqyJGz2dv2m+ZmHMqmUToMJCx3BM8Ku+jIIwLrse/1Xxm4uJkmt5 9lxByi9XWJ7er97R2mli2dzVzT4IzxTLH/PoPon3DqmKl5eyCdS+/HPkwV5Hzos52bGOtmcW5uR Fvg+6DAF7Fyiv2Sma7X5z3HXIbi1mqF8vjPIA1KUoJx1TWiro1hxkPgVNSycx0ZeXMDYcbgw6e1 K916qBwQX1R1vfaQFtrSDt43rhWw0qUEs/0PcufIFVFSk9onAkth65iBgQF9O+tiM8CSdxz9UUs QeqdOYDfcQ/WZVDf49Y1efku5tHkiU6Yz7IkmNUqJYRbnYRriYMQsr2md9TeQWmxNPSSEC92acu Emj8LIkc42k57Y4tGajNVSAjPnQ7WZn9ftQnMLMv4JWbn+TfL6Vgfqh6ET552glQzGv9+VzIwjD Yhis11LLZvtWM3saSyA== X-Authority-Analysis: v=2.4 cv=G4ER0tk5 c=1 sm=1 tr=0 ts=69ccbcba cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=t2MV0Cpg_TU8-8Jkrg8A:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-GUID: bl6C3OAGMwgxMVRcpHBn0PQD-aDsCpQr X-Proofpoint-ORIG-GUID: bl6C3OAGMwgxMVRcpHBn0PQD-aDsCpQr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_02,2026-03-31_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010056 Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 340 +++++++++++------------------------= ---- 1 file changed, 93 insertions(+), 247 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index 9c0edebcdbb12816d1be5249e4f04bcaf02048aa..585f87b23af2d92daef1787b2f3= 8911681c0d8ee 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -4,265 +4,115 @@ */ =20 #include +#include #include #include +#include #include #include =20 #include =20 -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, -}; - -static struct clk_branch tcsr_edp_clkref_en =3D { - .halt_reg =3D 0x60, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x60, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_edp_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, +static const char * const tcsr_pcie_1_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qrefrx5-0p9", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", +}; + +static const char * const tcsr_pcie_2_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + +static const char * const tcsr_pcie_3_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", +}; + +static const char * const tcsr_pcie_4_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + +static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] =3D { + [TCSR_EDP_CLKREF_EN] =3D { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, }, -}; - -static struct clk_branch tcsr_pcie_1_clkref_en =3D { - .halt_reg =3D 0x48, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x48, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_1_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_1_clkref_en", + .offset =3D 0x48, + .regulator_names =3D tcsr_pcie_1_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_1_regulators), }, -}; - -static struct clk_branch tcsr_pcie_2_clkref_en =3D { - .halt_reg =3D 0x4c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x4c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_2_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D tcsr_pcie_2_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_2_regulators), }, -}; - -static struct clk_branch tcsr_pcie_3_clkref_en =3D { - .halt_reg =3D 0x54, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x54, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_3_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D tcsr_pcie_3_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_3_regulators), }, -}; - -static struct clk_branch tcsr_pcie_4_clkref_en =3D { - .halt_reg =3D 0x58, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x58, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_4_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D tcsr_pcie_4_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_4_regulators), }, -}; - -static struct clk_branch tcsr_usb2_1_clkref_en =3D { - .halt_reg =3D 0x6c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x6c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en =3D { - .halt_reg =3D 0x70, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x70, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, }, -}; - -static struct clk_branch tcsr_usb2_3_clkref_en =3D { - .halt_reg =3D 0x74, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x74, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_3_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, }, -}; - -static struct clk_branch tcsr_usb2_4_clkref_en =3D { - .halt_reg =3D 0x88, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x88, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_4_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, }, -}; - -static struct clk_branch tcsr_usb3_0_clkref_en =3D { - .halt_reg =3D 0x64, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x64, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_0_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB3_0_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, }, -}; - -static struct clk_branch tcsr_usb3_1_clkref_en =3D { - .halt_reg =3D 0x68, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x68, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB3_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en =3D { - .halt_reg =3D 0x44, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x44, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB4_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en =3D { - .halt_reg =3D 0x5c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x5c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB4_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, }, }; =20 -static struct clk_regmap *tcsr_cc_glymur_clocks[] =3D { - [TCSR_EDP_CLKREF_EN] =3D &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, - [TCSR_PCIE_2_CLKREF_EN] =3D &tcsr_pcie_2_clkref_en.clkr, - [TCSR_PCIE_3_CLKREF_EN] =3D &tcsr_pcie_3_clkref_en.clkr, - [TCSR_PCIE_4_CLKREF_EN] =3D &tcsr_pcie_4_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, - [TCSR_USB2_3_CLKREF_EN] =3D &tcsr_usb2_3_clkref_en.clkr, - [TCSR_USB2_4_CLKREF_EN] =3D &tcsr_usb2_4_clkref_en.clkr, - [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, - [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] =3D &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] =3D &tcsr_usb4_2_clkref_en.clkr, -}; - static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -271,11 +121,12 @@ static const struct regmap_config tcsr_cc_glymur_regm= ap_config =3D { .fast_io =3D true, }; =20 -static const struct qcom_cc_desc tcsr_cc_glymur_desc =3D { - .config =3D &tcsr_cc_glymur_regmap_config, - .clks =3D tcsr_cc_glymur_clocks, - .num_clks =3D ARRAY_SIZE(tcsr_cc_glymur_clocks), -}; +static int tcsr_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config, + tcsr_cc_glymur_clk_descs, + ARRAY_SIZE(tcsr_cc_glymur_clk_descs)); +} =20 static const struct of_device_id tcsr_cc_glymur_match_table[] =3D { { .compatible =3D "qcom,glymur-tcsr" }, @@ -283,11 +134,6 @@ static const struct of_device_id tcsr_cc_glymur_match_= table[] =3D { }; MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); =20 -static int tcsr_cc_glymur_probe(struct platform_device *pdev) -{ - return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc); -} - static struct platform_driver tcsr_cc_glymur_driver =3D { .probe =3D tcsr_cc_glymur_probe, .driver =3D { --=20 2.34.1