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Mon, 30 Mar 2026 22:24:59 -0700 (PDT) Received: from hu-jkona-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82ca843db09sm10270751b3a.7.2026.03.30.22.24.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2026 22:24:58 -0700 (PDT) From: Jagadeesh Kona Date: Tue, 31 Mar 2026 10:54:13 +0530 Subject: [PATCH v3 4/7] clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260331-purwa-videocc-camcc-v3-4-6daca180a4b1@oss.qualcomm.com> References: <20260331-purwa-videocc-camcc-v3-0-6daca180a4b1@oss.qualcomm.com> In-Reply-To: <20260331-purwa-videocc-camcc-v3-0-6daca180a4b1@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio Cc: Ajit Pandey , Imran Shaik , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-GUID: IlPiKeqNqrhODOLGxbYZ6Cpkb05cmqtP X-Authority-Analysis: v=2.4 cv=VInQXtPX c=1 sm=1 tr=0 ts=69cb5aac cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=F2hG9-dZ5E7o3FMX4mIA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: IlPiKeqNqrhODOLGxbYZ6Cpkb05cmqtP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzMxMDA0OCBTYWx0ZWRfX8TPtWOg2D0zr uBp4gS2YDNyHGY+wNs2YHf9wKS0vBI4JiwuM4FDFwBbv0k3nyVM5g51gaMoKVWy1KnL5nosXEa2 UqON9rsI5uYdhYFQ8xI7XDY2+xx5p70srm9SzgpSc0iGu/tQPJ0y+yLIk20YlGtXmB73ji3ylxE KgH7BixB5B6e054tPiQ8dZupYU5Ax1qrhA9N6hJGnaNshzcZNZmVrXgtLOSqf9WAbyT2CZFnWkc D9N/fGkw0PtNnrIPocDwjNn395ZhmRhdy8u5iZhG9O3+kY30H7zYXjAxv/MWBI1K5vYP8hDfDBl MfZ3H2zKbSAUMxReIYG8W+k2cm661alIerID5AYVTOIK+ZcykFxjiBDiGEvZTDcvwOqMmbiJjqW YXmhzq7cqSXa6aXtawLNq46In/3JudIRE+UJEU/WbtokZI2ewQTPgp9PEWca07UDlNr/V7m53O8 +GdX9TLv033NSeeSX/w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-31_01,2026-03-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603310048 Add support for camera QDSS debug clocks on X1E80100 platform which are required to be voted for camera icp and cpas usecases. This change aligns the camcc driver to the new ABI exposed from X1E80100 camcc bindings that supports these camcc QDSS debug clocks. Reviewed-by: Konrad Dybcio Reviewed-by: Bryan O'Donoghue Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/camcc-x1e80100.c | 64 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/drivers/clk/qcom/camcc-x1e80100.c b/drivers/clk/qcom/camcc-x1e= 80100.c index cbcc1c9fcb341e51272f5595f574f9cb7ef2b52e..7e3fc7aee854eee841176a1330f= 97dc91af91670 100644 --- a/drivers/clk/qcom/camcc-x1e80100.c +++ b/drivers/clk/qcom/camcc-x1e80100.c @@ -1052,6 +1052,31 @@ static struct clk_rcg2 cam_cc_mclk7_clk_src =3D { }, }; =20 +static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(60000000, P_CAM_CC_PLL8_OUT_EVEN, 8, 0, 0), + F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0), + F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + { } +}; + +static struct clk_rcg2 cam_cc_qdss_debug_clk_src =3D { + .cmd_rcgr =3D 0x13938, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D cam_cc_parent_map_0, + .freq_tbl =3D ftbl_cam_cc_qdss_debug_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk_src", + .parent_data =3D cam_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(cam_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] =3D { F(345600000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0), @@ -2182,6 +2207,42 @@ static struct clk_branch cam_cc_mclk7_clk =3D { }, }; =20 +static struct clk_branch cam_cc_qdss_debug_clk =3D { + .halt_reg =3D 0x13a64, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13a64, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_qdss_debug_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch cam_cc_qdss_debug_xo_clk =3D { + .halt_reg =3D 0x13a68, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x13a68, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "cam_cc_qdss_debug_xo_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &cam_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + static struct clk_branch cam_cc_sfe_0_clk =3D { .halt_reg =3D 0x133c0, .halt_check =3D BRANCH_HALT, @@ -2398,6 +2459,9 @@ static struct clk_regmap *cam_cc_x1e80100_clocks[] = =3D { [CAM_CC_PLL6_OUT_EVEN] =3D &cam_cc_pll6_out_even.clkr, [CAM_CC_PLL8] =3D &cam_cc_pll8.clkr, [CAM_CC_PLL8_OUT_EVEN] =3D &cam_cc_pll8_out_even.clkr, + [CAM_CC_QDSS_DEBUG_CLK] =3D &cam_cc_qdss_debug_clk.clkr, + [CAM_CC_QDSS_DEBUG_CLK_SRC] =3D &cam_cc_qdss_debug_clk_src.clkr, + [CAM_CC_QDSS_DEBUG_XO_CLK] =3D &cam_cc_qdss_debug_xo_clk.clkr, [CAM_CC_SFE_0_CLK] =3D &cam_cc_sfe_0_clk.clkr, [CAM_CC_SFE_0_CLK_SRC] =3D &cam_cc_sfe_0_clk_src.clkr, [CAM_CC_SFE_0_FAST_AHB_CLK] =3D &cam_cc_sfe_0_fast_ahb_clk.clkr, --=20 2.34.1