From nobody Wed Apr 1 10:01:27 2026 Received: from mail-4322.protonmail.ch (mail-4322.protonmail.ch [185.70.43.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 528521FA272; Wed, 1 Apr 2026 02:17:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.22 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009839; cv=none; b=rnJHVD+EOyKxCOypy19J2Eh4xQZVK1tc/dRB1GVSSuQHiiSCn8MufKhJR9Yjx9IZ9QJ9E8n5Tdape3OOOsg8XobsOzAQZPmuUdzmCGyXfL9N+EYJpkly2S0Zi5weOvado0/rwr5nqXnq6ZIrFxSLg0DB7WGvKGvSli96/Z5XyQI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009839; c=relaxed/simple; bh=ClZxRM9og3QbzwORt37XB7tis1sA81EoeK5k6nc4KbI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YStVeut7bTQRJYvLCn4GgMe8ZAcwFUQ6/l+iwNcw6MyXCiCIqxGHKFi/PO0NR2gbs6+HxiL7IUOiEClVOTUUnzllU2Rj6XQ7f6LIVMSXaGlkxQOH8fRtgjeP9pd3TDZZl9UqyhjgYSXbwsGWZ0HMZA/lcR6RMTyDNf0+VFUHfyQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=YNmxoMwn; arc=none smtp.client-ip=185.70.43.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="YNmxoMwn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775009836; x=1775269036; bh=ClZxRM9og3QbzwORt37XB7tis1sA81EoeK5k6nc4KbI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=YNmxoMwn7u6bv1+0NZaxEh2yeBpSibgn8Ups01LZRRF/EsEmGUQuL+B600txYdxRm ew488RSxOuqLMTwZ47TNnojNlXDV49EbHCMvjGuzJLIYAiZ+ZrCp8Ri2Fnaeg4y5Gf CMboSI0S0UEfBRwzWWPXPqllUTQSOjsFp7OTP5su0006rY5ly5lWQvEb65tGOP2nw2 u1JX8e3J7e56PZYmA8LjdNympEXzXzQIQEU9xPwDTTQoW65hGC5Knp4B8ZL/l6bnHl ERxpDZCBpX4NtFc++bXtkZK1dOslVyL78Lzf4xGVMcugGLr5erMjXT64fBncBTvWso SiSr/+j0D3EYg== Date: Wed, 01 Apr 2026 02:17:12 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH 3/6] drm/msm/adreno: set cx_mmio regardless of if platform has LLCC Message-ID: <20260331-adreno-810-v1-3-725801dbb12b@pm.me> In-Reply-To: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> References: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: f234432ef166ec93064e856b582302fd8c46ea80 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Signed-off-by: Alexander Koskovich Reviewed-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++---------------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6ce14407007e..eea18ae7c019 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->cx_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->cx_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu= *a6xx_gpu) static void a6xx_llc_slices_init(struct platform_device *pdev, struct a6xx_gpu *a6xx_gpu, bool is_a7xx) { - struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) return; =20 - /* - * There is a different programming path for A6xx targets with an - * mmu500 attached, so detect if that is the case - */ - phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); - a6xx_gpu->have_mmu500 =3D (phandle && - of_device_is_compatible(phandle, "arm,mmu-500")); - of_node_put(phandle); - - if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->cx_mmio =3D msm_ioremap(pdev, "cx_mem"); - else - a6xx_gpu->cx_mmio =3D NULL; - a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); - - if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->cx_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; const struct adreno_info *info =3D config->info; + struct device_node *phandle; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; @@ -2656,6 +2638,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 + /* + * There is a different programming path for A6xx targets with an + * mmu500 attached, so detect if that is the case + */ + phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); + a6xx_gpu->have_mmu500 =3D (phandle && + of_device_is_compatible(phandle, "arm,mmu-500")); + of_node_put(phandle); + + if (is_a7xx || !a6xx_gpu->have_mmu500) + a6xx_gpu->cx_mmio =3D msm_ioremap(pdev, "cx_mem"); + else + a6xx_gpu->cx_mmio =3D NULL; + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); --=20 2.53.0