From nobody Wed Apr 1 08:41:16 2026 Received: from mail-43101.protonmail.ch (mail-43101.protonmail.ch [185.70.43.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D31A22A4E9; Wed, 1 Apr 2026 02:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009829; cv=none; b=cfUczrHptXTv+NQQGEVqiVyztPnH54h+4XOIrpUKz1Lot5JWk9ohK+qP9slIAh9TtmftvejR8rMOMn3DUi/hHjBlFE2ItqMJTV32pawUZa0XhIgQ+S7oEtzel3jjOstLV+jG50/slUg7C68iT6Ls6kS/UQLblDhxf4gBbUAnm/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009829; c=relaxed/simple; bh=JH2g1PDLQ62EN2TzO844yDEirDhI9/BSGo+X3kunn7s=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aa8xBsxgzQDnMRzRsp6C9J0ZTqlw6HBaFnT5ycGxojHoAcz2cpUizQfP1DFbeuue/aCJ05JQBOcmxsX+NTVvezAszG11IxOIoPTJuq8UcKzLTz37W8bfv9OwBRqHEfROYOzYPachUtes7zJOZBYBT80U5WHRHlLH/YivPgBwK7Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=puS8AkyL; arc=none smtp.client-ip=185.70.43.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="puS8AkyL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775009820; x=1775269020; bh=DN6N6QM+hWyI6T9W0zQCxmGO3I8fh0zxMgCzQtQUuu0=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=puS8AkyL89OSKvW1rPr1ateKFi6bHV6aPC2DK3VgIoSTC4tdq/Ycer4PWxyeHdOAU DzCoUYJ8EVUeCukPyFDQlxwCa4dfuA+/bNVxboDgQHJCfTnITisotDcAfSTn54ieHb J6Gbep4iSTJ12tbkCQNkAUDddtvzi6V/2FCQa1kHGhoIVOejp88XOBy66eivVcLfWY 1P5xMzwMYacFC2NNhubL0e4z8xNeglSEOaSmOO/WtBqaxYVSW7CJVLaz1WwcI7w+4s /P5cDZkr18ZS1Tu55W057lN56vRYr2lNJVH6UHgjqHge8NBRRSW0Qf65JO0dGrWC43 4uaU1lLxFVozw== Date: Wed, 01 Apr 2026 02:16:54 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH 1/6] dt-bindings: display/msm/gmu: Document Adreno 810 GMU Message-ID: <20260331-adreno-810-v1-1-725801dbb12b@pm.me> In-Reply-To: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> References: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 7233420edea383dfc51c8dcb5b4ddc11a8e24f9a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document Adreno 810 GMU in the dt-binding specification. Signed-off-by: Alexander Koskovich --- .../devicetree/bindings/display/msm/gmu.yaml | 32 ++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Docum= entation/devicetree/bindings/display/msm/gmu.yaml index e32056ae0f5d..2853f6aef966 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -299,6 +299,38 @@ allOf: required: - qcom,qmp =20 + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-810.0 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + - description: GPUSS DEMET clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - const: demet + - if: properties: compatible: --=20 2.53.0 From nobody Wed Apr 1 08:41:16 2026 Received: from mail-10628.protonmail.ch (mail-10628.protonmail.ch [79.135.106.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73D24318139 for ; Wed, 1 Apr 2026 02:17:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.28 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009841; cv=none; b=jdOuMAc248WzAknl0ZCH9n6jr2qwtrK+n0RePs45z6UdmqmYmfJe4msUfVYTi4zwu5jZ3vgCgYNUjyutaPs4D/EbJyKoDbcuvKW/Cpc6ehtTOASTnWyig99Q3DtqxTtizjjQIn1fXPJG2X31HvvCkEbamTR1v7KwA7M9iagNLXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009841; c=relaxed/simple; bh=5bDEwsQ78ZBznFWaDDl9Hwa+dW7MA5sil64tFmJKV4w=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Qy6geWZoJ9Ox5Yc5Jh8ZbEgkAsO94optKgbCfO1x+g1SdxTi33nk7RKArRUPFdveM//cvefjz/JDq7mEgCn2QAZhYGbOF1kLVI/MiRc6webW7KbEsbXld6n8MWeLLFiYgNCbThNUP9Zq/70qNqaBQsaNbU0xjecxCJBKWsbvogI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=jvh2HnAA; arc=none smtp.client-ip=79.135.106.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="jvh2HnAA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775009831; x=1775269031; bh=swaiMdjjcSgBCqEa91t2bbQx5mik4+A0jfff30QRHjE=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=jvh2HnAA+TrrO010+wipNHKmf3KgcSAo5Vm3AYaiBK4mobQpn0aqS3ZJFPDPaBB7P m2zcFVH5G2oNouUwi5/aEZH2BoWou52+QtfWuk3Hcj22asWB2PNTVMI8ON6XEvuKGL N20Y4hDUYyMYjKQ9RmtWQfLuiAKqJg3rPu2lolTdVl+29qIi6FX2tzzG/HyKvJRbTb g+9iPDkbGuE81GyANEhW8oXGJHhxor5kBwXb3l8dp/R4obzJQIJ9hhB+q9IvictAWx K7fmJlP8MPvfhph2hd5qaQDP2eLPOahtmoreghuKjv893v3kCICz8hsFtdDLfBY2Da SpAudeJ9/96pg== Date: Wed, 01 Apr 2026 02:17:04 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH 2/6] drm/msm/adreno: rename llc_mmio to cx_mmio Message-ID: <20260331-adreno-810-v1-2-725801dbb12b@pm.me> In-Reply-To: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> References: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: ce7482096adcf8a9dee2bb08bee2177983f69004 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This region is used for more than just LLCC, it also provides access to software fuse values (raytracing, etc). Rename relevant symbols from _llc to _cx for use in a follow up change that decouples this from LLCC. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 16 ++++++++-------- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 14 +++++++------- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 +- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index 916c5d99c4d1..e2f66ca0e319 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -947,7 +947,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsi= gned int state) =20 /* Turn on TCM (Tightly Coupled Memory) retention */ if (adreno_is_a7xx(adreno_gpu)) - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); + a6xx_cx_write(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL, 1); else if (!adreno_is_a8xx(adreno_gpu)) gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); =20 @@ -1215,7 +1215,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) if (!qcom_scm_is_available()) { dev_warn_once(gpu->dev->dev, "SCM is not available, poking fuse register\n"); - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + a6xx_cx_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); @@ -1236,7 +1236,7 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx= _gpu) * firmware, find out whether that's the case. The scm call * above sets the fuse register. */ - fuse_val =3D a6xx_llc_read(a6xx_gpu, + fuse_val =3D a6xx_cx_read(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE); adreno_gpu->has_ray_tracing =3D !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); @@ -1299,7 +1299,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) =20 /* Check to see if we are doing a cold or warm boot */ if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { - status =3D a6xx_llc_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D= 1 ? + status =3D a6xx_cx_read(a6xx_gpu, REG_A7XX_CX_MISC_TCM_RET_CNTL) =3D=3D = 1 ? GMU_WARM_BOOT : GMU_COLD_BOOT; } else if (gmu->legacy) { status =3D gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) =3D=3D 1 ? diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index e1eae6cb1e40..6ce14407007e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2078,14 +2078,14 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx= _gpu) * pagetables */ if (!a6xx_gpu->have_mmu500) { - a6xx_llc_write(a6xx_gpu, + a6xx_cx_write(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval); =20 /* * Program cacheability overrides to not allocate cache * lines on a write miss */ - a6xx_llc_rmw(a6xx_gpu, + a6xx_cx_rmw(a6xx_gpu, REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03); return; } @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->llc_mmio)) + if (IS_ERR(a6xx_gpu->cx_mmio)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2151,15 +2151,15 @@ static void a6xx_llc_slices_init(struct platform_de= vice *pdev, of_node_put(phandle); =20 if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->llc_mmio =3D msm_ioremap(pdev, "cx_mem"); + a6xx_gpu->cx_mmio =3D msm_ioremap(pdev, "cx_mem"); else - a6xx_gpu->llc_mmio =3D NULL; + a6xx_gpu->cx_mmio =3D NULL; =20 a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); =20 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); + a6xx_gpu->cx_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2560,7 +2560,7 @@ static int a6xx_read_speedbin(struct device *dev, str= uct a6xx_gpu *a6xx_gpu, return ret; =20 if (info->quirks & ADRENO_QUIRK_SOFTFUSE) { - *speedbin =3D a6xx_llc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMI= T_STATUS); + *speedbin =3D a6xx_cx_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT= _STATUS); *speedbin =3D A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*spe= edbin); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.h index eb431e5e00b1..e254d9711b30 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -102,7 +102,7 @@ struct a6xx_gpu { =20 bool has_whereami; =20 - void __iomem *llc_mmio; + void __iomem *cx_mmio; void *llc_slice; void *htw_llc_slice; bool have_mmu500; @@ -240,19 +240,19 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *g= pu) return true; } =20 -static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 ma= sk, u32 or) +static inline void a6xx_cx_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mas= k, u32 or) { - return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or); + return msm_rmw(a6xx_gpu->cx_mmio + (reg << 2), mask, or); } =20 -static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg) +static inline u32 a6xx_cx_read(struct a6xx_gpu *a6xx_gpu, u32 reg) { - return readl(a6xx_gpu->llc_mmio + (reg << 2)); + return readl(a6xx_gpu->cx_mmio + (reg << 2)); } =20 -static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 = value) +static inline void a6xx_cx_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 v= alue) { - writel(value, a6xx_gpu->llc_mmio + (reg << 2)); + writel(value, a6xx_gpu->cx_mmio + (reg << 2)); } =20 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \ diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 9e6f2ed69247..5af82d43f1e4 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -103,7 +103,7 @@ void a8xx_gpu_get_slice_info(struct msm_gpu *gpu) return; } =20 - slice_mask &=3D a6xx_llc_read(a6xx_gpu, + slice_mask &=3D a6xx_cx_read(a6xx_gpu, REG_A8XX_CX_MISC_SLICE_ENABLE_FINAL); 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smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=YNmxoMwn; arc=none smtp.client-ip=185.70.43.22 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="YNmxoMwn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775009836; x=1775269036; bh=ClZxRM9og3QbzwORt37XB7tis1sA81EoeK5k6nc4KbI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=YNmxoMwn7u6bv1+0NZaxEh2yeBpSibgn8Ups01LZRRF/EsEmGUQuL+B600txYdxRm ew488RSxOuqLMTwZ47TNnojNlXDV49EbHCMvjGuzJLIYAiZ+ZrCp8Ri2Fnaeg4y5Gf CMboSI0S0UEfBRwzWWPXPqllUTQSOjsFp7OTP5su0006rY5ly5lWQvEb65tGOP2nw2 u1JX8e3J7e56PZYmA8LjdNympEXzXzQIQEU9xPwDTTQoW65hGC5Knp4B8ZL/l6bnHl ERxpDZCBpX4NtFc++bXtkZK1dOslVyL78Lzf4xGVMcugGLr5erMjXT64fBncBTvWso SiSr/+j0D3EYg== Date: Wed, 01 Apr 2026 02:17:12 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH 3/6] drm/msm/adreno: set cx_mmio regardless of if platform has LLCC Message-ID: <20260331-adreno-810-v1-3-725801dbb12b@pm.me> In-Reply-To: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> References: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: f234432ef166ec93064e856b582302fd8c46ea80 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Platforms without a LLCC (e.g. milos) still need to be able to read and write to the cx_mem region. Previously if LLCC slices were unavailable the cx_mmio mapping was overwritten with ERR_PTR, causing a crash when the GMU later accessed cx_mem. Move the cx_mmio mapping out of a6xx_llc_slices_init() into a6xx_gpu_init() so that cx_mem mapping is independent of LLCC. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 ++++++++++++++++---------------= ---- 1 file changed, 17 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 6ce14407007e..eea18ae7c019 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2039,7 +2039,7 @@ static void a6xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct msm_gpu *gpu =3D &adreno_gpu->base; u32 cntl1_regval =3D 0; =20 - if (IS_ERR(a6xx_gpu->cx_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2098,7 +2098,7 @@ static void a7xx_llc_activate(struct a6xx_gpu *a6xx_g= pu) struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; struct msm_gpu *gpu =3D &adreno_gpu->base; =20 - if (IS_ERR(a6xx_gpu->cx_mmio)) + if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) return; =20 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) { @@ -2135,31 +2135,12 @@ static void a6xx_llc_slices_destroy(struct a6xx_gpu= *a6xx_gpu) static void a6xx_llc_slices_init(struct platform_device *pdev, struct a6xx_gpu *a6xx_gpu, bool is_a7xx) { - struct device_node *phandle; - /* No LLCC on non-RPMh (and by extension, non-GMU) SoCs */ if (adreno_has_gmu_wrapper(&a6xx_gpu->base)) return; =20 - /* - * There is a different programming path for A6xx targets with an - * mmu500 attached, so detect if that is the case - */ - phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); - a6xx_gpu->have_mmu500 =3D (phandle && - of_device_is_compatible(phandle, "arm,mmu-500")); - of_node_put(phandle); - - if (is_a7xx || !a6xx_gpu->have_mmu500) - a6xx_gpu->cx_mmio =3D msm_ioremap(pdev, "cx_mem"); - else - a6xx_gpu->cx_mmio =3D NULL; - a6xx_gpu->llc_slice =3D llcc_slice_getd(LLCC_GPU); a6xx_gpu->htw_llc_slice =3D llcc_slice_getd(LLCC_GPUHTW); - - if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_l= lc_slice)) - a6xx_gpu->cx_mmio =3D ERR_PTR(-EINVAL); } =20 #define GBIF_CLIENT_HALT_MASK BIT(0) @@ -2621,6 +2602,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devic= e *dev) struct platform_device *pdev =3D priv->gpu_pdev; struct adreno_platform_config *config =3D pdev->dev.platform_data; const struct adreno_info *info =3D config->info; + struct device_node *phandle; struct device_node *node; struct a6xx_gpu *a6xx_gpu; struct adreno_gpu *adreno_gpu; @@ -2656,6 +2638,20 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) =20 a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); =20 + /* + * There is a different programming path for A6xx targets with an + * mmu500 attached, so detect if that is the case + */ + phandle =3D of_parse_phandle(pdev->dev.of_node, "iommus", 0); + a6xx_gpu->have_mmu500 =3D (phandle && + of_device_is_compatible(phandle, "arm,mmu-500")); + of_node_put(phandle); + + if (is_a7xx || !a6xx_gpu->have_mmu500) + a6xx_gpu->cx_mmio =3D msm_ioremap(pdev, "cx_mem"); + else + a6xx_gpu->cx_mmio =3D NULL; + ret =3D a6xx_set_supported_hw(&pdev->dev, a6xx_gpu, info); if (ret) { a6xx_llc_slices_destroy(a6xx_gpu); --=20 2.53.0 From nobody Wed Apr 1 08:41:16 2026 Received: from mail-244122.protonmail.ch (mail-244122.protonmail.ch [109.224.244.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4EDEF1862 for ; Wed, 1 Apr 2026 02:17:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.122 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009854; cv=none; b=chsuhqZko38eHBfgABmIz3je5jQfZOJAqn5FxtLOq0Hxah/aJ/uBxUQHDoIVfm9ne8ZcRC04tvtV+3NLRVAIo83H+cbDt3oWGSxSnwatglNTYx/BT5upoqsJWKGQGGzOfMjTimQLqCXHFh3nR+1CEVRYqxM1BaXt61dpIPCYeIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009854; c=relaxed/simple; bh=73Psf8RUrYZQFi6blmvy3tdL4+HY9hFI5sWBh7+SDko=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pND40rNXhzqx5TMVHDfMS/seAc7Ge/JgtkeHkn5ri5C9Bqa0xAztx57cG2pOdOWSSPA7BfeG7xTAw1SggR6PFmrYyrJ6QVuDMbOeWWpdL2S2W10uVU5ZliM7dtbk6AwI9tBmlQkA/+oIpE3ujts22zxN7nQsfGV0kF7zRzIZBdg= ARC-Authentication-Results: i=1; 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charset="utf-8" A8XX GPUs have two sets of protect registers: 64 global slots and 16 pipe specific slots. The last-span-unbound feature is only available on pipe protect registers, and should always target pipe slot 15. This matches the downstream driver which hardcodes pipe slot 15 for all A8XX GPUs (GRAPHICS.LA.15.0.r1) and resolves protect errors on A810. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a8xx_gpu.c index 5af82d43f1e4..63387ee9b04a 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -252,11 +252,12 @@ static void a8xx_set_cp_protect(struct msm_gpu *gpu) } =20 /* - * Last span feature is only supported on PIPE specific register. - * So update those here + * Last span setting is only being applied to the last pipe specific + * register. Hence duplicate the last span from protect reg into the + * BR and BV protect reg pipe 15. */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); - a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max= ), final_cfg); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); + a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(15), final_cfg); =20 a8xx_aperture_clear(gpu); } --=20 2.53.0 From nobody Wed Apr 1 08:41:16 2026 Received: from mail-106120.protonmail.ch (mail-106120.protonmail.ch [79.135.106.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A9E81A3172 for ; Wed, 1 Apr 2026 02:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009868; cv=none; b=KUHMdPlZSTKY4CqqKma1k68kfS+8R4HpWdu73dU56ys7OMm7dj0EAb28IyBA4nQtdQUVXlux81BjsE8nMRr/tawdHOWCOZeGQiiy3gyb18uoFbJBYFXkdynQ6vbF5Nf1UnDhI8ZVegx3qkKTTw6Kn9VLILxOs9nNkgavCU3m8nw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775009868; c=relaxed/simple; bh=kywi2quHqF2VmkIRACmAiSwBoPwAqfyAl564Fg/SWe8=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ntUX7BaRK9UplxjRqpjLyQ4whj8UFZP3uSPs6OfFfOkI9R9vxI1xguYFyj+3LcF23EBobkAH/uPgY5EezF+ox86VxC4smXDQW6zTI8Cb2hzdCtMSqtLjdBgT8KeqEqKpoq6pTNe6H7XvjXQfbNv7SydlcBAnHLWW+9xouOBQRgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=P4Kn0fmz; arc=none smtp.client-ip=79.135.106.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="P4Kn0fmz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775009857; x=1775269057; bh=GNz2muK+gIGZE1XVz2JEGj9VN/9lWf0LL0UI4iVUxMg=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=P4Kn0fmzHvscsd0boWdfHk1jQ45/p5Wl5nUVLqabo2C41M/c01pMTn0QmDsRV+fom Hgzi6LrLJtcSrXWnx2XMOiK4j54nnTNJ9INSupBCbAyB8kjmwH2nnIHztFeqN4Fhcd nJ29ZWWuONkxG/qPl8SkR1L0r9VE5FPSJ13Fa8MNak/vUDftL3gk1yXBkhbKj3jZ4S YEuiGBcKOE2ALz0LthaqpBX1Bw+aDe9E7vcIO88Z/v2Vt1kqCWOAqBOaldjago6Ftm cYGqHseMApjgAZq2tLmDn16v9PZS5ADzkUGk/mFItphbZuuOq1Ytq9I9KCm+N5yf2g 4SwyCJh5wqIJg== Date: Wed, 01 Apr 2026 02:17:31 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH 5/6] drm/msm/adreno: add Adreno 810 GPU support Message-ID: <20260331-adreno-810-v1-5-725801dbb12b@pm.me> In-Reply-To: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> References: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 9195d3451ce1f53dcd24c6155c9dcca70316c1a5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add catalog entry and register configuration for the Adreno 810 found in Qualcomm SM7635 (Milos) based devices. Signed-off-by: Alexander Koskovich --- drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 271 ++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 + 2 files changed, 276 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/ms= m/adreno/a6xx_catalog.c index 550ff3a9b82e..0d7d9c86205e 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c @@ -1799,6 +1799,240 @@ static const struct adreno_reglist_pipe x285_dyn_pw= rup_reglist_regs[] =3D { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); =20 +static const struct adreno_reglist_pipe a810_nonctxt_regs[] =3D { + { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00f80800, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_BR)= }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0x10010000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0x00000002, BIT(PIPE_BV) |= BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000003, BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0x00000023, BIT(PIPE_BV) }, /* Avoid partia= l waves at VFD */ + { REG_A8XX_PC_CHICKEN_BITS_2, 0x00000200, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0x00500000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0x00000068, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0x00000007, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0x00004000, BIT(PIPE_BR) }, + { REG_A8XX_RBBM_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, 0x00000001, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_WAIT_IDLE_CLOCKS_CNTL2, 0x00000030, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_GBIF_GX_CONFIG, 0x010240e0, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x22122212, BIT(PIPE_NONE) }, + { REG_A8XX_RBBM_CGC_P2S_CNTL, 0x00000040, BIT(PIPE_NONE) }, + /* + * BIT(22): Disable PS out of order retire + * BIT(23): Enable half wave mode and MM instruction src&dst is half prec= ision + */ + { REG_A7XX_SP_CHICKEN_BITS_2, BIT(22) | BIT(23), BIT(PIPE_NONE) }, + { REG_A7XX_SP_CHICKEN_BITS_3, 0x00300000, BIT(PIPE_NONE) }, + { REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x0000003f, BIT(PIPE_NONE) }, + { REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, 0x00000080, BIT(PIPE_NONE) }, + { REG_A7XX_SP_READ_SEL, 0x0001ff00, BIT(PIPE_NONE) }, + { REG_A6XX_TPL1_DBG_ECO_CNTL, 0x10000000, BIT(PIPE_NONE) }, + /* BIT(26): Disable final clamp for bicubic filtering */ + { REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x04000720, BIT(PIPE_NONE) }, + { REG_A6XX_UCHE_MODE_CNTL, 0x80080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_MODE_CNTL, 0x00001000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CCHE_CACHE_WAYS, 0x00000800, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_CACHE_WAYS, 0x00080000, BIT(PIPE_NONE) }, + { REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, 0x00000020, BIT(PIPE_NONE) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0x00500050, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0x00600060, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0x00200020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0x00100020, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0x00000001, BIT(PIPE_BV) | BIT(PIPE_B= R) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0x00900000, BIT(PIPE_BR) }, + { }, +}; + +static const u32 a810_protect_regs[] =3D { + A6XX_PROTECT_RDONLY(0x00000, 0x03a3), + A6XX_PROTECT_RDONLY(0x003b4, 0x008b), + A6XX_PROTECT_NORDWR(0x00440, 0x001f), + A6XX_PROTECT_RDONLY(0x00580, 0x005f), + A6XX_PROTECT_NORDWR(0x005e0, 0x011f), + A6XX_PROTECT_RDONLY(0x0074a, 0x0005), + A6XX_PROTECT_RDONLY(0x00759, 0x0026), + A6XX_PROTECT_RDONLY(0x00789, 0x0000), + A6XX_PROTECT_RDONLY(0x0078c, 0x0013), + A6XX_PROTECT_NORDWR(0x00800, 0x0029), + A6XX_PROTECT_NORDWR(0x00837, 0x00af), + A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), + A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), + A6XX_PROTECT_NORDWR(0x009b1, 0x0250), + A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), + A6XX_PROTECT_RDONLY(0x00df0, 0x0000), + A6XX_PROTECT_NORDWR(0x00df1, 0x0000), + A6XX_PROTECT_NORDWR(0x00e01, 0x0000), + A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), + A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), + A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), + A6XX_PROTECT_NORDWR(0x08600, 0x01ff), + A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), + A6XX_PROTECT_RDONLY(0x08f00, 0x0000), + A6XX_PROTECT_NORDWR(0x08f01, 0x01be), + A6XX_PROTECT_NORDWR(0x09600, 0x01ff), + A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), + A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), + A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), + A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), + A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), + A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), + A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), + A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), + A6XX_PROTECT_NORDWR(0x18400, 0x003f), + A6XX_PROTECT_RDONLY(0x18440, 0x013f), + A6XX_PROTECT_NORDWR(0x18580, 0x1fff), + A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), + A6XX_PROTECT_NORDWR(0x1f400, 0x0477), + A6XX_PROTECT_RDONLY(0x1f878, 0x0787), + A6XX_PROTECT_NORDWR(0x1f930, 0x0329), + A6XX_PROTECT_NORDWR(0x20000, 0x1fff), + A6XX_PROTECT_NORDWR(0x27800, 0x007f), + A6XX_PROTECT_RDONLY(0x27880, 0x0381), + A6XX_PROTECT_NORDWR(0x27882, 0x0001), + /* CP_PROTECT_REG[46, 62] are left untouched! */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + A6XX_PROTECT_NORDWR(0x27c02, 0x0000), +}; +DECLARE_ADRENO_PROTECT(a810_protect, 64); + +static const uint32_t a810_pwrup_reglist_regs[] =3D { + REG_A6XX_UCHE_MODE_CNTL, + REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, + REG_A8XX_UCHE_GBIF_GX_CONFIG, + REG_A8XX_UCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_MODE_CNTL, + REG_A8XX_UCHE_CCHE_CACHE_WAYS, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN, + REG_A8XX_UCHE_CCHE_GC_GMEM_RANGE_MIN + 1, + REG_A8XX_UCHE_WRITE_THRU_BASE, + REG_A8XX_UCHE_WRITE_THRU_BASE + 1, + REG_A8XX_UCHE_TRAP_BASE, + REG_A8XX_UCHE_TRAP_BASE + 1, + REG_A8XX_UCHE_CLIENT_PF, + REG_A8XX_VSC_BIN_SIZE, + REG_A8XX_RB_CMP_NC_MODE_CNTL, + REG_A7XX_SP_HLSQ_TIMEOUT_THRESHOLD_DP, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, + REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN + 1, + REG_A7XX_SP_READ_SEL, +}; +DECLARE_ADRENO_REGLIST_LIST(a810_pwrup_reglist); + +static const u32 a810_ifpc_reglist_regs[] =3D { + REG_A8XX_RBBM_NC_MODE_CNTL, + REG_A8XX_RBBM_SLICE_INTERFACE_HANG_INT_CNTL, + REG_A8XX_RBBM_SLICE_NC_MODE_CNTL, + REG_A6XX_SP_NC_MODE_CNTL, + REG_A7XX_SP_CHICKEN_BITS_2, + REG_A7XX_SP_CHICKEN_BITS_3, + REG_A6XX_SP_PERFCTR_SHADER_MASK, + REG_A6XX_TPL1_NC_MODE_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL, + REG_A6XX_TPL1_DBG_ECO_CNTL1, + REG_A8XX_RBBM_PERFCTR_CNTL, + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(1), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(2), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(3), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(4), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(5), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(6), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(7), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(8), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(9), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(10), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(11), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(12), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(13), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(14), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(15), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(16), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(17), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(18), + REG_A8XX_TPL1_BICUBIC_WEIGHTS_TABLE(19), + REG_A8XX_CP_PROTECT_GLOBAL(0), + REG_A8XX_CP_PROTECT_GLOBAL(1), + REG_A8XX_CP_PROTECT_GLOBAL(2), + REG_A8XX_CP_PROTECT_GLOBAL(3), + REG_A8XX_CP_PROTECT_GLOBAL(4), + REG_A8XX_CP_PROTECT_GLOBAL(5), + REG_A8XX_CP_PROTECT_GLOBAL(6), + REG_A8XX_CP_PROTECT_GLOBAL(7), + REG_A8XX_CP_PROTECT_GLOBAL(8), + REG_A8XX_CP_PROTECT_GLOBAL(9), + REG_A8XX_CP_PROTECT_GLOBAL(10), + REG_A8XX_CP_PROTECT_GLOBAL(11), + REG_A8XX_CP_PROTECT_GLOBAL(12), + REG_A8XX_CP_PROTECT_GLOBAL(13), + REG_A8XX_CP_PROTECT_GLOBAL(14), + REG_A8XX_CP_PROTECT_GLOBAL(15), + REG_A8XX_CP_PROTECT_GLOBAL(16), + REG_A8XX_CP_PROTECT_GLOBAL(17), + REG_A8XX_CP_PROTECT_GLOBAL(18), + REG_A8XX_CP_PROTECT_GLOBAL(19), + REG_A8XX_CP_PROTECT_GLOBAL(20), + REG_A8XX_CP_PROTECT_GLOBAL(21), + REG_A8XX_CP_PROTECT_GLOBAL(22), + REG_A8XX_CP_PROTECT_GLOBAL(23), + REG_A8XX_CP_PROTECT_GLOBAL(24), + REG_A8XX_CP_PROTECT_GLOBAL(25), + REG_A8XX_CP_PROTECT_GLOBAL(26), + REG_A8XX_CP_PROTECT_GLOBAL(27), + REG_A8XX_CP_PROTECT_GLOBAL(28), + REG_A8XX_CP_PROTECT_GLOBAL(29), + REG_A8XX_CP_PROTECT_GLOBAL(30), + REG_A8XX_CP_PROTECT_GLOBAL(31), + REG_A8XX_CP_PROTECT_GLOBAL(32), + REG_A8XX_CP_PROTECT_GLOBAL(33), + REG_A8XX_CP_PROTECT_GLOBAL(34), + REG_A8XX_CP_PROTECT_GLOBAL(35), + REG_A8XX_CP_PROTECT_GLOBAL(36), + REG_A8XX_CP_PROTECT_GLOBAL(37), + REG_A8XX_CP_PROTECT_GLOBAL(38), + REG_A8XX_CP_PROTECT_GLOBAL(39), + REG_A8XX_CP_PROTECT_GLOBAL(40), + REG_A8XX_CP_PROTECT_GLOBAL(41), + REG_A8XX_CP_PROTECT_GLOBAL(42), + REG_A8XX_CP_PROTECT_GLOBAL(43), + REG_A8XX_CP_PROTECT_GLOBAL(44), + REG_A8XX_CP_PROTECT_GLOBAL(45), + REG_A8XX_CP_PROTECT_GLOBAL(63), +}; +DECLARE_ADRENO_REGLIST_LIST(a810_ifpc_reglist); + +static const struct adreno_reglist_pipe a810_dyn_pwrup_reglist_regs[] =3D { + { REG_A8XX_CP_PROTECT_CNTL_PIPE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_CP_PROTECT_PIPE(15), 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_GRAS_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_RB_CCU_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CCU_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_NC_MODE_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_RESOLVE_PREFETCH_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_CMP_DBG_ECO_CNTL, 0, BIT(PIPE_BR) }, + { REG_A8XX_RB_GC_GMEM_PROTECT, 0, BIT(PIPE_BR) }, + { REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE, 0, BIT(PIPE_BR) }, + { REG_A8XX_VPC_FLATSHADE_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_1, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_2, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_3, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_PC_CHICKEN_BITS_4, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A6XX_PC_AUTO_VERTEX_STRIDE, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_VIS_STREAM_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, + { REG_A8XX_PC_CONTEXT_SWITCH_STABILIZE_CNTL_1, 0, BIT(PIPE_BR) | BIT(PIPE= _BV) }, + { REG_A8XX_VFD_CB_BV_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BR_THRESHOLD, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_BUSY_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A8XX_VFD_CB_LP_REQ_CNT, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, + { REG_A7XX_VFD_DBG_ECO_CNTL, 0, BIT(PIPE_BR) | BIT(PIPE_BV) }, +}; +DECLARE_ADRENO_REGLIST_PIPE_LIST(a810_dyn_pwrup_reglist); + static const struct adreno_reglist_pipe a840_nonctxt_regs[] =3D { { REG_A8XX_CP_SMMU_STREAM_ID_LPAC, 0x00000101, BIT(PIPE_NONE) }, { REG_A8XX_GRAS_DBG_ECO_CNTL, 0x00000800, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -2193,6 +2427,43 @@ static const struct adreno_info a8xx_gpus[] =3D { { 252, 2 }, { 221, 3 }, ), + }, { + .chip_ids =3D ADRENO_CHIP_IDS(0x44010000), + .family =3D ADRENO_8XX_GEN1, + .fw =3D { + [ADRENO_FW_SQE] =3D "gen80300_sqe.fw", + [ADRENO_FW_GMU] =3D "gen80300_gmu.bin", + }, + .gmem =3D SZ_512K + SZ_64K, + .inactive_period =3D DRM_MSM_INACTIVE_PERIOD, + .quirks =3D ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV | + ADRENO_QUIRK_PREEMPTION | + ADRENO_QUIRK_IFPC, + .funcs =3D &a8xx_gpu_funcs, + .zapfw =3D "gen80300_zap.mbn", + .a6xx =3D &(const struct a6xx_info) { + .protect =3D &a810_protect, + .nonctxt_reglist =3D a810_nonctxt_regs, + .pwrup_reglist =3D &a810_pwrup_reglist, + .dyn_pwrup_reglist =3D &a810_dyn_pwrup_reglist, + .ifpc_reglist =3D &a810_ifpc_reglist, + .gbif_cx =3D a840_gbif, + .max_slices =3D 1, + .gmu_chipid =3D 0x8030000, + .bcms =3D (const struct a6xx_bcm[]) { + { .name =3D "SH0", .buswidth =3D 16 }, + { .name =3D "MC0", .buswidth =3D 4 }, + { + .name =3D "ACV", + .fixed =3D true, + .perfmode =3D BIT(2), + .perfmode_bw =3D 10687500, + }, + { /* sentinel */ }, + }, + }, + .preempt_record_size =3D 4558 * SZ_1K, } }; =20 diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/= adreno/adreno_gpu.h index c0ee544ce257..d474d88b9152 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -596,6 +596,11 @@ static inline int adreno_is_a8xx(struct adreno_gpu *gp= u) return gpu->info->family >=3D ADRENO_8XX_GEN1; } =20 +static inline int adreno_is_a810(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] =3D=3D 0x44010000; +} + static inline int adreno_is_x285(struct adreno_gpu *gpu) { return gpu->info->chip_ids[0] =3D=3D 0x44070001; --=20 2.53.0 From nobody Wed Apr 1 08:41:16 2026 Received: from mail-24417.protonmail.ch (mail-24417.protonmail.ch [109.224.244.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 463731B4223 for ; Wed, 1 Apr 2026 02:17:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.17 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="KRG3jemk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1775009871; x=1775269071; bh=zy8587+oFNVsqxwUuWfVfQ5DN4CfY+6dqyufp9WdTwk=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=KRG3jemkGXXGqSwXVOHdT+nosBtTB5WkA6LGtLMe8iM//j+ee/5yN/voVOHLFA7y2 0B1cM8zYg4R/fY0kd67XJE8IIAtjigCQjzLJbum9eFw9omMUYcdPhPByKbFO4TVKmk HPeTKXSZjkyWjqIuXPn5A51LXeWnLkFKjZuFsAiR3vMPQU7PEs43kXboIhhcyRw4VJ pK4V20njICJU+OZvz2j4BjrHlAP9GjXvRD5gR68oK9t+Lr2ZX2mu6Q0ymh+ZtokxsJ Wn6ia1EdZi0juV2Pbd1XiQ8C6RqmYmtrqYdpuurL++HYlEcY3FwrOyT0zBgvls3gbQ j8vUuEk0TSPOQ== Date: Wed, 01 Apr 2026 02:17:44 +0000 To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Akhil P Oommen , Bjorn Andersson From: Alexander Koskovich Cc: Luca Weiss , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH 6/6] arm64: dts: qcom: milos: Add Adreno 810 GPU and GMU nodes Message-ID: <20260331-adreno-810-v1-6-725801dbb12b@pm.me> In-Reply-To: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> References: <20260331-adreno-810-v1-0-725801dbb12b@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: f8721f5a201037d2b10c26d63dc15ceca7ba8756 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add GPU and GMU devicetree nodes for the Adreno 810 GPU found on Qualcomm SM7635 (Milos) based devices. Signed-off-by: Alexander Koskovich --- arch/arm64/boot/dts/qcom/milos.dtsi | 148 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 621f05820826..a8feb0339804 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1224,6 +1225,153 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + gpu: gpu@3d00000 { + compatible =3D "qcom,adreno-44010000", "qcom,adreno"; + reg =3D <0x0 0x03d00000 0x0 0x40000>, + <0x0 0x03d9e000 0x0 0x2000>, + <0x0 0x03d61000 0x0 0x800>; + reg-names =3D "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + + interrupts =3D ; + + iommus =3D <&adreno_smmu 0 0x0>; + + operating-points-v2 =3D <&gpu_opp_table>; + + qcom,gmu =3D <&gmu>; + #cooling-cells =3D <2>; + + interconnects =3D <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "gfx-mem"; + + status =3D "disabled"; + + gpu_zap_shader: zap-shader { + memory-region =3D <&gpu_microcode_mem>; + }; + + gpu_opp_table: opp-table { + compatible =3D "operating-points-v2-adreno", + "operating-points-v2"; + + opp-264000000 { + opp-hz =3D /bits/ 64 <264000000>; + opp-level =3D ; + opp-peak-kBps =3D <2136718>; + qcom,opp-acd-level =3D <0xc8295ffd>; + }; + + opp-362000000 { + opp-hz =3D /bits/ 64 <362000000>; + opp-level =3D ; + opp-peak-kBps =3D <2136718>; + qcom,opp-acd-level =3D <0xc02c5ffd>; + }; + + opp-510000000 { + opp-hz =3D /bits/ 64 <510000000>; + opp-level =3D ; + opp-peak-kBps =3D <3972656>; + qcom,opp-acd-level =3D <0x882b5ffd>; + }; + + opp-644000000 { + opp-hz =3D /bits/ 64 <644000000>; + opp-level =3D ; + opp-peak-kBps =3D <5285156>; + qcom,opp-acd-level =3D <0x882a5ffd>; + }; + + opp-688000000 { + opp-hz =3D /bits/ 64 <688000000>; + opp-level =3D ; + opp-peak-kBps =3D <6074218>; + qcom,opp-acd-level =3D <0x882a5ffd>; + }; + + opp-763000000 { + opp-hz =3D /bits/ 64 <763000000>; + opp-level =3D ; + opp-peak-kBps =3D <6671875>; + qcom,opp-acd-level =3D <0xa8295ffd>; + }; + + opp-895000000 { + opp-hz =3D /bits/ 64 <895000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + qcom,opp-acd-level =3D <0x88295ffd>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-level =3D ; + opp-peak-kBps =3D <8171875>; + qcom,opp-acd-level =3D <0xa8285ffd>; + }; + + opp-1050000000 { + opp-hz =3D /bits/ 64 <1050000000>; + opp-level =3D ; + opp-peak-kBps =3D <18597656>; + qcom,opp-acd-level =3D <0x88285ffd>; + }; + }; + }; + + gmu: gmu@3d37000 { + compatible =3D "qcom,adreno-gmu-810.0", "qcom,adreno-gmu"; + reg =3D <0x0 0x03d37000 0x0 0x68000>; + reg-names =3D "gmu"; + + interrupts =3D , + ; + interrupt-names =3D "hfi", "gmu"; + + clocks =3D <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_DEMET_CLK>; + clock-names =3D "ahb", + "gmu", + "cxo", + "axi", + "memnoc", + "hub", + "demet"; + + power-domains =3D <&gpucc GPU_CC_CX_GDSC>, + <&gxclkctl GX_CLKCTL_GX_GDSC>; + power-domain-names =3D "cx", + "gx"; + + iommus =3D <&adreno_smmu 5 0x0>; + + qcom,qmp =3D <&aoss_qmp>; + + operating-points-v2 =3D <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-350000000 { + opp-hz =3D /bits/ 64 <350000000>; + opp-level =3D ; + }; + + opp-650000000 { + opp-hz =3D /bits/ 64 <650000000>; + opp-level =3D ; + }; + }; + }; + gxclkctl: clock-controller@3d64000 { compatible =3D "qcom,milos-gxclkctl"; reg =3D <0x0 0x03d64000 0x0 0x6000>; --=20 2.53.0