From nobody Wed Apr 1 11:14:34 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012018.outbound.protection.outlook.com [52.101.48.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CD5138737F for ; Mon, 30 Mar 2026 16:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.18 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774888649; cv=fail; b=f64p/71HWQ7/qihAETEBMqRVGuDifMhLpCRzhdgDljxd2uvlJA8pKAgB1Hn9/6czWxZ28uM9iDAocjfHeQez36w9Gz9iJB4bg692phRoHhT+lTxH9qCs5KYWSDY7p6TobqOQ7zVk1tGAGwgqlOslzJyda81LAgJcW8Xaq25YJzo= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774888649; c=relaxed/simple; bh=ublNaOqB1BiMCHvxt+QqC4fekr+3n/dEOAn2VOFvSzU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XS8uSnxxzd2xW8fGVc8yXS6j+V4/FLkqinR4YJTGmQvRzgjVZ+xXCYa47NzqSYrzCpdGeqlKlr88/b5+YdtEb/ncAew+j8/tUwg6TdOKpyGCPDD7vCi5kHRZfdOnCxnIWWcScaKrc1ByppDMO8gaQ+Sq8j6GXgyRnr0KVg9vuss= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=wRPISTed; arc=fail smtp.client-ip=52.101.48.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="wRPISTed" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Y4FLYpT2uym4jSd2lV7fmLYuAriIkrvCPZCk7k1rM2SeB7G7pCjWJvRialwwLWBOifGGnFiRI8kLRKqT/a+ZEqjcpDXtBYfWQZ5AN2z0dG1bEb4yW7Jp7xBgFXkZ9uNHJg5BsIABvw56KjMreMxXElGDDYNgzXR9JN3eLe6+/2hgHbQiSBu/+1w8zznwBlJmq1CE8rY9gS9HKPr7t5teCkvarHah51O4QuINjdVWZmDV7T7hAaU+Ez1xN6Ji46mFgRx8Oa6C9wSxyKiBc/9rr40KJildnxYtPVvlNCoy62xbn1DpgAmeFrIQ8kihWn12ZmS27btt1iU54um/iGju+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cAvxypEaS75UACMOooZFFDs9ezXsxmY0hlODqbX7HZk=; b=WMe38fVLo7hBjhgwZE3K5816qwa/zBgfFKDp9L3ttK9miICnRnUTqYxyVSv4dwvbM7c5osNSRbaFn85MPNcA4rrCyrNsSN9fzXisSYaoj0h/DDX1BOe+TkrNROdsELD5pO7mIq1Lhh4LwqLp7E06VGUMMJ9eZzjaRvy7NQBaP+fdluza4yKIB3faVcK/zT2xZtnzwZa7VDegDUADYvx1IxmIiUU6Bh3SLIMgOxkQJBQ0MuTBwMtn+XnftqH5jNnHVNGoNgvk0rNAnnJhmPLR0S0cHFFNS84le2ZEE9hpxJSKmeKPaqL/dmNNndW+dAmol7NZfVw25xCRVp0ANoKBxQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cAvxypEaS75UACMOooZFFDs9ezXsxmY0hlODqbX7HZk=; b=wRPISTed9wAe0+u1P2wbAzPTiKh7Qt7xkzxEcKTxamIEGmdyT69WAD6LiBWTcAJbynEtEeBikk+JqD51dBYDyOqGyJKx10DUryKhLjeByslIcjHdqWTzzGECuLfQox4yVcKMDOnaIAGbKE+yrkmlg+oithYGNdreHiYgKun0rWo= Received: from SA0PR12CA0016.namprd12.prod.outlook.com (2603:10b6:806:6f::21) by MW3PR12MB4363.namprd12.prod.outlook.com (2603:10b6:303:56::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.15; Mon, 30 Mar 2026 16:37:21 +0000 Received: from SN1PEPF0002636B.namprd02.prod.outlook.com (2603:10b6:806:6f:cafe::e4) by SA0PR12CA0016.outlook.office365.com (2603:10b6:806:6f::21) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9745.28 via Frontend Transport; Mon, 30 Mar 2026 16:36:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF0002636B.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.21 via Frontend Transport; Mon, 30 Mar 2026 16:37:21 +0000 Received: from SATLEXMB04.amd.com (10.181.40.145) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.17; Mon, 30 Mar 2026 11:37:19 -0500 Received: from satlexmb07.amd.com (10.181.42.216) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 11:37:19 -0500 Received: from xsjlizhih51.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.17 via Frontend Transport; Mon, 30 Mar 2026 11:37:18 -0500 From: Lizhi Hou To: , , , , CC: David Zhang , , , , Hayden Laccabue , Lizhi Hou Subject: [PATCH V1 5/6] accel/amdxdna: Create common SMU interfaces for AIE2 and AIE4 Date: Mon, 30 Mar 2026 09:37:04 -0700 Message-ID: <20260330163705.3153647-6-lizhi.hou@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330163705.3153647-1-lizhi.hou@amd.com> References: <20260330163705.3153647-1-lizhi.hou@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: lizhi.hou@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636B:EE_|MW3PR12MB4363:EE_ X-MS-Office365-Filtering-Correlation-Id: 4be920e5-e279-45fe-fa04-08de8e7a9d85 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|376014|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: ASBEgBgPaJApOVKUoak6linnqNsxgCQt0E5YN/cfGIWKO+hohmGx2BkUBeBNB9z9P4cROeyv4GSF8RbqrZYeAJhDVFdEX7RWyBPse26ad4uTa0NRIHYC3DeHScWRbQwBW7TF0YJSd690bJbirsGm9fMe3XMQuxE5nNG6CSfWwsa9n9fNq/SpYP9wEdq52IcnAb6IFfyWmpnO7igGtuVIiiYmMH3paThWdv9tiwZ3OOZpTlRqQfzKz6b6sdLdgibb6U05pP0geOG0BbYAwrd93NT3XpW+4IN+tc0zvsL2RBWyrBnN4LGRVEnjW/4HCgp43jR45TtCwMtFRQ7FvEmhtUMbKk1HWkfXF0ko4qn5rjqX2HUZaSl3yWoKDL4ehS03iMfqURl9FvK0VgpiO/fX57wsHd1CB9i1tHQyJJoW/ilvrLY6vohZOZVp+4upSUNKVqU4mHaDZohdNHwcK6NqgptWeo1+2Rs4pvdrnP2mO50JvMSdrvth574mY20dnNJ0j9ggPSXw7t8pZXWyKSEhTVJi3Y+9JmdkG1qip1hjOelsz9jeeTWEK3ozta0OcDMhVwXTFv9gbW8k1pV4EjeWOutDpLTa6JpxuYm7TQcNpjn1x6aTUknmqM1Cb5E4u69Ja+nsAfABq/vkQl/LPHDwFC1NpOP9Vvyy3ziYyHRtECqs87s0vnw5oZlRr7Q0WoCSo/j2vH6M0A9E14nlto7J1NHl/SzuYqlkRuBMXNWMmvqR/Ng6mwvh0nrBpLH1REx4bNO5f0z+DlIA+jsfwRP3tg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(376014)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8A1l6fFbH/oQKYB2QjmmCMW4oisfU/KIXLkx1a3kP6CYSl5O4mLcFkUSc+t++xpnCDKUW3iWIFQymQyOI1M4tjn6K+M68UNJ1sV3UGukkWBx/FMikWsiDhOqHXOUgQOLh+ORtKErzLKzaUt4M0WOJFJqn3ikAz0MRNffGJF46ckxYhbwFaLM/p5Sd9FekSgFbvvbervPrfDEjxBTPudsbpcPKo66ONIwh16atOs4wvGSdXouNC3PtYiAde5ASbTML+P6MFYsvb2s2r4d6HQaUDvt5rJ544I2dIWqkkKHZ3JxAkA7QYVjiT52NIrMdGYOqh3gZwXqSGIpH/fxnJcZON5aiXk2RC2qabMCO1EMtwlFko2UwA3XWnTcIopfQJN2uO9VRh95SGc9OJd73NF/KGQD8a3Szq/nWtlO9l/II6Su/3PKLBgv9GcRZe9FjjK7 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Mar 2026 16:37:21.2415 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4be920e5-e279-45fe-fa04-08de8e7a9d85 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4363 Content-Type: text/plain; charset="utf-8" From: David Zhang AIE2 and AIE4 use similar interfaces to the SMU (System Management Unit). Move the SMU implementation into aie_smu.c and provide common interfaces for both platforms. This allows AIE2 and AIE4 to share the same implementation and reduces code duplication. Co-developed-by: Hayden Laccabue Signed-off-by: Hayden Laccabue Signed-off-by: David Zhang Signed-off-by: Lizhi Hou Reviewed-by: Mario Limonciello (AMD) --- drivers/accel/amdxdna/Makefile | 2 +- drivers/accel/amdxdna/aie.h | 25 +++++ drivers/accel/amdxdna/aie2_pci.c | 22 ++++- drivers/accel/amdxdna/aie2_pci.h | 20 ---- drivers/accel/amdxdna/aie2_smu.c | 156 ------------------------------ drivers/accel/amdxdna/aie_smu.c | 153 +++++++++++++++++++++++++++++ drivers/accel/amdxdna/npu1_regs.c | 21 ++++ drivers/accel/amdxdna/npu4_regs.c | 26 +++++ 8 files changed, 245 insertions(+), 180 deletions(-) delete mode 100644 drivers/accel/amdxdna/aie2_smu.c create mode 100644 drivers/accel/amdxdna/aie_smu.c diff --git a/drivers/accel/amdxdna/Makefile b/drivers/accel/amdxdna/Makefile index d3c0fe765a8b..79369e497540 100644 --- a/drivers/accel/amdxdna/Makefile +++ b/drivers/accel/amdxdna/Makefile @@ -3,12 +3,12 @@ amdxdna-y :=3D \ aie.o \ aie_psp.o \ + aie_smu.o \ aie2_ctx.o \ aie2_error.o \ aie2_message.o \ aie2_pci.o \ aie2_pm.o \ - aie2_smu.o \ aie2_solver.o \ aie4_message.o \ aie4_pci.o \ diff --git a/drivers/accel/amdxdna/aie.h b/drivers/accel/amdxdna/aie.h index 423ed34af9ee..ba4c9ee21823 100644 --- a/drivers/accel/amdxdna/aie.h +++ b/drivers/accel/amdxdna/aie.h @@ -12,6 +12,7 @@ #define AIE_TIMEOUT 1000000 /* us */ =20 struct psp_device; +struct smu_device; =20 struct aie_device { struct amdxdna_dev *xdna; @@ -24,6 +25,7 @@ struct aie_device { unsigned long feature_mask; =20 struct psp_device *psp_hdl; + struct smu_device *smu_hdl; }; =20 #define DECLARE_AIE_MSG(name, op) \ @@ -33,9 +35,21 @@ struct aie_device { #define PSP_REG_BAR(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].bar_idx) #define PSP_REG_OFF(ndev, idx) ((ndev)->priv->psp_regs_off[(idx)].offset) =20 +#define SMU_REG_BAR(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].bar_idx) +#define SMU_REG_OFF(ndev, idx) ((ndev)->priv->smu_regs_off[(idx)].offset) + #define DEFINE_BAR_OFFSET(reg_name, bar, reg_addr) \ [reg_name] =3D {bar##_BAR_INDEX, (reg_addr) - bar##_BAR_BASE} =20 +enum smu_reg_idx { + SMU_CMD_REG =3D 0, + SMU_ARG_REG, + SMU_INTR_REG, + SMU_RESP_REG, + SMU_OUT_REG, + SMU_MAX_REGS /* Keep this at the end */ +}; + enum psp_reg_idx { PSP_CMD_REG =3D 0, PSP_ARG0_REG, @@ -54,6 +68,10 @@ struct aie_bar_off_pair { u32 offset; }; =20 +struct smu_config { + void __iomem *smu_regs[SMU_MAX_REGS]; +}; + struct psp_config { const void *fw_buf; u32 fw_size; @@ -76,4 +94,11 @@ int aie_psp_start(struct psp_device *psp); void aie_psp_stop(struct psp_device *psp); int aie_psp_waitmode_poll(struct psp_device *psp); =20 +/* aie_smu.c */ +struct smu_device *aiem_smu_create(struct drm_device *ddev, struct smu_con= fig *conf); +int aie_smu_init(struct smu_device *smu); +void aie_smu_fini(struct smu_device *smu); +int aie_smu_set_clocks(struct smu_device *smu, u32 *npuclk, u32 *hclk); +int aie_smu_set_dpm(struct smu_device *smu, u32 dpm_level); + #endif /* _AIE_H_ */ diff --git a/drivers/accel/amdxdna/aie2_pci.c b/drivers/accel/amdxdna/aie2_= pci.c index 0489e668cd73..164e188ba501 100644 --- a/drivers/accel/amdxdna/aie2_pci.c +++ b/drivers/accel/amdxdna/aie2_pci.c @@ -282,6 +282,12 @@ static struct xrs_action_ops aie2_xrs_actions =3D { .set_dft_dpm_level =3D aie2_xrs_set_dft_dpm_level, }; =20 +static void aie2_smu_fini(struct amdxdna_dev_hdl *ndev) +{ + ndev->priv->hw_ops.set_dpm(ndev, 0); + aie_smu_fini(ndev->aie.smu_hdl); +} + static void aie2_hw_stop(struct amdxdna_dev *xdna) { struct pci_dev *pdev =3D to_pci_dev(xdna->ddev.dev); @@ -344,7 +350,7 @@ static int aie2_hw_start(struct amdxdna_dev *xdna) goto disable_dev; } =20 - ret =3D aie2_smu_init(ndev); + ret =3D aie_smu_init(ndev->aie.smu_hdl); if (ret) { XDNA_ERR(xdna, "failed to init smu, ret %d", ret); goto free_channel; @@ -464,6 +470,7 @@ static int aie2_init(struct amdxdna_dev *xdna) struct init_config xrs_cfg =3D { 0 }; struct amdxdna_dev_hdl *ndev; struct psp_config psp_conf =3D { 0 }; + struct smu_config smu_conf; const struct firmware *fw; unsigned long bars =3D 0; char *fw_full_path; @@ -508,9 +515,10 @@ static int aie2_init(struct amdxdna_dev *xdna) =20 for (i =3D 0; i < PSP_MAX_REGS; i++) set_bit(PSP_REG_BAR(ndev, i), &bars); + for (i =3D 0; i < SMU_MAX_REGS; i++) + set_bit(SMU_REG_BAR(ndev, i), &bars); =20 set_bit(xdna->dev_info->sram_bar, &bars); - set_bit(xdna->dev_info->smu_bar, &bars); set_bit(xdna->dev_info->mbox_bar, &bars); =20 for (i =3D 0; i < PCI_NUM_RESOURCES; i++) { @@ -525,7 +533,6 @@ static int aie2_init(struct amdxdna_dev *xdna) } =20 ndev->sram_base =3D tbl[xdna->dev_info->sram_bar]; - ndev->smu_base =3D tbl[xdna->dev_info->smu_bar]; ndev->mbox_base =3D tbl[xdna->dev_info->mbox_bar]; =20 ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); @@ -559,6 +566,15 @@ static int aie2_init(struct amdxdna_dev *xdna) ret =3D -ENOMEM; goto release_fw; } + + for (i =3D 0; i < SMU_MAX_REGS; i++) + smu_conf.smu_regs[i] =3D tbl[SMU_REG_BAR(ndev, i)] + SMU_REG_OFF(ndev, i= ); + ndev->aie.smu_hdl =3D aiem_smu_create(&xdna->ddev, &smu_conf); + if (!ndev->aie.smu_hdl) { + XDNA_ERR(xdna, "failed to create smu"); + ret =3D -ENOMEM; + goto release_fw; + } xdna->dev_handle =3D ndev; =20 ret =3D aie2_hw_start(xdna); diff --git a/drivers/accel/amdxdna/aie2_pci.h b/drivers/accel/amdxdna/aie2_= pci.h index 4f036b9fa096..7c308672b5fe 100644 --- a/drivers/accel/amdxdna/aie2_pci.h +++ b/drivers/accel/amdxdna/aie2_pci.h @@ -25,11 +25,6 @@ =20 #define SRAM_REG_OFF(ndev, idx) ((ndev)->priv->sram_offs[(idx)].offset) =20 -#define SMU_REG(ndev, idx) \ -({ \ - typeof(ndev) _ndev =3D ndev; \ - ((_ndev)->smu_base + (_ndev)->priv->smu_regs_off[(idx)].offset); \ -}) #define SRAM_GET_ADDR(ndev, idx) \ ({ \ typeof(ndev) _ndev =3D ndev; \ @@ -71,15 +66,6 @@ }) #endif =20 -enum aie2_smu_reg_idx { - SMU_CMD_REG =3D 0, - SMU_ARG_REG, - SMU_INTR_REG, - SMU_RESP_REG, - SMU_OUT_REG, - SMU_MAX_REGS /* Keep this at the end */ -}; - enum aie2_sram_reg_idx { MBOX_CHANN_OFF =3D 0, FW_ALIVE_OFF, @@ -183,7 +169,6 @@ struct amdxdna_dev_hdl { struct aie_device aie; const struct amdxdna_dev_priv *priv; void __iomem *sram_base; - void __iomem *smu_base; void __iomem *mbox_base; =20 u32 total_col; @@ -258,11 +243,6 @@ extern const struct dpm_clk_freq npu4_dpm_clk_table[]; extern const struct rt_config npu1_default_rt_cfg[]; extern const struct rt_config npu4_default_rt_cfg[]; extern const struct amdxdna_fw_feature_tbl npu4_fw_feature_table[]; - -/* aie2_smu.c */ -int aie2_smu_init(struct amdxdna_dev_hdl *ndev); -void aie2_smu_fini(struct amdxdna_dev_hdl *ndev); -int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level); =20 /* aie2_pm.c */ diff --git a/drivers/accel/amdxdna/aie2_smu.c b/drivers/accel/amdxdna/aie2_= smu.c deleted file mode 100644 index 1b966bbef2e5..000000000000 --- a/drivers/accel/amdxdna/aie2_smu.c +++ /dev/null @@ -1,156 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022-2024, Advanced Micro Devices, Inc. - */ - -#include -#include -#include -#include -#include - -#include "aie2_pci.h" -#include "amdxdna_pci_drv.h" - -#define SMU_RESULT_OK 1 - -/* SMU commands */ -#define AIE2_SMU_POWER_ON 0x3 -#define AIE2_SMU_POWER_OFF 0x4 -#define AIE2_SMU_SET_MPNPUCLK_FREQ 0x5 -#define AIE2_SMU_SET_HCLK_FREQ 0x6 -#define AIE2_SMU_SET_SOFT_DPMLEVEL 0x7 -#define AIE2_SMU_SET_HARD_DPMLEVEL 0x8 - -#define NPU4_DPM_TOPS(ndev, dpm_level) \ -({ \ - typeof(ndev) _ndev =3D ndev; \ - (4096 * (_ndev)->total_col * \ - (_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \ -}) - -static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd, - u32 reg_arg, u32 *out) -{ - u32 resp; - int ret; - - writel(0, SMU_REG(ndev, SMU_RESP_REG)); - writel(reg_arg, SMU_REG(ndev, SMU_ARG_REG)); - writel(reg_cmd, SMU_REG(ndev, SMU_CMD_REG)); - - /* Clear and set SMU_INTR_REG to kick off */ - writel(0, SMU_REG(ndev, SMU_INTR_REG)); - writel(1, SMU_REG(ndev, SMU_INTR_REG)); - - ret =3D readx_poll_timeout(readl, SMU_REG(ndev, SMU_RESP_REG), resp, - resp, AIE_INTERVAL, AIE_TIMEOUT); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "smu cmd %d timed out", reg_cmd); - return ret; - } - - if (out) - *out =3D readl(SMU_REG(ndev, SMU_OUT_REG)); - - if (resp !=3D SMU_RESULT_OK) { - XDNA_ERR(ndev->aie.xdna, "smu cmd %d failed, 0x%x", reg_cmd, resp); - return -EINVAL; - } - - return 0; -} - -int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) -{ - u32 freq; - int ret; - - ret =3D aie2_smu_exec(ndev, AIE2_SMU_SET_MPNPUCLK_FREQ, - ndev->priv->dpm_clk_tbl[dpm_level].npuclk, &freq); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "Set npu clock to %d failed, ret %d\n", - ndev->priv->dpm_clk_tbl[dpm_level].npuclk, ret); - return ret; - } - ndev->npuclk_freq =3D freq; - - ret =3D aie2_smu_exec(ndev, AIE2_SMU_SET_HCLK_FREQ, - ndev->priv->dpm_clk_tbl[dpm_level].hclk, &freq); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "Set h clock to %d failed, ret %d\n", - ndev->priv->dpm_clk_tbl[dpm_level].hclk, ret); - return ret; - } - - ndev->hclk_freq =3D freq; - ndev->max_tops =3D 2 * ndev->total_col; - ndev->curr_tops =3D ndev->max_tops * freq / 1028; - - XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", - ndev->npuclk_freq, ndev->hclk_freq); - - return 0; -} - -int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) -{ - int ret; - - ret =3D aie2_smu_exec(ndev, AIE2_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "Set hard dpm level %d failed, ret %d ", - dpm_level, ret); - return ret; - } - - ret =3D aie2_smu_exec(ndev, AIE2_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "Set soft dpm level %d failed, ret %d", - dpm_level, ret); - return ret; - } - - ndev->npuclk_freq =3D ndev->priv->dpm_clk_tbl[dpm_level].npuclk; - ndev->hclk_freq =3D ndev->priv->dpm_clk_tbl[dpm_level].hclk; - ndev->max_tops =3D NPU4_DPM_TOPS(ndev, ndev->max_dpm_level); - ndev->curr_tops =3D NPU4_DPM_TOPS(ndev, dpm_level); - - XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", - ndev->npuclk_freq, ndev->hclk_freq); - - return 0; -} - -int aie2_smu_init(struct amdxdna_dev_hdl *ndev) -{ - int ret; - - /* - * Failing to set power off indicates an unrecoverable hardware or - * firmware error. - */ - ret =3D aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "Access power failed, ret %d", ret); - return ret; - } - - ret =3D aie2_smu_exec(ndev, AIE2_SMU_POWER_ON, 0, NULL); - if (ret) { - XDNA_ERR(ndev->aie.xdna, "Power on failed, ret %d", ret); - return ret; - } - - return 0; -} - -void aie2_smu_fini(struct amdxdna_dev_hdl *ndev) -{ - int ret; - - ndev->priv->hw_ops.set_dpm(ndev, 0); - ret =3D aie2_smu_exec(ndev, AIE2_SMU_POWER_OFF, 0, NULL); - if (ret) - XDNA_ERR(ndev->aie.xdna, "Power off failed, ret %d", ret); -} diff --git a/drivers/accel/amdxdna/aie_smu.c b/drivers/accel/amdxdna/aie_sm= u.c new file mode 100644 index 000000000000..62aea550aabc --- /dev/null +++ b/drivers/accel/amdxdna/aie_smu.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026, Advanced Micro Devices, Inc. + */ + +#include "drm/amdxdna_accel.h" +#include +#include +#include +#include +#include + +#include "aie.h" + +#define SMU_RESULT_OK 1 + +/* SMU commands */ +#define AIE_SMU_POWER_ON 0x3 +#define AIE_SMU_POWER_OFF 0x4 +#define AIE_SMU_SET_MPNPUCLK_FREQ 0x5 +#define AIE_SMU_SET_HCLK_FREQ 0x6 +#define AIE_SMU_SET_SOFT_DPMLEVEL 0x7 +#define AIE_SMU_SET_HARD_DPMLEVEL 0x8 + +#define SMU_REG(s, reg) ((s)->smu_regs[reg]) + +struct smu_device { + struct drm_device *ddev; + struct smu_config conf; + void __iomem *smu_regs[SMU_MAX_REGS]; +}; + +static int aie_smu_exec(struct smu_device *smu, u32 reg_cmd, u32 reg_arg, = u32 *out) +{ + u32 resp; + int ret; + + writel(0, SMU_REG(smu, SMU_RESP_REG)); + writel(reg_arg, SMU_REG(smu, SMU_ARG_REG)); + writel(reg_cmd, SMU_REG(smu, SMU_CMD_REG)); + + /* Clear and set SMU_INTR_REG to kick off */ + writel(0, SMU_REG(smu, SMU_INTR_REG)); + writel(1, SMU_REG(smu, SMU_INTR_REG)); + + ret =3D readx_poll_timeout(readl, SMU_REG(smu, SMU_RESP_REG), resp, + resp, AIE_INTERVAL, AIE_TIMEOUT); + if (ret) { + drm_err(smu->ddev, "smu cmd %d timed out", reg_cmd); + return ret; + } + + if (out) + *out =3D readl(SMU_REG(smu, SMU_OUT_REG)); + + if (resp !=3D SMU_RESULT_OK) { + drm_err(smu->ddev, "smu cmd %d failed, 0x%x", reg_cmd, resp); + return -EINVAL; + } + + return 0; +} + +int aie_smu_init(struct smu_device *smu) +{ + int ret; + + /* + * Failing to set power off indicates an unrecoverable hardware or + * firmware error. + */ + ret =3D aie_smu_exec(smu, AIE_SMU_POWER_OFF, 0, NULL); + if (ret) { + drm_err(smu->ddev, "Access power failed, ret %d", ret); + return ret; + } + + ret =3D aie_smu_exec(smu, AIE_SMU_POWER_ON, 0, NULL); + if (ret) { + drm_err(smu->ddev, "Power on failed, ret %d", ret); + return ret; + } + + return 0; +} + +void aie_smu_fini(struct smu_device *smu) +{ + int ret; + + ret =3D aie_smu_exec(smu, AIE_SMU_POWER_OFF, 0, NULL); + if (ret) + drm_err(smu->ddev, "Power off failed, ret %d", ret); +} + +int aie_smu_set_clocks(struct smu_device *smu, u32 *npuclk, u32 *hclk) +{ + int ret; + + if (npuclk) { + ret =3D aie_smu_exec(smu, AIE_SMU_SET_MPNPUCLK_FREQ, *npuclk, npuclk); + if (ret) { + drm_err(smu->ddev, "Set mpnpu clock to %d failed, ret %d", *npuclk, ret= ); + return ret; + } + } + + if (hclk) { + ret =3D aie_smu_exec(smu, AIE_SMU_SET_HCLK_FREQ, *hclk, hclk); + if (ret) { + drm_err(smu->ddev, "Set hclock to %d failed, ret %d", + *hclk, ret); + return ret; + } + } + + return 0; +} + +int aie_smu_set_dpm(struct smu_device *smu, u32 dpm_level) +{ + int ret; + + ret =3D aie_smu_exec(smu, AIE_SMU_SET_HARD_DPMLEVEL, dpm_level, NULL); + if (ret) { + drm_err(smu->ddev, "Set hard dpm level %d failed, ret %d", + dpm_level, ret); + return ret; + } + + ret =3D aie_smu_exec(smu, AIE_SMU_SET_SOFT_DPMLEVEL, dpm_level, NULL); + if (ret) { + drm_err(smu->ddev, "Set soft dpm level %d failed, ret %d", + dpm_level, ret); + return ret; + } + + return 0; +} + +struct smu_device *aiem_smu_create(struct drm_device *ddev, struct smu_con= fig *conf) +{ + struct smu_device *smu; + + smu =3D drmm_kzalloc(ddev, sizeof(*smu), GFP_KERNEL); + if (!smu) + return NULL; + + smu->ddev =3D ddev; + memcpy(smu->smu_regs, conf->smu_regs, sizeof(smu->smu_regs)); + + return smu; +} diff --git a/drivers/accel/amdxdna/npu1_regs.c b/drivers/accel/amdxdna/npu1= _regs.c index 2ea7568a2e99..a83e44f378ad 100644 --- a/drivers/accel/amdxdna/npu1_regs.c +++ b/drivers/accel/amdxdna/npu1_regs.c @@ -71,6 +71,27 @@ static const struct amdxdna_fw_feature_tbl npu1_fw_featu= re_table[] =3D { { 0 } }; =20 +static int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) +{ + u32 npuclk, hclk; + int ret; + + npuclk =3D ndev->priv->dpm_clk_tbl[dpm_level].npuclk; + hclk =3D ndev->priv->dpm_clk_tbl[dpm_level].hclk; + ret =3D aie_smu_set_clocks(ndev->aie.smu_hdl, &npuclk, &hclk); + if (ret) + return ret; + + ndev->npuclk_freq =3D npuclk; + ndev->hclk_freq =3D hclk; + ndev->max_tops =3D 2 * ndev->total_col; + ndev->curr_tops =3D ndev->max_tops * hclk / 1028; + + XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", + ndev->npuclk_freq, ndev->hclk_freq); + return 0; +} + static const struct amdxdna_dev_priv npu1_dev_priv =3D { .fw_path =3D "amdnpu/1502_00/", .rt_config =3D npu1_default_rt_cfg, diff --git a/drivers/accel/amdxdna/npu4_regs.c b/drivers/accel/amdxdna/npu4= _regs.c index 9689c56c83be..5d68171f4ec2 100644 --- a/drivers/accel/amdxdna/npu4_regs.c +++ b/drivers/accel/amdxdna/npu4_regs.c @@ -63,6 +63,13 @@ #define NPU4_SMU_BAR_BASE MMNPU_APERTURE4_BASE #define NPU4_SRAM_BAR_BASE MMNPU_APERTURE1_BASE =20 +#define NPU4_DPM_TOPS(ndev, dpm_level) \ +({ \ + typeof(ndev) _ndev =3D ndev; \ + (4096 * (_ndev)->total_col * \ + (_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \ +}) + const struct rt_config npu4_default_rt_cfg[] =3D { { 5, 1, AIE2_RT_CFG_INIT }, /* PDI APP LOAD MODE */ { 10, 1, AIE2_RT_CFG_INIT }, /* DEBUG BUF */ @@ -98,6 +105,25 @@ const struct amdxdna_fw_feature_tbl npu4_fw_feature_tab= le[] =3D { { 0 } }; =20 +int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level) +{ + int ret; + + ret =3D aie_smu_set_dpm(ndev->aie.smu_hdl, dpm_level); + if (ret) + return ret; + + ndev->npuclk_freq =3D ndev->priv->dpm_clk_tbl[dpm_level].npuclk; + ndev->hclk_freq =3D ndev->priv->dpm_clk_tbl[dpm_level].hclk; + ndev->max_tops =3D NPU4_DPM_TOPS(ndev, ndev->max_dpm_level); + ndev->curr_tops =3D NPU4_DPM_TOPS(ndev, dpm_level); + + XDNA_DBG(ndev->aie.xdna, "MP-NPU clock %d, H clock %d\n", + ndev->npuclk_freq, ndev->hclk_freq); + + return 0; +} + static const struct amdxdna_dev_priv npu4_dev_priv =3D { .fw_path =3D "amdnpu/17f0_10/", .rt_config =3D npu4_default_rt_cfg, --=20 2.34.1