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[176.247.30.22]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43cf21e29b1sm18796564f8f.8.2026.03.30.09.19.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2026 09:19:16 -0700 (PDT) From: Francesco Lavra To: Linus Walleij , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] pinctrl: mcp23s08: Disable all pin interrupts during probe Date: Mon, 30 Mar 2026 18:19:14 +0200 Message-Id: <20260330161914.1071118-1-flavra@baylibre.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4436; i=flavra@baylibre.com; h=from:subject; bh=hgGtkNEYd3/BeM5nsJ4Pr/kLRh68Go04WXIspuv2d8I=; b=owEB7QES/pANAwAKAe3xO3POlDZfAcsmYgBpyqJ6k+fhPfJ2tZeDtag7fp7JU0CzQvwwvHbQk OPfzSXzcXaJAbMEAAEKAB0WIQSGV4VPlTvcox7DFObt8TtzzpQ2XwUCacqiegAKCRDt8TtzzpQ2 X3o6C/0fIDZXhIG0IXYz4VynyCvWA9w+4hUrLt2WOAd6jICfZFuO7mBkE95B7qAJj073SX3NFbi dulU/PbCisLROc3qq2myaRHisrc2hodJOyA5w0KeddwniOWg0ppBQRLSwHCPK1U+PpWfH5mgX5w 06+QgX8xP7bR8tCTlKYMk9DhO6nDKOgJGdiBzERnuhsOYfwDk1bw29jCp6tA+1M09iwynWvd8FM ZSZGJZVvwE2aSRsnJkxyMgkW1vl71lrKOJnBiF6aNd8Y6jpCfrdlrfn9lO4feJGo4Ix13gSrgkg JQR86hQqm0Q6WJcCADtNbuntVFg5DgMhBHsCJpmy/ChbA35a5NN3nVCK+7w6sArtrFHzhMkMWLA 3/zxTtP4SUbpZDqfLi0Rd8GUQEeqVdBIGFrqtZxeENeoSEiun0UczI80YAlRaZciZP3jjEJLXlJ z38n0KtDilNUo6bEjqXAoQVVbIK7ZfwGZYDa1JpNLEwneWXknAnoyqbmsLvdT2Yv1vd2E= X-Developer-Key: i=flavra@baylibre.com; a=openpgp; fpr=8657854F953BDCA31EC314E6EDF13B73CE94365F Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A chip being probed may have the interrupt-on-change feature enabled on some of its pins, for example after a reboot. This can cause the chip to generate interrupts for pins that don't have a registered nested handler, which leads to a kernel crash such as below: [ 7.928897] Unable to handle kernel read from unreadable memory at virtu= al address 00000000000000ac [ 7.932314] Mem abort info: [ 7.935081] ESR =3D 0x0000000096000004 [ 7.938808] EC =3D 0x25: DABT (current EL), IL =3D 32 bits [ 7.944094] SET =3D 0, FnV =3D 0 [ 7.947127] EA =3D 0, S1PTW =3D 0 [ 7.950247] FSC =3D 0x04: level 0 translation fault [ 7.955101] Data abort info: [ 7.957961] ISV =3D 0, ISS =3D 0x00000004, ISS2 =3D 0x00000000 [ 7.963421] CM =3D 0, WnR =3D 0, TnD =3D 0, TagAccess =3D 0 [ 7.968447] GCS =3D 0, Overlay =3D 0, DirtyBit =3D 0, Xs =3D 0 [ 7.973734] user pgtable: 4k pages, 48-bit VAs, pgdp=3D00000000089b7000 [ 7.980148] [00000000000000ac] pgd=3D0000000000000000, p4d=3D00000000000= 00000 [ 7.986913] Internal error: Oops: 0000000096000004 [#1] SMP [ 7.992545] Modules linked in: [ 8.073678] CPU: 0 UID: 0 PID: 81 Comm: irq/18-4-0025 Not tainted 7.0.0-= rc6-gd2b5a1f931c8-dirty #199 [ 8.073689] Hardware name: Khadas VIM3 (DT) [ 8.073692] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE= =3D--) [ 8.094639] pc : _raw_spin_lock_irq+0x40/0x80 [ 8.098970] lr : handle_nested_irq+0x2c/0x168 [ 8.098979] sp : ffff800082b2bd20 [ 8.106599] x29: ffff800082b2bd20 x28: ffff800080107920 x27: ffff8000801= 04d88 [ 8.106611] x26: ffff000003298080 x25: 0000000000000001 x24: 00000000000= 0ff00 [ 8.113707] x23: 0000000000000001 x22: 0000000000000000 x21: 00000000000= 0000e [ 8.120850] x20: 0000000000000000 x19: 00000000000000ac x18: 00000000000= 00000 [ 8.135046] x17: 0000000000000000 x16: 0000000000000000 x15: 00000000000= 00000 [ 8.135062] x14: ffff800081567ea8 x13: ffffffffffffffff x12: 00000000000= 00000 [ 8.135070] x11: 00000000000000c0 x10: 0000000000000b60 x9 : ffff8000801= 09e0c [ 8.135078] x8 : 1fffe0000069dbc1 x7 : 0000000000000001 x6 : ffff0000034= ede00 [ 8.135086] x5 : 0000000000000000 x4 : ffff0000034ede08 x3 : 00000000000= 00001 [ 8.163460] x2 : 0000000000000000 x1 : 0000000000000001 x0 : 00000000000= 000ac [ 8.170560] Call trace: [ 8.180094] _raw_spin_lock_irq+0x40/0x80 (P) [ 8.184443] mcp23s08_irq+0x248/0x358 [ 8.184462] irq_thread_fn+0x34/0xb8 [ 8.184470] irq_thread+0x1a4/0x310 [ 8.195093] kthread+0x13c/0x150 [ 8.198309] ret_from_fork+0x10/0x20 [ 8.201850] Code: d65f03c0 d2800002 52800023 f9800011 (885ffc01) [ 8.207931] ---[ end trace 0000000000000000 ]--- This issue has always been present, but has been latent until commit "f9f4fda15e72" ("pinctrl: mcp23s08: init reg_defaults from HW at probe and switch cache type"), which correctly removed reg_defaults from the regmap and as a side effect changed the behavior of the interrupt handler so that the real value of the MCP_GPINTEN register is now being read from the chip instead of using a bogus 0 default value; a non-zero value for this register can trigger the invocation of a nested handler which may not exist (yet). Fix this issue by disabling all pin interrupts during initialization. Fixes: "f9f4fda15e72" ("pinctrl: mcp23s08: init reg_defaults from HW at pro= be and switch cache type") Signed-off-by: Francesco Lavra --- drivers/pinctrl/pinctrl-mcp23s08.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-m= cp23s08.c index 586f2f67c617..b89b3169e8be 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -664,6 +664,15 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct de= vice *dev, if (mcp->irq && mcp->irq_controller) { struct gpio_irq_chip *girq =3D &mcp->chip.irq; =20 + /* + * Disable all pin interrupts, to prevent the interrupt handler from + * calling nested handlers for any currently-enabled interrupts that + * do not (yet) have an actual handler. + */ + ret =3D mcp_write(mcp, MCP_GPINTEN, 0); + if (ret < 0) + return dev_err_probe(dev, ret, "can't disable interrupts\n"); + gpio_irq_chip_set_chip(girq, &mcp23s08_irq_chip); /* This will let us handle the parent IRQ in the driver */ girq->parent_handler =3D NULL; --=20 2.39.5