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Mon, 30 Mar 2026 07:46:22 -0700 From: Akhil R To: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Jonathan Hunter" , Laxman Dewangan , Philipp Zabel , , , , CC: Akhil R Subject: [PATCH v5 08/10] dmaengine: tegra: Use iommu-map for stream ID Date: Mon, 30 Mar 2026 20:14:54 +0530 Message-ID: <20260330144456.13551-9-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com> References: <20260330144456.13551-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3D:EE_|CH3PR12MB9023:EE_ X-MS-Office365-Filtering-Correlation-Id: 459522b5-d1cc-4d65-e93b-08de8e6b2964 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|1800799024|36860700016|376014|921020|22082099003|18002099003|56012099003; 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charset="utf-8" Use 'iommu-map', when provided, to get the stream ID to be programmed for each channel. Iterate over the channels registered and configure each channel device separately using of_dma_configure_id() to allow it to use a separate IOMMU domain for the transfer. However, do this in a second loop since the first loop populates the DMA device channels list and async_device_register() registers the channels. Both are prerequisites for using the channel device in the next loop. Channels will continue to use the same global stream ID if the 'iommu-map' property is not present in the device tree. Signed-off-by: Akhil R --- drivers/dma/tegra186-gpc-dma.c | 57 ++++++++++++++++++++++++++++------ 1 file changed, 48 insertions(+), 9 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index 9bea2ffb3b9e..64743d852dda 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1380,9 +1381,13 @@ static int tegra_dma_program_sid(struct tegra_dma_ch= annel *tdc, int stream_id) static int tegra_dma_probe(struct platform_device *pdev) { const struct tegra_dma_chip_data *cdata =3D NULL; + struct tegra_dma_channel *tdc; + struct tegra_dma *tdma; + struct dma_chan *chan; + struct device *chdev; + bool use_iommu_map =3D false; unsigned int i; u32 stream_id; - struct tegra_dma *tdma; int ret; =20 cdata =3D of_device_get_match_data(&pdev->dev); @@ -1410,9 +1415,12 @@ static int tegra_dma_probe(struct platform_device *p= dev) =20 tdma->dma_dev.dev =3D &pdev->dev; =20 - if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { - dev_err(&pdev->dev, "Missing iommu stream-id\n"); - return -EINVAL; + use_iommu_map =3D of_property_present(pdev->dev.of_node, "iommu-map"); + if (!use_iommu_map) { + if (!tegra_dev_iommu_get_stream_id(&pdev->dev, &stream_id)) { + dev_err(&pdev->dev, "Missing iommu stream-id\n"); + return -EINVAL; + } } =20 ret =3D device_property_read_u32(&pdev->dev, "dma-channel-mask", @@ -1424,9 +1432,10 @@ static int tegra_dma_probe(struct platform_device *p= dev) tdma->chan_mask =3D TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; } =20 + /* Initialize vchan for each channel and populate the channels list */ INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i =3D 0; i < cdata->nr_channels; i++) { - struct tegra_dma_channel *tdc =3D &tdma->channels[i]; + tdc =3D &tdma->channels[i]; =20 /* Check for channel mask */ if (!(tdma->chan_mask & BIT(i))) @@ -1446,10 +1455,6 @@ static int tegra_dma_probe(struct platform_device *p= dev) =20 vchan_init(&tdc->vc, &tdma->dma_dev); tdc->vc.desc_free =3D tegra_dma_desc_free; - - /* program stream-id for this channel */ - tegra_dma_program_sid(tdc, stream_id); - tdc->stream_id =3D stream_id; } =20 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits)); @@ -1483,6 +1488,7 @@ static int tegra_dma_probe(struct platform_device *pd= ev) tdma->dma_dev.device_synchronize =3D tegra_dma_chan_synchronize; tdma->dma_dev.residue_granularity =3D DMA_RESIDUE_GRANULARITY_BURST; =20 + /* Register the DMA device and the channels */ ret =3D dmaenginem_async_device_register(&tdma->dma_dev); if (ret < 0) { dev_err_probe(&pdev->dev, ret, @@ -1490,6 +1496,39 @@ static int tegra_dma_probe(struct platform_device *p= dev) return ret; } =20 + /* + * Configure stream ID for each channel from the channels registered + * above. This is done in a separate iteration to ensure that only + * the channels available and registered for the DMA device are used. + */ + list_for_each_entry(chan, &tdma->dma_dev.channels, device_node) { + chdev =3D &chan->dev->device; + tdc =3D to_tegra_dma_chan(chan); + + if (use_iommu_map) { + chdev->bus =3D pdev->dev.bus; + dma_coerce_mask_and_coherent(chdev, DMA_BIT_MASK(cdata->addr_bits)); + + ret =3D of_dma_configure_id(chdev, pdev->dev.of_node, + true, &tdc->id); + if (ret) + return dev_err_probe(chdev, ret, + "Failed to configure IOMMU for channel %d", tdc->id); + + if (!tegra_dev_iommu_get_stream_id(chdev, &stream_id)) { + dev_err(chdev, "Failed to get stream ID for channel %d\n", + tdc->id); + return -EINVAL; + } + + chan->dev->chan_dma_dev =3D true; + } + + /* program stream-id for this channel */ + tegra_dma_program_sid(tdc, stream_id); + tdc->stream_id =3D stream_id; + } + ret =3D devm_of_dma_controller_register(&pdev->dev, pdev->dev.of_node, tegra_dma_of_xlate, tdma); if (ret < 0) { --=20 2.50.1