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Mon, 30 Mar 2026 07:45:53 -0700 From: Akhil R To: Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , "Jonathan Hunter" , Laxman Dewangan , Philipp Zabel , , , , CC: Akhil R , Frank Li Subject: [PATCH v5 05/10] dmaengine: tegra: Use struct for register offsets Date: Mon, 30 Mar 2026 20:14:51 +0530 Message-ID: <20260330144456.13551-6-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260330144456.13551-1-akhilrajeev@nvidia.com> References: <20260330144456.13551-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE38:EE_|SJ1PR12MB6049:EE_ X-MS-Office365-Filtering-Correlation-Id: e2b8a405-84cb-45e6-8e7d-08de8e6b1aed X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|1800799024|82310400026|56012099003|18002099003|22082099003|921020; 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charset="utf-8" Repurpose the struct tegra_dma_channel_regs to define offsets for all the channel registers. Previously, the struct only held the register values for each transfer and was wrapped within tegra_dma_sg_req. Move the values directly into tegra_dma_sg_req and use channel_regs for storing the register offsets. Update all register reads/writes to use the struct channel_regs. This prepares for the register offset change in Tegra264. Signed-off-by: Akhil R Reviewed-by: Frank Li --- drivers/dma/tegra186-gpc-dma.c | 282 +++++++++++++++++---------------- 1 file changed, 142 insertions(+), 140 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index a0522a992ebc..b213c4ae07d2 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -22,7 +22,6 @@ #include "virt-dma.h" =20 /* CSR register */ -#define TEGRA_GPCDMA_CHAN_CSR 0x00 #define TEGRA_GPCDMA_CSR_ENB BIT(31) #define TEGRA_GPCDMA_CSR_IE_EOC BIT(30) #define TEGRA_GPCDMA_CSR_ONCE BIT(27) @@ -58,7 +57,6 @@ #define TEGRA_GPCDMA_CSR_WEIGHT GENMASK(13, 10) =20 /* STATUS register */ -#define TEGRA_GPCDMA_CHAN_STATUS 0x004 #define TEGRA_GPCDMA_STATUS_BUSY BIT(31) #define TEGRA_GPCDMA_STATUS_ISE_EOC BIT(30) #define TEGRA_GPCDMA_STATUS_PING_PONG BIT(28) @@ -70,22 +68,13 @@ #define TEGRA_GPCDMA_STATUS_IRQ_STA BIT(21) #define TEGRA_GPCDMA_STATUS_IRQ_TRIG_STA BIT(20) =20 -#define TEGRA_GPCDMA_CHAN_CSRE 0x008 #define TEGRA_GPCDMA_CHAN_CSRE_PAUSE BIT(31) =20 -/* Source address */ -#define TEGRA_GPCDMA_CHAN_SRC_PTR 0x00C - -/* Destination address */ -#define TEGRA_GPCDMA_CHAN_DST_PTR 0x010 - /* High address pointer */ -#define TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR 0x014 #define TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR GENMASK(7, 0) #define TEGRA_GPCDMA_HIGH_ADDR_DST_PTR GENMASK(23, 16) =20 /* MC sequence register */ -#define TEGRA_GPCDMA_CHAN_MCSEQ 0x18 #define TEGRA_GPCDMA_MCSEQ_DATA_SWAP BIT(31) #define TEGRA_GPCDMA_MCSEQ_REQ_COUNT GENMASK(30, 25) #define TEGRA_GPCDMA_MCSEQ_BURST GENMASK(24, 23) @@ -101,7 +90,6 @@ #define TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK GENMASK(6, 0) =20 /* MMIO sequence register */ -#define TEGRA_GPCDMA_CHAN_MMIOSEQ 0x01c #define TEGRA_GPCDMA_MMIOSEQ_DBL_BUF BIT(31) #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH GENMASK(30, 28) #define TEGRA_GPCDMA_MMIOSEQ_BUS_WIDTH_8 \ @@ -120,17 +108,7 @@ #define TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD GENMASK(18, 16) #define TEGRA_GPCDMA_MMIOSEQ_MMIO_PROT GENMASK(8, 7) =20 -/* Channel WCOUNT */ -#define TEGRA_GPCDMA_CHAN_WCOUNT 0x20 - -/* Transfer count */ -#define TEGRA_GPCDMA_CHAN_XFER_COUNT 0x24 - -/* DMA byte count status */ -#define TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS 0x28 - /* Error Status Register */ -#define TEGRA_GPCDMA_CHAN_ERR_STATUS 0x30 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_SHIFT 8 #define TEGRA_GPCDMA_CHAN_ERR_TYPE_MASK 0xF #define TEGRA_GPCDMA_CHAN_ERR_TYPE(err) ( \ @@ -143,16 +121,6 @@ #define TEGRA_DMA_MC_SLAVE_ERR 0xB #define TEGRA_DMA_MMIO_SLAVE_ERR 0xA =20 -/* Fixed Pattern */ -#define TEGRA_GPCDMA_CHAN_FIXED_PATTERN 0x34 - -#define TEGRA_GPCDMA_CHAN_TZ 0x38 -#define TEGRA_GPCDMA_CHAN_TZ_MMIO_PROT_1 BIT(0) -#define TEGRA_GPCDMA_CHAN_TZ_MC_PROT_1 BIT(1) - -#define TEGRA_GPCDMA_CHAN_SPARE 0x3c -#define TEGRA_GPCDMA_CHAN_SPARE_EN_LEGACY_FC BIT(16) - /* * If any burst is in flight and DMA paused then this is the time to compl= ete * on-flight burst and update DMA status register. @@ -181,18 +149,24 @@ struct tegra_dma_chip_data { unsigned int nr_channels; unsigned int channel_reg_size; unsigned int max_dma_count; + const struct tegra_dma_channel_regs *channel_regs; int (*terminate)(struct tegra_dma_channel *tdc); }; =20 /* DMA channel registers */ struct tegra_dma_channel_regs { u32 csr; - u32 src_ptr; - u32 dst_ptr; - u32 high_addr_ptr; + u32 status; + u32 csre; + u32 src; + u32 dst; + u32 high_addr; u32 mc_seq; u32 mmio_seq; u32 wcount; + u32 wxfer; + u32 wstatus; + u32 err_status; u32 fixed_pattern; }; =20 @@ -205,7 +179,14 @@ struct tegra_dma_channel_regs { */ struct tegra_dma_sg_req { unsigned int len; - struct tegra_dma_channel_regs ch_regs; + u32 csr; + u32 src; + u32 dst; + u32 high_addr; + u32 mc_seq; + u32 mmio_seq; + u32 wcount; + u32 fixed_pattern; }; =20 /* @@ -228,19 +209,20 @@ struct tegra_dma_desc { * tegra_dma_channel: Channel specific information */ struct tegra_dma_channel { - bool config_init; - char name[30]; - enum dma_transfer_direction sid_dir; - enum dma_status status; - int id; - int irq; - int slave_id; + const struct tegra_dma_channel_regs *regs; struct tegra_dma *tdma; struct virt_dma_chan vc; struct tegra_dma_desc *dma_desc; struct dma_slave_config dma_sconfig; + enum dma_transfer_direction sid_dir; + enum dma_status status; unsigned int stream_id; unsigned long chan_base_offset; + bool config_init; + char name[30]; + int id; + int irq; + int slave_id; }; =20 /* @@ -288,22 +270,22 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma= _channel *tdc) { dev_dbg(tdc2dev(tdc), "DMA Channel %d name %s register dump:\n", tdc->id, tdc->name); - dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x SRC %x DST %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_DST_PTR) - ); - dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x BSTA %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_WCOUNT), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT), - tdc_read(tdc, TEGRA_GPCDMA_CHAN_DMA_BYTE_STATUS) - ); + dev_dbg(tdc2dev(tdc), "CSR %x STA %x CSRE %x\n", + tdc_read(tdc, tdc->regs->csr), + tdc_read(tdc, tdc->regs->status), + tdc_read(tdc, tdc->regs->csre)); + dev_dbg(tdc2dev(tdc), "SRC %x DST %x HI ADDR %x\n", + tdc_read(tdc, tdc->regs->src), + tdc_read(tdc, tdc->regs->dst), + tdc_read(tdc, tdc->regs->high_addr)); + dev_dbg(tdc2dev(tdc), "MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\n", + tdc_read(tdc, tdc->regs->mc_seq), + tdc_read(tdc, tdc->regs->mmio_seq), + tdc_read(tdc, tdc->regs->wcount), + tdc_read(tdc, tdc->regs->wxfer), + tdc_read(tdc, tdc->regs->wstatus)); dev_dbg(tdc2dev(tdc), "DMA ERR_STA %x\n", - tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS)); + tdc_read(tdc, tdc->regs->err_status)); } =20 static int tegra_dma_sid_reserve(struct tegra_dma_channel *tdc, @@ -377,13 +359,13 @@ static int tegra_dma_pause(struct tegra_dma_channel *= tdc) int ret; u32 val; =20 - val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); + val =3D tdc_read(tdc, tdc->regs->csre); val |=3D TEGRA_GPCDMA_CHAN_CSRE_PAUSE; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + tdc_write(tdc, tdc->regs->csre, val); =20 /* Wait until busy bit is de-asserted */ ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + - tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, + tdc->chan_base_offset + tdc->regs->status, val, !(val & TEGRA_GPCDMA_STATUS_BUSY), TEGRA_GPCDMA_BURST_COMPLETE_TIME, @@ -419,9 +401,9 @@ static void tegra_dma_resume(struct tegra_dma_channel *= tdc) { u32 val; =20 - val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSRE); + val =3D tdc_read(tdc, tdc->regs->csre); val &=3D ~TEGRA_GPCDMA_CHAN_CSRE_PAUSE; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSRE, val); + tdc_write(tdc, tdc->regs->csre, val); =20 tdc->status =3D DMA_IN_PROGRESS; } @@ -456,27 +438,27 @@ static void tegra_dma_disable(struct tegra_dma_channe= l *tdc) { u32 csr, status; =20 - csr =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); + csr =3D tdc_read(tdc, tdc->regs->csr); =20 /* Disable interrupts */ csr &=3D ~TEGRA_GPCDMA_CSR_IE_EOC; =20 /* Disable DMA */ csr &=3D ~TEGRA_GPCDMA_CSR_ENB; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); + tdc_write(tdc, tdc->regs->csr, csr); =20 /* Clear interrupt status if it is there */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) { dev_dbg(tdc2dev(tdc), "%s():clearing interrupt\n", __func__); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, status); + tdc_write(tdc, tdc->regs->status, status); } } =20 static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc) { struct tegra_dma_desc *dma_desc =3D tdc->dma_desc; - struct tegra_dma_channel_regs *ch_regs; + struct tegra_dma_sg_req *sg_req; int ret; u32 val; =20 @@ -488,29 +470,29 @@ static void tegra_dma_configure_next_sg(struct tegra_= dma_channel *tdc) =20 /* Configure next transfer immediately after DMA is busy */ ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + - tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, + tdc->chan_base_offset + tdc->regs->status, val, (val & TEGRA_GPCDMA_STATUS_BUSY), 0, TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT); if (ret) return; =20 - ch_regs =3D &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; + sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); + tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); =20 /* Start DMA */ - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, - ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); + tdc_write(tdc, tdc->regs->csr, + sg_req->csr | TEGRA_GPCDMA_CSR_ENB); } =20 static void tegra_dma_start(struct tegra_dma_channel *tdc) { struct tegra_dma_desc *dma_desc =3D tdc->dma_desc; - struct tegra_dma_channel_regs *ch_regs; + struct tegra_dma_sg_req *sg_req; struct virt_dma_desc *vdesc; =20 if (!dma_desc) { @@ -526,21 +508,21 @@ static void tegra_dma_start(struct tegra_dma_channel = *tdc) tegra_dma_resume(tdc); } =20 - ch_regs =3D &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; + sg_req =3D &dma_desc->sg_req[dma_desc->sg_idx]; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, 0); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); + tdc_write(tdc, tdc->regs->wcount, sg_req->wcount); + tdc_write(tdc, tdc->regs->csr, 0); + tdc_write(tdc, tdc->regs->src, sg_req->src); + tdc_write(tdc, tdc->regs->dst, sg_req->dst); + tdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr); + tdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern); + tdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq); + tdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq); + tdc_write(tdc, tdc->regs->csr, sg_req->csr); =20 /* Start DMA */ - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, - ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); + tdc_write(tdc, tdc->regs->csr, + sg_req->csr | TEGRA_GPCDMA_CSR_ENB); } =20 static void tegra_dma_xfer_complete(struct tegra_dma_channel *tdc) @@ -601,19 +583,19 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_i= d) u32 status; =20 /* Check channel error status register */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS); + status =3D tdc_read(tdc, tdc->regs->err_status); if (status) { tegra_dma_chan_decode_error(tdc, status); tegra_dma_dump_chan_regs(tdc); - tdc_write(tdc, TEGRA_GPCDMA_CHAN_ERR_STATUS, 0xFFFFFFFF); + tdc_write(tdc, tdc->regs->err_status, 0xFFFFFFFF); } =20 spin_lock(&tdc->vc.lock); - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC)) goto irq_done; =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_STATUS, + tdc_write(tdc, tdc->regs->status, TEGRA_GPCDMA_STATUS_ISE_EOC); =20 if (!dma_desc) @@ -673,10 +655,10 @@ static int tegra_dma_stop_client(struct tegra_dma_cha= nnel *tdc) * to stop DMA engine from starting any more bursts for * the given client and wait for in flight bursts to complete */ - csr =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_CSR); + csr =3D tdc_read(tdc, tdc->regs->csr); csr &=3D ~(TEGRA_GPCDMA_CSR_REQ_SEL_MASK); csr |=3D TEGRA_GPCDMA_CSR_REQ_SEL_UNUSED; - tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, csr); + tdc_write(tdc, tdc->regs->csr, csr); =20 /* Wait for in flight data transfer to finish */ udelay(TEGRA_GPCDMA_BURST_COMPLETE_TIME); @@ -687,7 +669,7 @@ static int tegra_dma_stop_client(struct tegra_dma_chann= el *tdc) =20 ret =3D readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + tdc->chan_base_offset + - TEGRA_GPCDMA_CHAN_STATUS, + tdc->regs->status, status, !(status & (TEGRA_GPCDMA_STATUS_CHANNEL_TX | TEGRA_GPCDMA_STATUS_CHANNEL_RX)), @@ -739,14 +721,14 @@ static int tegra_dma_get_residual(struct tegra_dma_ch= annel *tdc) unsigned int bytes_xfer, residual; u32 wcount =3D 0, status; =20 - wcount =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_XFER_COUNT); + wcount =3D tdc_read(tdc, tdc->regs->wxfer); =20 /* * Set wcount =3D 0 if EOC bit is set. The transfer would have * already completed and the CHAN_XFER_COUNT could have updated * for the next transfer, specifically in case of cyclic transfers. */ - status =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_STATUS); + status =3D tdc_read(tdc, tdc->regs->status); if (status & TEGRA_GPCDMA_STATUS_ISE_EOC) wcount =3D 0; =20 @@ -893,7 +875,7 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr= _t dest, int value, /* Configure default priority weight for the channel */ csr |=3D FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -916,16 +898,16 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_ad= dr_t dest, int value, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].ch_regs.src_ptr =3D 0; - sg_req[0].ch_regs.dst_ptr =3D dest; - sg_req[0].ch_regs.high_addr_ptr =3D + sg_req[0].src =3D 0; + sg_req[0].dst =3D dest; + sg_req[0].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); - sg_req[0].ch_regs.fixed_pattern =3D value; + sg_req[0].fixed_pattern =3D value; /* Word count reg takes value as (N +1) words */ - sg_req[0].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[0].ch_regs.csr =3D csr; - sg_req[0].ch_regs.mmio_seq =3D 0; - sg_req[0].ch_regs.mc_seq =3D mc_seq; + sg_req[0].wcount =3D ((len - 4) >> 2); + sg_req[0].csr =3D csr; + sg_req[0].mmio_seq =3D 0; + sg_req[0].mc_seq =3D mc_seq; sg_req[0].len =3D len; =20 dma_desc->cyclic =3D false; @@ -961,7 +943,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr= _t dest, /* Configure default priority weight for the channel */ csr |=3D FIELD_PREP(TEGRA_GPCDMA_CSR_WEIGHT, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D (TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK) | (TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); @@ -985,17 +967,17 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_ad= dr_t dest, dma_desc->sg_count =3D 1; sg_req =3D dma_desc->sg_req; =20 - sg_req[0].ch_regs.src_ptr =3D src; - sg_req[0].ch_regs.dst_ptr =3D dest; - sg_req[0].ch_regs.high_addr_ptr =3D + sg_req[0].src =3D src; + sg_req[0].dst =3D dest; + sg_req[0].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32)); - sg_req[0].ch_regs.high_addr_ptr |=3D + sg_req[0].high_addr |=3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32)); /* Word count reg takes value as (N +1) words */ - sg_req[0].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[0].ch_regs.csr =3D csr; - sg_req[0].ch_regs.mmio_seq =3D 0; - sg_req[0].ch_regs.mc_seq =3D mc_seq; + sg_req[0].wcount =3D ((len - 4) >> 2); + sg_req[0].csr =3D csr; + sg_req[0].mmio_seq =3D 0; + sg_req[0].mc_seq =3D mc_seq; sg_req[0].len =3D len; =20 dma_desc->cyclic =3D false; @@ -1049,7 +1031,7 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct s= catterlist *sgl, if (flags & DMA_PREP_INTERRUPT) csr |=3D TEGRA_GPCDMA_CSR_IE_EOC; =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -1096,14 +1078,14 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, dma_desc->bytes_req +=3D len; =20 if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].ch_regs.src_ptr =3D mem; - sg_req[i].ch_regs.dst_ptr =3D apb_ptr; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D mem; + sg_req[i].dst =3D apb_ptr; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].ch_regs.src_ptr =3D apb_ptr; - sg_req[i].ch_regs.dst_ptr =3D mem; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D apb_ptr; + sg_req[i].dst =3D mem; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } =20 @@ -1111,10 +1093,10 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct= scatterlist *sgl, * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. */ - sg_req[i].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[i].ch_regs.csr =3D csr; - sg_req[i].ch_regs.mmio_seq =3D mmio_seq; - sg_req[i].ch_regs.mc_seq =3D mc_seq; + sg_req[i].wcount =3D ((len - 4) >> 2); + sg_req[i].csr =3D csr; + sg_req[i].mmio_seq =3D mmio_seq; + sg_req[i].mc_seq =3D mc_seq; sg_req[i].len =3D len; } =20 @@ -1186,7 +1168,7 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_ad= dr_t buf_addr, size_t buf_l =20 mmio_seq |=3D FIELD_PREP(TEGRA_GPCDMA_MMIOSEQ_WRAP_WORD, 1); =20 - mc_seq =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + mc_seq =3D tdc_read(tdc, tdc->regs->mc_seq); /* retain stream-id and clean rest */ mc_seq &=3D TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK; =20 @@ -1217,24 +1199,24 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_= addr_t buf_addr, size_t buf_l for (i =3D 0; i < period_count; i++) { mmio_seq |=3D get_burst_size(tdc, burst_size, slave_bw, len); if (direction =3D=3D DMA_MEM_TO_DEV) { - sg_req[i].ch_regs.src_ptr =3D mem; - sg_req[i].ch_regs.dst_ptr =3D apb_ptr; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D mem; + sg_req[i].dst =3D apb_ptr; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32)); } else if (direction =3D=3D DMA_DEV_TO_MEM) { - sg_req[i].ch_regs.src_ptr =3D apb_ptr; - sg_req[i].ch_regs.dst_ptr =3D mem; - sg_req[i].ch_regs.high_addr_ptr =3D + sg_req[i].src =3D apb_ptr; + sg_req[i].dst =3D mem; + sg_req[i].high_addr =3D FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32)); } /* * Word count register takes input in words. Writing a value * of N into word count register means a req of (N+1) words. */ - sg_req[i].ch_regs.wcount =3D ((len - 4) >> 2); - sg_req[i].ch_regs.csr =3D csr; - sg_req[i].ch_regs.mmio_seq =3D mmio_seq; - sg_req[i].ch_regs.mc_seq =3D mc_seq; + sg_req[i].wcount =3D ((len - 4) >> 2); + sg_req[i].csr =3D csr; + sg_req[i].mmio_seq =3D mmio_seq; + sg_req[i].mc_seq =3D mc_seq; sg_req[i].len =3D len; =20 mem +=3D len; @@ -1304,11 +1286,28 @@ static struct dma_chan *tegra_dma_of_xlate(struct o= f_phandle_args *dma_spec, return chan; } =20 +static const struct tegra_dma_channel_regs tegra186_reg_offsets =3D { + .csr =3D 0x0, + .status =3D 0x4, + .csre =3D 0x8, + .src =3D 0xc, + .dst =3D 0x10, + .high_addr =3D 0x14, + .mc_seq =3D 0x18, + .mmio_seq =3D 0x1c, + .wcount =3D 0x20, + .wxfer =3D 0x24, + .wstatus =3D 0x28, + .err_status =3D 0x30, + .fixed_pattern =3D 0x34, +}; + static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { .nr_channels =3D 32, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D false, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_stop_client, }; =20 @@ -1317,6 +1316,7 @@ static const struct tegra_dma_chip_data tegra194_dma_= chip_data =3D { .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_pause, }; =20 @@ -1325,6 +1325,7 @@ static const struct tegra_dma_chip_data tegra234_dma_= chip_data =3D { .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, + .channel_regs =3D &tegra186_reg_offsets, .terminate =3D tegra_dma_pause_noerr, }; =20 @@ -1345,7 +1346,7 @@ MODULE_DEVICE_TABLE(of, tegra_dma_of_match); =20 static int tegra_dma_program_sid(struct tegra_dma_channel *tdc, int stream= _id) { - unsigned int reg_val =3D tdc_read(tdc, TEGRA_GPCDMA_CHAN_MCSEQ); + unsigned int reg_val =3D tdc_read(tdc, tdc->regs->mc_seq); =20 reg_val &=3D ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK); reg_val &=3D ~(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK); @@ -1353,7 +1354,7 @@ static int tegra_dma_program_sid(struct tegra_dma_cha= nnel *tdc, int stream_id) reg_val |=3D FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID0_MASK, stream_id); reg_val |=3D FIELD_PREP(TEGRA_GPCDMA_MCSEQ_STREAM_ID1_MASK, stream_id); =20 - tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, reg_val); + tdc_write(tdc, tdc->regs->mc_seq, reg_val); return 0; } =20 @@ -1419,6 +1420,7 @@ static int tegra_dma_probe(struct platform_device *pd= ev) tdc->chan_base_offset =3D TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + i * cdata->channel_reg_size; snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); + tdc->regs =3D cdata->channel_regs; tdc->tdma =3D tdma; tdc->id =3D i; tdc->slave_id =3D -1; --=20 2.50.1