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Mon, 30 Mar 2026 06:23:51 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 1/5] clk: renesas: r9a08g046: Add GPIO clocks/resets Date: Mon, 30 Mar 2026 14:23:38 +0100 Message-ID: <20260330132349.149391-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330132349.149391-1-biju.das.jz@bp.renesas.com> References: <20260330132349.149391-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add GPIO clock and reset entries. Signed-off-by: Biju Das --- drivers/clk/renesas/r9a08g046-cpg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a0= 8g046-cpg.c index e75781198873..d31572a99f73 100644 --- a/drivers/clk/renesas/r9a08g046-cpg.c +++ b/drivers/clk/renesas/r9a08g046-cpg.c @@ -174,6 +174,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] = __initconst =3D { DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_ETH1_RM, 1, 1), DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1), DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1), + DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1), }; =20 static const struct rzg2l_mod_clk r9a08g046_mod_clks[] =3D { @@ -233,6 +234,8 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = =3D { MSTOP(BUS_PERI_COM, BIT(3))), DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584= , 0, MSTOP(BUS_MCPU2, BIT(1))), + DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0, + MSTOP(BUS_PERI_CPU, BIT(6))), }; =20 static const struct rzg2l_reset r9a08g046_resets[] =3D { @@ -244,6 +247,9 @@ static const struct rzg2l_reset r9a08g046_resets[] =3D { DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0), DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1), DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0), + DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0), + DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1), + DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2), }; =20 static const unsigned int r9a08g046_crit_mod_clks[] __initconst =3D { --=20 2.43.0