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Mon, 30 Mar 2026 03:44:54 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: Chris Brandt , Laurent Pinchart , Sam Ravnborg , dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das Subject: [PATCH v3 3/3] drm: renesas: rzg2l_mipi_dsi: Fix deassert/assert of CMN_RSTB signal Date: Mon, 30 Mar 2026 11:44:46 +0100 Message-ID: <20260330104450.128512-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330104450.128512-1-biju.das.jz@bp.renesas.com> References: <20260330104450.128512-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G2L hardware manual (Rev. 1.50, May 2025), Section 34.4.2.1, requires deasserting the CMN_RSTB signal after setting the Link registers. Move the reset_control_deassert() call from rzg2l_mipi_dsi_dphy_init() to rzg2l_mipi_dsi_startup(), placing it after the Link register writes. This reset signal is optional for RZ/V2H SoCs, so add a NULL check. Drop the unused ret variable from rzg2l_mipi_dsi_dphy_init(). The CMN_RSTB signal is not required for reading PHY registers in the probe. Move reset_control_assert() from rzg2l_mipi_dsi_dphy_exit() to rzg2l_mipi_dsi_stop(), placing it before the dphy_exit() call. Since this reset signal is optional for RZ/V2H, the call is a no-op on that SoC. Signed-off-by: Biju Das --- v2->v3: * Merged patch#2 and patch#3 to avoid breakage. * Updated commit description v1->v2: * Updated commit header and description * Moved the code from rzg2l_mipi_dsi_dphy_init() to rzg2l_mipi_dsi_startup= () * Moved the check before calling reset_control_deassert(), so that it will= be skipped for RZ/V2H SoC --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index 9d9f77d8f949..715872130780 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -484,7 +484,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_d= si *dsi, u32 dphytim1; u32 dphytim2; u32 dphytim3; - int ret; =20 /* All DSI global operation timings are set with recommended setting */ for (i =3D 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { @@ -524,12 +523,6 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_= dsi *dsi, rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM2, dphytim2); rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYTIM3, dphytim3); =20 - ret =3D reset_control_deassert(dsi->rstc); - if (ret < 0) - return ret; - - fsleep(1000); - return 0; } =20 @@ -541,8 +534,6 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mipi_= dsi *dsi) =20 dphyctrl0 &=3D ~(DSIDPHYCTRL0_EN_LDO1200 | DSIDPHYCTRL0_EN_BGR); rzg2l_mipi_dsi_phy_write(dsi, DSIDPHYCTRL0, dphyctrl0); - - reset_control_assert(dsi->rstc); } =20 static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long = mode_freq, @@ -811,6 +802,14 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_ds= i *dsi, FIELD_MODIFY(DSISETR_MRPSZ, &dsisetr, RZG2L_DCS_BUF_SIZE); rzg2l_mipi_dsi_link_write(dsi, DSISETR, dsisetr); =20 + if (dsi->rstc) { + ret =3D reset_control_deassert(dsi->rstc); + if (ret < 0) + goto err_phy; + + fsleep(1000); + } + return 0; =20 err_phy: @@ -822,6 +821,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi= *dsi, =20 static void rzg2l_mipi_dsi_stop(struct rzg2l_mipi_dsi *dsi) { + reset_control_assert(dsi->rstc); dsi->info->dphy_exit(dsi); pm_runtime_put(dsi->dev); } --=20 2.43.0