From nobody Thu Apr 2 05:51:09 2026 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A5F92E8B71 for ; Mon, 30 Mar 2026 10:29:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774866545; cv=none; b=u6ks/nv+dOSRArcoE0NECX9xwg1FvWCB9keK/6dwvGa0kFPaOCgqSEMK4a06ki3SiimjNPVIAifhN0Bh9IpERL2k/mNfLXGrNcPsIX234fUM0syh/n2aXIQAqDar7z044usvkekGaXF048Mh9K25Itmf2uIbs6sEwmHro85g790= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774866545; c=relaxed/simple; bh=xR4/eiW2jwE62sTUaUNq6rB16VdY5+2Jv/gBv7tkuoc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ti9MJvdCsC/EmzwIuNo5FTpltAsEEd4gnFfxh4UmUj8lYxsh4MAXMtwyuYnM8c1CT748ck2KS70J4hkivs0GIqM0Itz+qsMb7kgECmYZihQcOQ4V1Pk+zwxUj9crGJsvE6EbR7usH/IeMYRH67ebq5Qu2MDIvSmnHCLBBraDiQg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UASI1F038289; Mon, 30 Mar 2026 18:28:18 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:18 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 6/7] dts: riscv: update cache compatible strings to LLC Date: Mon, 30 Mar 2026 18:27:23 +0800 Message-ID: <20260330102724.1012470-7-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 62UASI1F038289 Content-Type: text/plain; charset="utf-8" Update the cache driver compatible strings from ax45mp-cache to llcache for both Qilai and RZ/Five platforms. This follows the Andes cache driver refactoring to use more generic Last Level Cache (LLC) naming. Signed-off-by: Hui Min Mina Chou --- arch/riscv/boot/dts/andes/qilai.dtsi | 4 ++-- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi index de3de32f8c39..a7436cbf6f69 100644 --- a/arch/riscv/boot/dts/andes/qilai.dtsi +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -137,8 +137,8 @@ plmt: timer@100000 { }; =20 l2_cache: cache-controller@200000 { - compatible =3D "andestech,qilai-ax45mp-cache", - "andestech,ax45mp-cache", "cache"; + compatible =3D "andestech,qilai-llcache", + "andestech,llcache", "cache"; reg =3D <0x0 0x00200000 0x0 0x100000>; interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; cache-line-size =3D <64>; diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/= dts/renesas/r9a07g043f.dtsi index 571de3cafa82..83a5d4d41f8e 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -144,7 +144,7 @@ plic: interrupt-controller@12c00000 { }; =20 l2cache: cache-controller@13400000 { - compatible =3D "renesas,r9a07g043f-ax45mp-cache", "andestech,ax45mp-cach= e", + compatible =3D "renesas,r9a07g043f-llcache", "andestech,llcache", "cache"; reg =3D <0x0 0x13400000 0x0 0x100000>; interrupts =3D ; --=20 2.34.1