From nobody Thu Apr 2 05:51:08 2026 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAFF13C1995 for ; Mon, 30 Mar 2026 10:47:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867671; cv=none; b=hsIRNqlTThbWmViXcnJ1ZVzOSOUNIIbQlBZmVevaWUgP9+9ExFCMtSFD1bhoNJ3vYqjrDW5nzTccU/9YExMe8bVQ/gggbPCY+ZBOWtrcW3ouFKiCykm9D0AJxOy8QE34u9T2G9bwgA3q+6m+Vf4OghdBZyihsc0NZ4gTiHv1nF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867671; c=relaxed/simple; bh=CQ87WG7tB0NGFgqYnwUzrD65BoyJsudzvJu0vnidgbQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Gh7fYONbiLyNsFKR+Tic+DUGyo0wL5Onx8VKOumsA26jfI9xJL36Gxs1i1L2+gSVfsVYTEdMIiv19JjPFvmQ2F8CU7Gq3xKnTq+/yaf2f7SjjXy7FsZ8VqC7VqDugaAM5Q4/JVj2F77/MlI6/gJB+duaXPaXnUWuGayXxSX5G5s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 62UASm6l039345 for ; Mon, 30 Mar 2026 18:28:48 +0800 (+08) (envelope-from minachou@andestech.com) Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UASEsn038230; Mon, 30 Mar 2026 18:28:14 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:14 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 4/7] cache: andes_llcache: centralize cache ops and use native WBINVAL Date: Mon, 30 Mar 2026 18:27:21 +0800 Message-ID: <20260330102724.1012470-5-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 62UASm6l039345 Content-Type: text/plain; charset="utf-8" Introduce andes_cpu_cache_operation() to centralize address translation, alignment, and IRQ handling, removing the redundant wrappers andes_cpu_dcache_wb_range and andes_cpu_dcache_inval_range. This refactoring includes the following refinements: - Consolidates address translation, boundary alignment, and IRQ handling (local_irq_save/restore) into the central function. - Make IRQ handling per cache line instead of across the entire cache operation. - Cleans up redundant intermediate wrapper functions (andes_cpu_dcache_wb_range, andes_cpu_dcache_inval_range). - wback_inv was chaining wback + inv separately; use the hardware's native WBINVAL CCTL instead, which does both in one shot. Signed-off-by: Alex Chun-Ju Lin Signed-off-by: Hui Min Mina Chou --- drivers/cache/andes_llcache.c | 63 ++++++++++++----------------------- 1 file changed, 21 insertions(+), 42 deletions(-) diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c index 57f666bc537a..0efa6e9c80bd 100644 --- a/drivers/cache/andes_llcache.c +++ b/drivers/cache/andes_llcache.c @@ -69,21 +69,29 @@ static inline uint32_t andes_cpu_llc_get_cctl_status(vo= id) return readl_relaxed(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFS= ET_C0); } =20 -static void andes_cpu_cache_operation(unsigned long start, unsigned long e= nd, - unsigned int l1_op, unsigned int llc_op) +static void andes_cpu_cache_operation(phys_addr_t paddr, size_t size, + unsigned int l1_op, unsigned int llc_op) { unsigned long line_size =3D andes_priv.andes_cache_line_size; void __iomem *base =3D andes_priv.llc_base; + unsigned long start =3D (unsigned long)phys_to_virt(paddr); + unsigned long end =3D start + size; + unsigned long flags; unsigned long pa; int mhartid =3D 0; =20 + start =3D ALIGN_DOWN(start, line_size); + end =3D ALIGN(end, line_size); + if (IS_ENABLED(CONFIG_SMP)) mhartid =3D cpuid_to_hartid_map(get_cpu()); else mhartid =3D cpuid_to_hartid_map(0); =20 mb(); /* complete earlier memory accesses before the cache flush */ - while (end > start) { + for (; start < end; start +=3D line_size) { + local_irq_save(flags); + csr_write(CSR_UCCTLBEGINADDR, start); csr_write(CSR_UCCTLCOMMAND, l1_op); =20 @@ -95,7 +103,7 @@ static void andes_cpu_cache_operation(unsigned long star= t, unsigned long end, ANDES_LLC_CCTL_STATUS_IDLE) ; =20 - start +=3D line_size; + local_irq_restore(flags); } mb(); /* issue later memory accesses after the cache flush */ =20 @@ -103,60 +111,31 @@ static void andes_cpu_cache_operation(unsigned long s= tart, unsigned long end, put_cpu(); } =20 -/* Write-back L1 and LLC entry */ -static inline void andes_cpu_dcache_wb_range(unsigned long start, unsigned= long end) -{ - andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_WB, - ANDES_LLC_CCTL_PA_WB); -} - -/* Invalidate the L1 and LLC entry */ -static inline void andes_cpu_dcache_inval_range(unsigned long start, unsig= ned long end) -{ - andes_cpu_cache_operation(start, end, ANDES_L1D_CCTL_VA_INVAL, - ANDES_LLC_CCTL_PA_INVAL); -} - static void andes_dma_cache_inv(phys_addr_t paddr, size_t size) { - unsigned long start =3D (unsigned long)phys_to_virt(paddr); - unsigned long end =3D start + size; - unsigned long line_size =3D andes_priv.andes_cache_line_size; - unsigned long flags; - if (unlikely(!size)) return; =20 - start =3D ALIGN_DOWN(start, line_size); - end =3D ALIGN(end, line_size); - - local_irq_save(flags); - andes_cpu_dcache_inval_range(start, end); - local_irq_restore(flags); + andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_INVAL, + ANDES_LLC_CCTL_PA_INVAL); } =20 static void andes_dma_cache_wback(phys_addr_t paddr, size_t size) { - unsigned long start =3D (unsigned long)phys_to_virt(paddr); - unsigned long end =3D start + size; - unsigned long line_size =3D andes_priv.andes_cache_line_size; - unsigned long flags; - if (unlikely(!size)) return; =20 - start =3D ALIGN_DOWN(start, line_size); - end =3D ALIGN(end, line_size); - - local_irq_save(flags); - andes_cpu_dcache_wb_range(start, end); - local_irq_restore(flags); + andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_WB, + ANDES_LLC_CCTL_PA_WB); } =20 static void andes_dma_cache_wback_inv(phys_addr_t paddr, size_t size) { - andes_dma_cache_wback(paddr, size); - andes_dma_cache_inv(paddr, size); + if (unlikely(!size)) + return; + + andes_cpu_cache_operation(paddr, size, ANDES_L1D_CCTL_VA_WBINVAL, + ANDES_LLC_CCTL_PA_WBINVAL); } =20 static int andes_get_llc_line_size(struct device_node *np) --=20 2.34.1