From nobody Thu Apr 2 05:51:09 2026 Received: from Atcsqr.andestech.com (exmail.andestech.com [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CDA23C3BE5 for ; Mon, 30 Mar 2026 10:47:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867667; cv=none; b=AL2t5I+bhcv8w1zdf0uF8fFe+7gjx1vePi8sDb5cvweCF1sme/LoKQ0SRtHMgnRt/7HXv3k+P2pyuFWd+G6XkmL7ocnQTl2xUTHgpZQ4/tkEWnTe22rMGVsD3qAQ9fsdLfL4Q9vBIcE/kybdSqwU8LENACHwiapzenK/qnoRYuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867667; c=relaxed/simple; bh=/47/5HHnaif3JHAckrH81FG+m9EH64JkilwpPo/i3Fo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QfgssvLANzifFE5Co6ot4THUQQCbdYmeI7ziw96iKuNNyfkTQfgksfl5Rat13fr6LHROUOza/O1q2Ut7VzdcW3SZFSXZ6uvImaO0v6rw1I1RerGIy2XZy+qoKEcyfPfeysUtFTvKwB8k3Xi5H02grYbdpUYeOX2BAVGQr9CEd6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 62UASONH038345 for ; Mon, 30 Mar 2026 18:28:24 +0800 (+08) (envelope-from minachou@andestech.com) Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UAS8LP038225; Mon, 30 Mar 2026 18:28:08 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:07 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" , Leo Yu-Chi Liang Subject: [PATCH 3/7] cache: andes_llcache: improve performance of LLC operation Date: Mon, 30 Mar 2026 18:27:20 +0800 Message-ID: <20260330102724.1012470-4-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 62UASONH038345 Content-Type: text/plain; charset="utf-8" Eliminate get_cpu() on !CONFIG_SMP and switch readl/writel to their relaxed variants to remove unnecessary fence instructions on I/O memory access. The platform specification defines all I/O regions are on channel 0 (point-to-point strongly ordered), so explicit fences are not required [1][2][3]. Explicit memory barriers (mb) are added before and after the CCTL loop to ensure overall memory consistency. Also fix hart ID mapping by switching to cpuid_to_hartid_map() instead of using the logical CPU ID directly. In AMP setups (e.g. Linux on Hart 1, RTOS on Hart 0), Linux sees itself as CPU 0 but must access Hart 1's CCTL registers, so using the logical ID would cause accidental interference with other cores. [1] platform spec 2.1.1: https://github.com/riscvarchive/riscv-platform-spe= cs/blob/main/riscv-platform-spec.adoc?plain=3D1#L169 [2] privileged spec 3.6.5: https://github.com/riscv/riscv-isa-manual/blob/m= ain/src/machine.adoc?plain=3D1#L2835 [3] riscv: asm/mmio.h: https://gitea.andestech.com/RD-SW/linux/src/branch/a= st-v5_4_0-branch/arch/riscv/include/asm/mmio.h#L105 Signed-off-by: Leo Yu-Chi Liang Signed-off-by: Hui Min Mina Chou --- drivers/cache/andes_llcache.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c index d318b8009f7f..57f666bc537a 100644 --- a/drivers/cache/andes_llcache.c +++ b/drivers/cache/andes_llcache.c @@ -66,7 +66,7 @@ static struct andes_priv andes_priv; /* LLC operations */ static inline uint32_t andes_cpu_llc_get_cctl_status(void) { - return readl(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFSET_C0); + return readl_relaxed(andes_priv.llc_base + ANDES_LLC_REG_CCTL_STATUS_OFFS= ET_C0); } =20 static void andes_cpu_cache_operation(unsigned long start, unsigned long e= nd, @@ -74,16 +74,22 @@ static void andes_cpu_cache_operation(unsigned long sta= rt, unsigned long end, { unsigned long line_size =3D andes_priv.andes_cache_line_size; void __iomem *base =3D andes_priv.llc_base; - int mhartid =3D smp_processor_id(); unsigned long pa; + int mhartid =3D 0; =20 + if (IS_ENABLED(CONFIG_SMP)) + mhartid =3D cpuid_to_hartid_map(get_cpu()); + else + mhartid =3D cpuid_to_hartid_map(0); + + mb(); /* complete earlier memory accesses before the cache flush */ while (end > start) { csr_write(CSR_UCCTLBEGINADDR, start); csr_write(CSR_UCCTLCOMMAND, l1_op); =20 pa =3D virt_to_phys((void *)start); - writel(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid)); - writel(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhartid)); + writel_relaxed(pa, base + ANDES_LLC_REG_CCTL_ACC_OFFSET_BY_CORE(mhartid)= ); + writel_relaxed(llc_op, base + ANDES_LLC_REG_CCTL_CMD_OFFSET_BY_CORE(mhar= tid)); while ((andes_cpu_llc_get_cctl_status() & ANDES_LLC_CCTL_STATUS_MASK_BY_CORE(mhartid)) !=3D ANDES_LLC_CCTL_STATUS_IDLE) @@ -91,6 +97,10 @@ static void andes_cpu_cache_operation(unsigned long star= t, unsigned long end, =20 start +=3D line_size; } + mb(); /* issue later memory accesses after the cache flush */ + + if (IS_ENABLED(CONFIG_SMP)) + put_cpu(); } =20 /* Write-back L1 and LLC entry */ --=20 2.34.1