From nobody Thu Apr 2 05:51:08 2026 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B34223C13F1 for ; Mon, 30 Mar 2026 10:47:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867663; cv=none; b=f1t5VtFWxWZvl+W6D7+pNf1snYliZCN3CwoX1CCo7Ix64Oy3kvmdJQFejynfMQUovJrQZUXj0mKYBlnfnPxcO11QcCyflFk1QbyXfvZWMU3SC++21PtsVYCAQExA9s674ypIvrHp3zveKx6KcO9N1rU+WJVFJF4NFrRzTa1uAUA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867663; c=relaxed/simple; bh=hKHKp9my13roBU2qU8iKtL9x9H9TJ7oi8Qn9L8SW+R4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aL903k3mNuoZ4ydLZf7nqi/wmb23k3S+deKtc5pRC2Rl3vu5y5Iy/cLY0owdsT1mSXAlyRqP/d/5E6+KeOMDNDnmbXUVnSe6OiKk2iPGiiSdpWVMvOoc8zB1ie94lhrsiwe1nO/w5mD98PRMWVKgtmIyQbRRrnuiswVH3HByiGw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 62UASESw038229 for ; Mon, 30 Mar 2026 18:28:14 +0800 (+08) (envelope-from minachou@andestech.com) Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UAS2eU038167; Mon, 30 Mar 2026 18:28:02 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:28:02 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 2/7] cache: andes_llcache: refactor initialization and cache operations Date: Mon, 30 Mar 2026 18:27:19 +0800 Message-ID: <20260330102724.1012470-3-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330102724.1012470-1-minachou@andestech.com> References: <20260330102724.1012470-1-minachou@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 62UASESw038229 Content-Type: text/plain; charset="utf-8" This patch cleans up the Andes LLC cache driver: - improved error handling in andes_cache_init() by using goto labels - updated andes_dma_cache_inv/wback() to check for !size instead of start =3D=3D end - cache-line-size mismatch from an error to a warning - Use ALIGN and ALIGN_DOWN helpers instead of the alignment logic in andes_dma_cache_inv() and andes_dma_cache_wback(). Signed-off-by: Hui Min Mina Chou --- drivers/cache/andes_llcache.c | 56 ++++++++++++++++++----------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/cache/andes_llcache.c b/drivers/cache/andes_llcache.c index d5e382f3c801..d318b8009f7f 100644 --- a/drivers/cache/andes_llcache.c +++ b/drivers/cache/andes_llcache.c @@ -111,21 +111,17 @@ static void andes_dma_cache_inv(phys_addr_t paddr, si= ze_t size) { unsigned long start =3D (unsigned long)phys_to_virt(paddr); unsigned long end =3D start + size; - unsigned long line_size; + unsigned long line_size =3D andes_priv.andes_cache_line_size; unsigned long flags; =20 - if (unlikely(start =3D=3D end)) + if (unlikely(!size)) return; =20 - line_size =3D andes_priv.andes_cache_line_size; - - start =3D start & (~(line_size - 1)); - end =3D ((end + line_size - 1) & (~(line_size - 1))); + start =3D ALIGN_DOWN(start, line_size); + end =3D ALIGN(end, line_size); =20 local_irq_save(flags); - andes_cpu_dcache_inval_range(start, end); - local_irq_restore(flags); } =20 @@ -133,15 +129,15 @@ static void andes_dma_cache_wback(phys_addr_t paddr, = size_t size) { unsigned long start =3D (unsigned long)phys_to_virt(paddr); unsigned long end =3D start + size; - unsigned long line_size; + unsigned long line_size =3D andes_priv.andes_cache_line_size; unsigned long flags; =20 - if (unlikely(start =3D=3D end)) + if (unlikely(!size)) return; =20 - line_size =3D andes_priv.andes_cache_line_size; - start =3D start & (~(line_size - 1)); - end =3D ((end + line_size - 1) & (~(line_size - 1))); + start =3D ALIGN_DOWN(start, line_size); + end =3D ALIGN(end, line_size); + local_irq_save(flags); andes_cpu_dcache_wb_range(start, end); local_irq_restore(flags); @@ -159,14 +155,13 @@ static int andes_get_llc_line_size(struct device_node= *np) =20 ret =3D of_property_read_u32(np, "cache-line-size", &andes_priv.andes_cac= he_line_size); if (ret) { - pr_err("Failed to get cache-line-size, defaulting to 64 bytes\n"); + pr_err("Cache: Failed to get cache-line-size\n"); return ret; } =20 if (andes_priv.andes_cache_line_size !=3D ANDES_CACHE_LINE_SIZE) { - pr_err("Expected cache-line-size to be 64 bytes (found:%u)\n", - andes_priv.andes_cache_line_size); - return -EINVAL; + pr_warn("Cache: Expected cache-line-size to be 64 bytes (found:%u)\n", + andes_priv.andes_cache_line_size); } =20 return 0; @@ -186,16 +181,18 @@ static const struct of_device_id andes_cache_ids[] = =3D { static int __init andes_cache_init(void) { struct resource res; - int ret; + int ret =3D 0; =20 struct device_node *np __free(device_node) =3D of_find_matching_node(NULL, andes_cache_ids); - if (!of_device_is_available(np)) - return -ENODEV; + if (!of_device_is_available(np)) { + ret =3D -ENODEV; + goto err_ret; + } =20 ret =3D of_address_to_resource(np, 0, &res); if (ret) - return ret; + goto err_ret; =20 /* * If IOCP is present on the Andes AX45MP core riscv_cbom_block_size @@ -208,17 +205,22 @@ static int __init andes_cache_init(void) return 0; =20 andes_priv.llc_base =3D ioremap(res.start, resource_size(&res)); - if (!andes_priv.llc_base) - return -ENOMEM; + if (!andes_priv.llc_base) { + ret =3D -ENOMEM; + goto err_ret; + } =20 ret =3D andes_get_llc_line_size(np); - if (ret) { - iounmap(andes_priv.llc_base); - return ret; - } + if (ret) + goto err_unmap; =20 riscv_noncoherent_register_cache_ops(&andes_cmo_ops); =20 return 0; + +err_unmap: + iounmap(andes_priv.llc_base); +err_ret: + return ret; } early_initcall(andes_cache_init); --=20 2.34.1