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charset="utf-8" This will be reused in a new iommufd.c file for nested translation. Signed-off-by: Suravee Suthikulpanit Reviewed-by: Nicolin Chen --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/iommu.c | 26 ++++++++++++-------------- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 02f10922f70b..7308c6f1835c 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -197,6 +197,7 @@ void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_da= ta, void amd_iommu_update_dte(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, struct dev_table_entry *new); +int amd_iommu_completion_wait(struct amd_iommu *iommu); =20 static inline void amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table= _entry *new) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 7e724f5675f4..ffa65a97ba86 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -90,8 +90,6 @@ static int amd_iommu_set_dirty_tracking(struct iommu_doma= in *domain, =20 static void clone_aliases(struct amd_iommu *iommu, struct device *dev); =20 -static int iommu_completion_wait(struct amd_iommu *iommu); - /*************************************************************************= *** * * Helper functions @@ -216,7 +214,7 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, update_dte256(iommu, dev_data, new); clone_aliases(iommu, dev_data->dev); device_flush_dte(dev_data); - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void get_dte256(struct amd_iommu *iommu, struct iommu_dev_data *dev= _data, @@ -1443,7 +1441,7 @@ static int iommu_queue_command(struct amd_iommu *iomm= u, struct iommu_cmd *cmd) * This function queues a completion wait command into the command * buffer of an IOMMU */ -static int iommu_completion_wait(struct amd_iommu *iommu) +int amd_iommu_completion_wait(struct amd_iommu *iommu) { struct iommu_cmd cmd; unsigned long flags; @@ -1481,7 +1479,7 @@ static void domain_flush_complete(struct protection_d= omain *domain) * We need to wait for completion of all commands. */ xa_for_each(&domain->iommu_array, i, pdom_iommu_info) - iommu_completion_wait(pdom_iommu_info->iommu); + amd_iommu_completion_wait(pdom_iommu_info->iommu); } =20 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) @@ -1499,7 +1497,7 @@ static void iommu_flush_dte_sync(struct amd_iommu *io= mmu, u16 devid) =20 ret =3D iommu_flush_dte(iommu, devid); if (!ret) - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu) @@ -1510,7 +1508,7 @@ static void amd_iommu_flush_dte_all(struct amd_iommu = *iommu) for (devid =3D 0; devid <=3D last_bdf; ++devid) iommu_flush_dte(iommu, devid); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 /* @@ -1529,7 +1527,7 @@ static void amd_iommu_flush_tlb_all(struct amd_iommu = *iommu) iommu_queue_command(iommu, &cmd); } =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id) @@ -1540,7 +1538,7 @@ static void amd_iommu_flush_tlb_domid(struct amd_iomm= u *iommu, u32 dom_id) dom_id, IOMMU_NO_PASID, false); iommu_queue_command(iommu, &cmd); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static int iommu_flush_pages_v1_hdom_ids(struct protection_domain *pdom, u= 64 address, size_t size) @@ -1576,7 +1574,7 @@ static void amd_iommu_flush_all(struct amd_iommu *iom= mu) build_inv_all(&cmd); =20 iommu_queue_command(iommu, &cmd); - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid) @@ -1599,7 +1597,7 @@ static void amd_iommu_flush_irt_all(struct amd_iommu = *iommu) for (devid =3D 0; devid <=3D last_bdf; devid++) iommu_flush_irt(iommu, devid); =20 - iommu_completion_wait(iommu); + amd_iommu_completion_wait(iommu); } =20 void amd_iommu_flush_all_caches(struct amd_iommu *iommu) @@ -1835,7 +1833,7 @@ void amd_iommu_dev_flush_pasid_pages(struct iommu_dev= _data *dev_data, if (dev_data->ats_enabled) device_flush_iotlb(dev_data, address, size, pasid, true); =20 - iommu_completion_wait(iommu); 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charset="utf-8" Adding support for new vIOMMU events: * Guest Event Fault event * vIOMMU Hardware Error event Also, adding support for the additional vIOMMU related flags in existing events. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 3 ++ drivers/iommu/amd/iommu.c | 58 ++++++++++++++++++++++------- 2 files changed, 48 insertions(+), 13 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index cfcbad6c28ff..31f7f426bab6 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -153,6 +153,9 @@ #define EVENT_TYPE_IOTLB_INV_TO 0x7 #define EVENT_TYPE_INV_DEV_REQ 0x8 #define EVENT_TYPE_INV_PPR_REQ 0x9 +#define EVENT_TYPE_GUEST_EVENT_FAULT 0xb +#define EVENT_TYPE_VIOMMU_HW_ERR 0xc + #define EVENT_TYPE_RMP_FAULT 0xd #define EVENT_TYPE_RMP_HW_ERR 0xe #define EVENT_DEVID_MASK 0xffff diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index ffa65a97ba86..d1f997b9a90b 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -849,7 +849,7 @@ static void amd_iommu_report_rmp_fault(struct amd_iommu= *iommu, volatile u32 *ev =20 static void amd_iommu_report_page_fault(struct amd_iommu *iommu, u16 devid, u16 domain_id, - u64 address, int flags) + u64 address, int flags, u8 vflags) { struct iommu_dev_data *dev_data =3D NULL; struct pci_dev *pdev; @@ -884,13 +884,13 @@ static void amd_iommu_report_page_fault(struct amd_io= mmu *iommu, } =20 if (__ratelimit(&dev_data->rs)) { - pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=3D0x%04x address=3D0x= %llx flags=3D0x%04x]\n", - domain_id, address, flags); + pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=3D0x%04x address=3D0x= %llx flags=3D0x%04x vflags=3D%#x]\n", + domain_id, address, flags, vflags); } } else { - pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=3D%04x:%02x:%02x.= %x domain=3D0x%04x address=3D0x%llx flags=3D0x%04x]\n", + pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=3D%04x:%02x:%02x.= %x domain=3D0x%04x address=3D0x%llx flags=3D0x%04x vflags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - domain_id, address, flags); + domain_id, address, flags, vflags); } =20 out: @@ -927,29 +927,42 @@ static void iommu_print_event(struct amd_iommu *iommu= , void *__evt) } =20 if (type =3D=3D EVENT_TYPE_IO_FAULT) { - amd_iommu_report_page_fault(iommu, devid, pasid, address, flags); + u8 vflags =3D (event[0] >> 27) & 0x1F; + + amd_iommu_report_page_fault(iommu, devid, pasid, address, flags, vflags); return; } =20 switch (type) { case EVENT_TYPE_ILL_DEV: - dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=3D%04x:%02x:%= 02x.%x pasid=3D0x%05x address=3D0x%llx flags=3D0x%04x]\n", + { + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY deice=3D%04x:%02x:%0= 2x.%x pasid=3D0x%05x address=3D0x%llx flags=3D0x%04x vflags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - pasid, address, flags); + pasid, address, flags, vflags); dev_err(dev, "Control Reg : 0x%llx\n", ctrl); dump_dte_entry(iommu, devid); break; + } case EVENT_TYPE_DEV_TAB_ERR: - dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=3D%04x:%02x:%0= 2x.%x " - "address=3D0x%llx flags=3D0x%04x]\n", + { + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=3D%04x:%02x:%0= 2x.%x address=3D%#llx flags=3D%#04x vlfags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - address, flags); + address, flags, vflags); break; + } case EVENT_TYPE_PAGE_TAB_ERR: - dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=3D%04x:%02x:%= 02x.%x pasid=3D0x%04x address=3D0x%llx flags=3D0x%04x]\n", + { + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=3D%04x:%02x:%= 02x.%x pasid=3D0x%04x address=3D0x%llx flags=3D0x%04x vflags=3D%#x]\n", iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), - pasid, address, flags); + pasid, address, flags, vflags); break; + } case EVENT_TYPE_ILL_CMD: dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=3D0x%llx]\n", = address); dump_command(address); @@ -981,6 +994,25 @@ static void iommu_print_event(struct amd_iommu *iommu,= void *__evt) iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid= ), pasid, address, flags, tag); break; + case EVENT_TYPE_GUEST_EVENT_FAULT: + { + u8 gid =3D event[1] & 0xFFFF; + u8 vflags =3D (event[0] >> 27) & 0x1F; + + dev_err(dev, "Event logged [GUEST_EVENT_FAULT gid=3D#%x flags=3D0x%04x v= flags=3D%#x]\n", + gid, flags, vflags); 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charset="utf-8" The feature is advertised w/ EFR[VIOMMUSup]. Please see the AMD IOMMU specification[1] for more detail. Introduce a new global variable amd_iommu_viommu, which is used to control the feature enablement in the driver. Currently, the feature is default to disabled. Once the feature is fully supported, it will be changed to enabled by default along with a command-line option to disable if needed. [1] https://docs.amd.com/v/u/en-US/48882_3.10_PUB Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/amd_viommu.h | 22 ++++++++++++++++++++++ drivers/iommu/amd/init.c | 13 +++++++++++++ drivers/iommu/amd/viommu.c | 29 +++++++++++++++++++++++++++++ 6 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/amd/amd_viommu.h create mode 100644 drivers/iommu/amd/viommu.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index 94b8ef2acb18..e1e824b9c7b0 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D iommu.o init.o quirks.o ppr.o pasid.o -obj-$(CONFIG_AMD_IOMMU_IOMMUFD) +=3D iommufd.o nested.o +obj-$(CONFIG_AMD_IOMMU_IOMMUFD) +=3D iommufd.o nested.o viommu.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) +=3D debugfs.o diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 7308c6f1835c..c440f2745b38 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -33,6 +33,8 @@ void amd_iommu_debugfs_setup(void); static inline void amd_iommu_debugfs_setup(void) {} #endif =20 +extern bool amd_iommu_viommu; + /* Needed for interrupt remapping */ int amd_iommu_prepare(void); int amd_iommu_enable(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 31f7f426bab6..c5f779d76fc4 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -106,6 +106,7 @@ #define FEATURE_HASUP BIT_ULL(49) #define FEATURE_EPHSUP BIT_ULL(50) #define FEATURE_HDSUP BIT_ULL(52) +#define FEATURE_VIOMMU BIT_ULL(55) #define FEATURE_SNP BIT_ULL(63) =20 =20 diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h new file mode 100644 index 000000000000..45c2b71af4ba --- /dev/null +++ b/drivers/iommu/amd/amd_viommu.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 Advanced Micro Devices, Inc. + */ + +#ifndef AMD_VIOMMU_H +#define AMD_VIOMMU_H + +#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) + +int amd_viommu_init(struct amd_iommu *iommu); + +#else + +static inline int amd_viommu_init(struct amd_iommu *iommu) +{ + return 0; +} + +#endif /* CONFIG_AMD_IOMMU_IOMMUFD */ + +#endif /* AMD_VIOMMU_H */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index b1c344ed7dbd..a1cc6aa6f7dc 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -34,6 +34,7 @@ #include =20 #include "amd_iommu.h" +#include "amd_viommu.h" #include "../irq_remapping.h" #include "../iommu-pages.h" =20 @@ -193,6 +194,9 @@ bool amdr_ivrs_remap_support __read_mostly; =20 bool amd_iommu_force_isolation __read_mostly; =20 +/* VIOMMU enabling flag */ +bool amd_iommu_viommu; + unsigned long amd_iommu_pgsize_bitmap __ro_after_init =3D AMD_IOMMU_PGSIZE= S; =20 enum iommu_init_state { @@ -2198,6 +2202,10 @@ static int __init iommu_init_pci(struct amd_iommu *i= ommu) if (check_feature(FEATURE_PPR) && amd_iommu_alloc_ppr_log(iommu)) return -ENOMEM; =20 + ret =3D amd_viommu_init(iommu); + if (ret) + pr_err("Failed to initialize vIOMMU.\n"); + if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { pr_info("Using strict mode due to virtualization\n"); iommu_set_dma_strict(); @@ -2291,6 +2299,9 @@ static void print_iommu_info(void) if (check_feature2(FEATURE_SEVSNPIO_SUP)) pr_cont(" SEV-TIO"); =20 + if (check_feature(FEATURE_VIOMMU)) + pr_cont(" vIOMMU"); + pr_cont("\n"); } =20 @@ -2303,6 +2314,8 @@ static void print_iommu_info(void) pr_info("V2 page table enabled (Paging mode : %d level)\n", amd_iommu_gpt_level); } + if (amd_iommu_viommu) + pr_info("AMD-Vi: vIOMMU enabled\n"); } =20 static int __init amd_iommu_init_pci(void) diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c new file mode 100644 index 000000000000..f4b5f96d4785 --- /dev/null +++ b/drivers/iommu/amd/viommu.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Advanced Micro Devices, Inc. + */ + +#define pr_fmt(fmt) "AMD-Vi: " fmt +#define dev_fmt(fmt) pr_fmt(fmt) + +#include +#include +#include +#include + +#include +#include + +#include "iommufd.h" +#include "amd_iommu.h" +#include "amd_iommu_types.h" +#include "amd_viommu.h" + +int __init amd_viommu_init(struct amd_iommu *iommu) +{ + if (!amd_iommu_viommu || + !check_feature(FEATURE_VIOMMU)) + return 0; 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charset="utf-8" Introduce a new enum iommu_viommu_type (IOMMU_VIOMMU_TYPE_AMD) for AMD vIOMMU along with the struct iommu_viommu_amd, which is used to initialize IOMMUFD vIOMMU instance when calling struct iommu_ops.viommu_init(). Also, hook up struct iomufd_viomu_ops.alloc_domain_nested to connect nested domain allocation with AMD vIOMMU implementation. Additional initialization will be added in subsequent patches. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommufd.c | 4 ++++ include/uapi/linux/iommufd.h | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index ad627fd5ccc7..e7ffa7e8915b 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -34,6 +34,9 @@ void *amd_iommufd_hw_info(struct device *dev, u32 *length= , u32 *type) =20 size_t amd_iommufd_get_viommu_size(struct device *dev, enum iommu_viommu_t= ype viommu_type) { + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_AMD) + return 0; + return VIOMMU_STRUCT_SIZE(struct amd_iommu_viommu, core); } =20 @@ -73,5 +76,6 @@ static void amd_iommufd_viommu_destroy(struct iommufd_vio= mmu *viommu) * struct iommufd_viommu_ops - vIOMMU specific operations */ static const struct iommufd_viommu_ops amd_viommu_ops =3D { + .alloc_domain_nested =3D amd_iommu_alloc_domain_nested, .destroy =3D amd_iommufd_viommu_destroy, }; diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 1dafbc552d37..3a2ac7234b9e 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1048,11 +1048,13 @@ struct iommu_fault_alloc { * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type * @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for= ARM * SMMUv3) enabled ARM SMMUv3 type + * @IOMMU_VIOMMU_TYPE_AMD: AMD HW-vIOMMU type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT =3D 0, IOMMU_VIOMMU_TYPE_ARM_SMMUV3 =3D 1, IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV =3D 2, + IOMMU_VIOMMU_TYPE_AMD =3D 3, }; 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charset="utf-8" AMD HW-vIOMMU feature requires IOMMU driver to specify a unique 16-bit Guest ID (GID) for each VM. This ID is per-vIOMMU instance, and it is used to index into various data structures for configuring the hardware. Introduce helper functions amd_iommu_gid_alloc() / amd_iommu_gid_free(), which will be called during vIOMMU initialize/destroy. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 4 ++++ drivers/iommu/amd/amd_iommu_types.h | 4 ++++ drivers/iommu/amd/iommu.c | 20 ++++++++++++++++++++ drivers/iommu/amd/iommufd.c | 29 +++++++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index c440f2745b38..51a7c3b3329f 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -226,4 +226,8 @@ amd_iommu_make_clear_dte(struct iommu_dev_data *dev_dat= a, struct dev_table_entry struct iommu_domain * amd_iommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags, const struct iommu_user_data *user_data); + +/* Guest ID for vIOMMU */ +int amd_iommu_gid_alloc(void); +void amd_iommu_gid_free(int gid); #endif /* AMD_IOMMU_H */ diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index c5f779d76fc4..0b4d713d3337 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -413,6 +413,9 @@ =20 #define MAX_DOMAIN_ID 65536 =20 +/* For vIOMMU, the GID is 16-bit. */ +#define VIOMMU_MAX_GID 0xFFFF + /* Timeout stuff */ #define LOOP_TIMEOUT 100000 #define MMIO_STATUS_TIMEOUT 2000000 @@ -509,6 +512,7 @@ struct amd_iommu_viommu { struct iommufd_viommu core; struct protection_domain *parent; /* nest parent domain for this viommu */ struct list_head pdom_list; /* For protection_domain->viommu_list */ + u16 gid; /* Guest ID for the vIOMMU */ =20 /* * Per-vIOMMU guest domain ID to host domain ID mapping. diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index d1f997b9a90b..037a50397f31 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -61,6 +61,9 @@ LIST_HEAD(acpihid_map); =20 const struct iommu_ops amd_iommu_ops; =20 +/* Global guest ID */ +static DEFINE_IDA(amd_iommu_global_gid_ida); + int amd_iommu_max_glx_val =3D -1; =20 /* @@ -252,6 +255,23 @@ static inline bool pdom_is_sva_capable(struct protecti= on_domain *pdom) return pdom_is_v2_pgtbl_mode(pdom) || pdom_is_in_pt_mode(pdom); } =20 +int amd_iommu_gid_alloc(void) +{ + int ret =3D ida_alloc_range(&amd_iommu_global_gid_ida, 1, VIOMMU_MAX_GID,= GFP_KERNEL); + + if (ret < 0) + pr_err("%s: Failed to allocate guest ID\n", __func__); + else + pr_debug("%s: gid=3D%u\n", __func__, ret); + + return ret; +} + +void amd_iommu_gid_free(int gid) +{ + ida_free(&amd_iommu_global_gid_ida, gid); +} + static inline int get_acpihid_device_id(struct device *dev, struct acpihid_map_entry **entry) { diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index e7ffa7e8915b..6fba5d9b1310 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -43,13 +43,35 @@ size_t amd_iommufd_get_viommu_size(struct device *dev, = enum iommu_viommu_type vi int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_do= main *parent, const struct iommu_user_data *user_data) { + int ret; unsigned long flags; + struct iommu_viommu_amd data; struct protection_domain *pdom =3D to_pdomain(parent); struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); =20 xa_init_flags(&aviommu->gdomid_array, XA_FLAGS_ALLOC1); aviommu->parent =3D pdom; =20 + if (!user_data) + return -EINVAL; + + ret =3D iommu_copy_struct_from_user(&data, user_data, + IOMMU_VIOMMU_TYPE_AMD, + reserved); + if (ret) + return ret; + + aviommu->gid =3D amd_iommu_gid_alloc(); + if (aviommu->gid < 0) + return aviommu->gid; + pr_debug("%s: gid=3D%#x", __func__, aviommu->gid); + + ret =3D iommu_copy_struct_to_user(user_data, &data, + IOMMU_VIOMMU_TYPE_AMD, + reserved); + if (ret) + goto err_out; + viommu->ops =3D &amd_viommu_ops; =20 spin_lock_irqsave(&pdom->lock, flags); @@ -57,6 +79,9 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu= , struct iommu_domain * spin_unlock_irqrestore(&pdom->lock, flags); =20 return 0; +err_out: + amd_iommu_gid_free(aviommu->gid); + return ret; } =20 static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu) @@ -64,11 +89,15 @@ static void amd_iommufd_viommu_destroy(struct iommufd_v= iommu *viommu) unsigned long flags; struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); struct protection_domain *pdom =3D aviommu->parent; + struct amd_iommu *iommu =3D container_of(viommu->iommu_dev, struct amd_io= mmu, iommu); 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charset="utf-8" To enable the vIOMMU feature, the AMD IOMMU driver needs to map vIOMMU VF MMIO and VF Control MMIO regions using information in the PCI vendor-specific capability (VSC). The VF Control MMIO region represents the 1st 4K of guest IOMMU mmio region, which contains IOMMU control registers, and will be trapped and handled by QEMU. The VF MMIO region represents the 3rd 4K of guest IOMMU mmio region, which will be virtualized by the IOMMU hardware. Signed-off-by: Vasant Hegde Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 29 ++++++++++ drivers/iommu/amd/init.c | 2 +- drivers/iommu/amd/viommu.c | 83 +++++++++++++++++++++++++++++ 4 files changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 51a7c3b3329f..470e5d98c52b 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -26,6 +26,7 @@ void amd_iommu_set_rlookup_table(struct amd_iommu *iommu,= u16 devid); void iommu_feature_enable(struct amd_iommu *iommu, u8 bit); void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); +u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS void amd_iommu_debugfs_setup(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 0b4d713d3337..f0e18a7dd7f2 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -38,6 +38,12 @@ #define MMIO_RANGE_OFFSET 0x0c #define MMIO_MISC_OFFSET 0x10 =20 +/* vIOMMU Capability offsets (from IOMMU Capability Header) */ +#define MMIO_VSC_VF_BAR_LO_OFFSET 0x08 +#define MMIO_VSC_VF_BAR_HI_OFFSET 0x0c +#define MMIO_VSC_VF_CNTL_BAR_LO_OFFSET 0x10 +#define MMIO_VSC_VF_CNTL_BAR_HI_OFFSET 0x14 + /* Masks, shifts and macros to parse the device range capability */ #define MMIO_RANGE_LD_MASK 0xff000000 #define MMIO_RANGE_FD_MASK 0x00ff0000 @@ -472,6 +478,16 @@ extern bool amdr_ivrs_remap_support; #define for_each_ivhd_dte_flags(entry) \ list_for_each_entry((entry), &amd_ivhd_dev_flags_list, list) =20 +/* VIOMMU stuff */ +#define VIOMMU_VF_MMIO_ENTRY_SIZE 4096 +#define VIOMMU_VFCTRL_MMIO_ENTRY_SIZE 64 + +#define VIOMMU_VF_MMIO_BASE(iommu, guestId) \ + (iommu->vf_base + (guestId * VIOMMU_VF_MMIO_ENTRY_SIZE)) + +#define VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId) \ + (iommu->vfctrl_base + (guestId * VIOMMU_VFCTRL_MMIO_ENTRY_SIZE)) + struct amd_iommu; struct iommu_domain; struct irq_domain; @@ -685,6 +701,19 @@ struct amd_iommu { */ u16 cap_ptr; =20 + /* Vendor-Specific Capability (VSC) pointer. */ + u16 vsc_offset; + + /* + * VF MMIO base physical address. This is needed to calculate/pass + * per guest VF MMIO address (3rd 4K of IOMMU MMIO space) + */ + u64 vf_base_phys; + + /* virtual addresses of vIOMMU VF/VF_CNTL BAR */ + u8 __iomem *vf_base; + u8 __iomem *vfctrl_base; + /* pci domain of this IOMMU */ struct amd_iommu_pci_seg *pci_seg; =20 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index a1cc6aa6f7dc..0018ae804ab4 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -478,7 +478,7 @@ static void iommu_disable(struct amd_iommu *iommu) * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMM= U in * the system has one. */ -static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) +u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end) { if (!request_mem_region(address, end, "amd_iommu")) { pr_err("Can not reserve memory region %llx-%llx for mmio\n", diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index f4b5f96d4785..887a9eb8122d 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -7,9 +7,15 @@ #define dev_fmt(fmt) pr_fmt(fmt) =20 #include +#include + +#include +#include +#include #include #include #include +#include =20 #include #include @@ -18,12 +24,89 @@ #include "amd_iommu.h" #include "amd_iommu_types.h" #include "amd_viommu.h" +#include "../iommu-pages.h" + +LIST_HEAD(viommu_devid_map); + +static int viommu_init_pci_vsc(struct amd_iommu *iommu) +{ + iommu->vsc_offset =3D pci_find_capability(iommu->dev, PCI_CAP_ID_VNDR); + if (!iommu->vsc_offset) + return -ENODEV; + + DUMP_printk("device:%s, vsc offset:%04x\n", + pci_name(iommu->dev), iommu->vsc_offset); + return 0; +} + +static int __init viommu_vf_vfcntl_init(struct amd_iommu *iommu) +{ + u32 lo, hi; + u64 vf_phys, vf_cntl_phys; + + /* Setting up VF and VF_CNTL MMIOs */ + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_BAR_LO_= OFFSET, &lo); + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_BAR_HI_= OFFSET, &hi); + vf_phys =3D hi; + vf_phys =3D (vf_phys << 32) | lo; + if (!(vf_phys & 1)) { + pr_err(FW_BUG "vf_phys disabled\n"); + return -EINVAL; + } + + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_CNTL_BA= R_LO_OFFSET, &lo); + pci_read_config_dword(iommu->dev, iommu->vsc_offset + MMIO_VSC_VF_CNTL_BA= R_HI_OFFSET, &hi); + vf_cntl_phys =3D hi; + vf_cntl_phys =3D (vf_cntl_phys << 32) | lo; + if (!(vf_cntl_phys & 1)) { + pr_err(FW_BUG "vf_cntl_phys disabled\n"); + return -EINVAL; + } + + if (!vf_phys || !vf_cntl_phys) { + pr_err(FW_BUG "AMD-Vi: Unassigned VF resources.\n"); + return -ENOMEM; + } + + /* Mapping 256MB of VF and 4MB of VF_CNTL BARs */ + vf_phys &=3D ~1ULL; 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charset="utf-8" The AMD vIOMMU virtualizes guest MMIO registers at the 3rd 4K region. This is achieved using the iommufd_viommu_alloc_mmap(). Co-developed-by: Vasant Hegde Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_viommu.h | 5 +++++ drivers/iommu/amd/iommufd.c | 17 ++++++++++++++++- drivers/iommu/amd/viommu.c | 11 +++++++++++ include/uapi/linux/iommufd.h | 2 ++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h index 45c2b71af4ba..8dbb12241e8d 100644 --- a/drivers/iommu/amd/amd_viommu.h +++ b/drivers/iommu/amd/amd_viommu.h @@ -10,6 +10,7 @@ =20 int amd_viommu_init(struct amd_iommu *iommu); =20 +u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, u16 gid); #else =20 static inline int amd_viommu_init(struct amd_iommu *iommu) @@ -17,6 +18,10 @@ static inline int amd_viommu_init(struct amd_iommu *iomm= u) return 0; } =20 +u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, u16 gid); +{ + return 0; +} #endif /* CONFIG_AMD_IOMMU_IOMMUFD */ =20 #endif /* AMD_VIOMMU_H */ diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 6fba5d9b1310..5dcd3fc3ba99 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -7,6 +7,7 @@ =20 #include "iommufd.h" #include "amd_iommu.h" +#include "amd_viommu.h" #include "amd_iommu_types.h" =20 static const struct iommufd_viommu_ops amd_viommu_ops; @@ -44,9 +45,11 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viomm= u, struct iommu_domain * const struct iommu_user_data *user_data) { int ret; + phys_addr_t page_base; unsigned long flags; struct iommu_viommu_amd data; struct protection_domain *pdom =3D to_pdomain(parent); + struct amd_iommu *iommu =3D container_of(viommu->iommu_dev, struct amd_io= mmu, iommu); struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); =20 xa_init_flags(&aviommu->gdomid_array, XA_FLAGS_ALLOC1); @@ -66,11 +69,21 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viom= mu, struct iommu_domain * return aviommu->gid; pr_debug("%s: gid=3D%#x", __func__, aviommu->gid); =20 + page_base =3D amd_viommu_get_vfmmio_addr(iommu, aviommu->gid); + if (page_base <=3D 0) + return -ENODEV; + + ret =3D iommufd_viommu_alloc_mmap(&aviommu->core, + page_base, SZ_4K, + (unsigned long *)&data.out_vfmmio_mmap_offset); + if (ret) + goto err_out; + ret =3D iommu_copy_struct_to_user(user_data, &data, IOMMU_VIOMMU_TYPE_AMD, reserved); if (ret) - goto err_out; + goto free_mmap; =20 viommu->ops =3D &amd_viommu_ops; =20 @@ -79,6 +92,8 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu= , struct iommu_domain * spin_unlock_irqrestore(&pdom->lock, flags); =20 return 0; +free_mmap: + iommufd_viommu_destroy_mmap(&aviommu->core, data.out_vfmmio_mmap_offset); err_out: amd_iommu_gid_free(aviommu->gid); return ret; diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 887a9eb8122d..76198bf4f4f6 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -92,6 +92,17 @@ static int __init viommu_vf_vfcntl_init(struct amd_iommu= *iommu) return 0; } =20 +/* + * Returns VF MMIO BAR offset for the give guest ID which will be + * mapped to guest vIOMMU 3rd 4K MMIO address + */ +u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, u16 gid) +{ + /* TODO: Add check for sVIOMMU and set gid[bit 15] */ + return iommu->vf_base_phys + gid * VIOMMU_VF_MMIO_ENTRY_SIZE; +} +EXPORT_SYMBOL(amd_viommu_get_vfmmio_addr); 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Mon, 30 Mar 2026 03:43:14 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 08/22] iommu/amd: Introduce Reset vMMIO Command Date: Mon, 30 Mar 2026 08:41:52 +0000 Message-ID: <20260330084206.9251-9-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> References: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017093:EE_|CY5PR12MB9054:EE_ X-MS-Office365-Filtering-Correlation-Id: 34521e2d-16d7-4af7-c37c-08de8e3864aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|56012099003|22082099003|18002099003; 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charset="utf-8" Introduce new IOMMU commands for vIOMMU to reset virtualized MMIO registers of a particular guest. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 1 + drivers/iommu/amd/iommu.c | 22 ++++++++++++++++++++++ drivers/iommu/amd/iommufd.c | 3 +++ 4 files changed, 27 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 470e5d98c52b..f1fafa21777d 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -11,6 +11,7 @@ =20 #include "amd_iommu_types.h" =20 +void iommu_reset_vmmio(struct amd_iommu *iommu, u16 gid); irqreturn_t amd_iommu_int_thread(int irq, void *data); irqreturn_t amd_iommu_int_thread_evtlog(int irq, void *data); irqreturn_t amd_iommu_int_thread_pprlog(int irq, void *data); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index f0e18a7dd7f2..53854a4f4307 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -221,6 +221,7 @@ #define CMD_INV_IRT 0x05 #define CMD_COMPLETE_PPR 0x07 #define CMD_INV_ALL 0x08 +#define CMD_RESET_VMMIO 0x0A =20 #define CMD_COMPL_WAIT_STORE_MASK 0x01 #define CMD_COMPL_WAIT_INT_MASK 0x02 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 037a50397f31..191a52b657c1 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1429,6 +1429,18 @@ static void build_inv_irt(struct iommu_cmd *cmd, u16= devid) CMD_SET_TYPE(cmd, CMD_INV_IRT); } =20 +static void build_reset_vmmio(struct iommu_cmd *cmd, u16 gid, + bool vcmd, bool all) +{ + memset(cmd, 0, sizeof(*cmd)); + cmd->data[0] =3D gid; + if (all) + cmd->data[0] |=3D (1 << 28); + if (vcmd) + cmd->data[0] |=3D (1 << 31); + CMD_SET_TYPE(cmd, CMD_RESET_VMMIO); +} + /* * Writes the command to the IOMMUs command buffer and informs the * hardware about the new command. @@ -1663,6 +1675,16 @@ void amd_iommu_flush_all_caches(struct amd_iommu *io= mmu) } } =20 +void iommu_reset_vmmio(struct amd_iommu *iommu, u16 gid) +{ + struct iommu_cmd cmd; + + build_reset_vmmio(&cmd, gid, 1, 1); + + iommu_queue_command(iommu, &cmd); + amd_iommu_completion_wait(iommu); +} + /* * Command send function for flushing on-device TLB */ diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 5dcd3fc3ba99..06d6aa87cdcd 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -79,6 +79,9 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu= , struct iommu_domain * if (ret) goto err_out; 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charset="utf-8" AMD vIOMMU introduces the IOMMU Private Address (IPA) region, which is used to manage data structures necessary for IOMMU virtualization within the guest. Introduce a new domain specifically for IPA region for each IOMMU, which is stored in struct amd_iommu.viommu_pdom. This domain uses AMD IOMMU v1 page table. For more info, please see section vIOMMU Private Address Space of the IOMMU specification [1]. [1] https://docs.amd.com/v/u/en-US/48882_3.10_PUB Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 3 ++ drivers/iommu/amd/amd_iommu_types.h | 3 ++ drivers/iommu/amd/iommu.c | 6 +-- drivers/iommu/amd/viommu.c | 76 +++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index f1fafa21777d..ad88c4118719 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -28,6 +28,7 @@ void iommu_feature_enable(struct amd_iommu *iommu, u8 bit= ); void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); +int iommu_flush_dte(struct amd_iommu *iommu, u16 devid); =20 #ifdef CONFIG_AMD_IOMMU_DEBUGFS void amd_iommu_debugfs_setup(void); @@ -36,6 +37,8 @@ static inline void amd_iommu_debugfs_setup(void) {} #endif =20 extern bool amd_iommu_viommu; +extern const struct pt_iommu_driver_ops amd_hw_driver_ops_v1; +extern const struct iommu_domain_ops amdv1_ops; =20 /* Needed for interrupt remapping */ int amd_iommu_prepare(void); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 53854a4f4307..36ca9003dd88 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -807,6 +807,9 @@ struct amd_iommu { /* IOPF support */ struct iopf_queue *iopf_queue; unsigned char iopfq_name[32]; + + /* HW vIOMMU support */ + struct protection_domain *viommu_pdom; }; =20 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 191a52b657c1..07a0314a3fdc 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1546,7 +1546,7 @@ static void domain_flush_complete(struct protection_d= omain *domain) amd_iommu_completion_wait(pdom_iommu_info->iommu); } =20 -static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) +int iommu_flush_dte(struct amd_iommu *iommu, u16 devid) { struct iommu_cmd cmd; =20 @@ -2720,12 +2720,12 @@ static void amd_iommu_iotlb_sync(struct iommu_domai= n *domain, iommu_put_pages_list(&gather->freelist); } =20 -static const struct pt_iommu_driver_ops amd_hw_driver_ops_v1 =3D { +const struct pt_iommu_driver_ops amd_hw_driver_ops_v1 =3D { .get_top_lock =3D amd_iommu_get_top_lock, .change_top =3D amd_iommu_change_top, }; =20 -static const struct iommu_domain_ops amdv1_ops =3D { +const struct iommu_domain_ops amdv1_ops =3D { IOMMU_PT_DOMAIN_OPS(amdv1), .iotlb_sync_map =3D amd_iommu_iotlb_sync_map, .flush_iotlb_all =3D amd_iommu_flush_iotlb_all, diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 76198bf4f4f6..2a6339076c6e 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -92,6 +92,78 @@ static int __init viommu_vf_vfcntl_init(struct amd_iommu= *iommu) return 0; } =20 +static struct iommu_domain * +viommu_domain_alloc(struct amd_iommu *iommu) +{ + int ret; + struct pt_iommu_amdv1_cfg cfg =3D {}; + struct protection_domain *domain; + + domain =3D protection_domain_alloc(); + if (!domain) + return NULL; + + domain->pd_mode =3D PD_MODE_V1; + domain->iommu.driver_ops =3D &amd_hw_driver_ops_v1; + domain->iommu.nid =3D dev_to_node(&iommu->dev->dev); + + cfg.common.features =3D BIT(PT_FEAT_DYNAMIC_TOP) | + BIT(PT_FEAT_AMDV1_ENCRYPT_TABLES) | + BIT(PT_FEAT_AMDV1_FORCE_COHERENCE); + cfg.common.features |=3D BIT(PT_FEAT_FLUSH_RANGE); + cfg.common.hw_max_vasz_lg2 =3D + min(64, (amd_iommu_hpt_level - 1) * 9 + 21); + cfg.common.hw_max_oasz_lg2 =3D 52; + cfg.starting_level =3D 2; + domain->domain.ops =3D &amdv1_ops; + + ret =3D pt_iommu_amdv1_init(&domain->amdv1, &cfg, GFP_KERNEL); + if (ret) { + amd_iommu_domain_free(&domain->domain); + return ERR_PTR(ret); + } + + /* + * Narrow the supported page sizes to those selected by the kernel + * command line. + */ + domain->domain.pgsize_bitmap &=3D amd_iommu_pgsize_bitmap; + domain->domain.type =3D IOMMU_DOMAIN_UNMANAGED; + + return &domain->domain; +} + +static int viommu_private_space_init(struct amd_iommu *iommu) +{ + struct iommu_domain *dom; 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charset="utf-8" By setting the domain ID, pagetable mode, and IOMMU v1 page table in the IOMMU Device Table Entry (DTE) indexed using the device ID of the AMD IOMMU. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/viommu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 2a6339076c6e..b7881de0b61e 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -175,6 +175,35 @@ u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu= , u16 gid) } EXPORT_SYMBOL(amd_viommu_get_vfmmio_addr); =20 +/* Set DTE for IOMMU device */ +static void set_iommu_dte(struct amd_iommu *iommu) +{ + u64 dte0, dte1; + u16 devid =3D iommu->devid; + struct pt_iommu_amdv1_hw_info pt_info; + struct protection_domain *pdom =3D iommu->viommu_pdom; + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + + pt_iommu_amdv1_hw_info(&pdom->amdv1, &pt_info); + + pr_debug("%s: host_pt_root=3D%#llx, mode=3D%#x\n", + __func__, pt_info.host_pt_root, pt_info.mode); + + dte0 =3D FIELD_PREP(DTE_HOST_TRP, pt_info.host_pt_root >> 12); + dte0 |=3D (pt_info.mode & DEV_ENTRY_MODE_MASK) << DEV_ENTRY_MODE_SHIFT; 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charset="utf-8" The AMD IOMMU Private Address (IPA) region is allocated and mapped during IOMMU driver initialization. According to the specification, 8MB is needed. Since the hardware does not require the IPA region to be physically contiguous, split the IPA region into 4 2MB subregions to match hugepage granularity and create mapping in the v1 page-table for each IOMMU. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 3 ++ drivers/iommu/amd/amd_iommu_types.h | 8 ++++ drivers/iommu/amd/iommu.c | 16 ++++++++ drivers/iommu/amd/viommu.c | 57 ++++++++++++++++++++++++++++- 4 files changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index ad88c4118719..9bf07887b044 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -100,6 +100,9 @@ void amd_iommu_domain_flush_pages(struct protection_dom= ain *domain, void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data, ioasid_t pasid, u64 address, size_t size); =20 +int amd_iommu_flush_private_vm_region(struct amd_iommu *iommu, struct prot= ection_domain *pdom, + u64 address, size_t size); + #ifdef CONFIG_IRQ_REMAP int amd_iommu_create_irq_domain(struct amd_iommu *iommu); #else diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 36ca9003dd88..2d96c72ba45f 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -423,6 +423,13 @@ /* For vIOMMU, the GID is 16-bit. */ #define VIOMMU_MAX_GID 0xFFFF =20 +/* + * Total IOMMU private region is 8MB (4 x 2MB-subregion) + */ +#define VIOMMU_PRIV_REGION_BASE (0) +#define VIOMMU_PRIV_SUBREGION_CNT (4) +#define VIOMMU_PRIV_SUBREGION_SIZE (0x200000) /* 2MB */ + /* Timeout stuff */ #define LOOP_TIMEOUT 100000 #define MMIO_STATUS_TIMEOUT 2000000 @@ -810,6 +817,7 @@ struct amd_iommu { =20 /* HW vIOMMU support */ struct protection_domain *viommu_pdom; + void *viommu_priv_region[VIOMMU_PRIV_SUBREGION_CNT]; }; =20 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 07a0314a3fdc..8143cf03dcc1 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -1803,6 +1803,22 @@ static int domain_flush_pages_v1(struct protection_d= omain *pdom, return ret; } =20 +int amd_iommu_flush_private_vm_region(struct amd_iommu *iommu, struct prot= ection_domain *pdom, + u64 address, size_t size) +{ + int ret; + struct iommu_cmd cmd; + + build_inv_iommu_pages(&cmd, address, size, pdom->id, 0, false); + + ret =3D iommu_queue_command(iommu, &cmd); + if (ret) + return ret; + + amd_iommu_completion_wait(iommu); + return ret; +} + /* * TLB invalidation function which is called from the mapping functions. * It flushes range of PTEs of the domain. diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index b7881de0b61e..27179d5087bc 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -133,8 +133,44 @@ viommu_domain_alloc(struct amd_iommu *iommu) return &domain->domain; } =20 +static void *alloc_private_subregion(struct amd_iommu *iommu, u64 base, si= ze_t size) +{ + int ret; + void *region; + size_t mapped; + int nid =3D iommu && iommu->dev ? dev_to_node(&iommu->dev->dev) : NUMA_NO= _NODE; + + region =3D (void *)iommu_alloc_pages_node_sz(nid, GFP_KERNEL | __GFP_ZERO= , size); + if (!region) + return NULL; + + ret =3D set_memory_uc((unsigned long)region, size >> PAGE_SHIFT); + if (ret) + goto err_out; + + ret =3D pt_iommu_amdv1_map_pages(&iommu->viommu_pdom->domain, base, + iommu_virt_to_phys(region), PAGE_SIZE, (size / PAGE_SIZE), + IOMMU_PROT_IR | IOMMU_PROT_IW, GFP_KERNEL, &mapped); + + if (ret) + goto err_out; + + pr_debug("%s: base=3D%#llx, size=3D%#lx, subregion=3D%#llx(%#llx)\n", + __func__, base, size, (unsigned long long)region, iommu_virt_to_phys(re= gion)); + + amd_iommu_flush_private_vm_region(iommu, iommu->viommu_pdom, base, size); + + return region; + +err_out: + free_pages((unsigned long)region, get_order(size)); + return NULL; +} + static int viommu_private_space_init(struct amd_iommu *iommu) { + int i; + u64 base; struct iommu_domain *dom; struct protection_domain *pdom; struct pt_iommu_amdv1_hw_info pt_info; @@ -146,12 +182,26 @@ static int viommu_private_space_init(struct amd_iommu= *iommu) dom =3D viommu_domain_alloc(iommu); if (!dom) { pr_err("%s: Failed to initialize private space\n", __func__); - goto err_out; + return -ENOMEM; } =20 pdom =3D to_pdomain(dom); iommu->viommu_pdom =3D pdom; =20 + /* + * Each private region requires to 8MB of memory to be allocated + * and mapped. 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charset="utf-8" Some parts of vIOMMU Private Address (IPA) region (i.e. Guest Device ID mappng and Guest Domain ID mapping) are managed per-VM during VM create and destroy. Introduce helper functions to allocate and map, free and upmap per-VM IPA region. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 2 ++ drivers/iommu/amd/iommu.c | 4 +-- drivers/iommu/amd/nested.c | 1 + drivers/iommu/amd/viommu.c | 52 +++++++++++++++++++++++++++++++++++ 4 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 9bf07887b044..b5a54617a9a1 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -100,6 +100,8 @@ void amd_iommu_domain_flush_pages(struct protection_dom= ain *domain, void amd_iommu_dev_flush_pasid_pages(struct iommu_dev_data *dev_data, ioasid_t pasid, u64 address, size_t size); =20 +void amd_iommu_iotlb_sync(struct iommu_domain *domain, + struct iommu_iotlb_gather *gather); int amd_iommu_flush_private_vm_region(struct amd_iommu *iommu, struct prot= ection_domain *pdom, u64 address, size_t size); =20 diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8143cf03dcc1..4be3589b9393 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -2723,8 +2723,8 @@ static void amd_iommu_flush_iotlb_all(struct iommu_do= main *domain) spin_unlock_irqrestore(&dom->lock, flags); } =20 -static void amd_iommu_iotlb_sync(struct iommu_domain *domain, - struct iommu_iotlb_gather *gather) +void amd_iommu_iotlb_sync(struct iommu_domain *domain, + struct iommu_iotlb_gather *gather) { struct protection_domain *dom =3D to_pdomain(domain); unsigned long flags; diff --git a/drivers/iommu/amd/nested.c b/drivers/iommu/amd/nested.c index 66cc36133c8b..c210b8003fd5 100644 --- a/drivers/iommu/amd/nested.c +++ b/drivers/iommu/amd/nested.c @@ -291,4 +291,5 @@ static void nested_domain_free(struct iommu_domain *dom) static const struct iommu_domain_ops nested_domain_ops =3D { .attach_dev =3D nested_attach_device, .free =3D nested_domain_free, + .iotlb_sync =3D amd_iommu_iotlb_sync, }; diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 27179d5087bc..fbc6b37b2517 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -283,3 +283,55 @@ int __init amd_viommu_init(struct amd_iommu *iommu) =20 return 0; } + +static int alloc_private_vm_region(struct amd_iommu *iommu, u64 **entry, + u64 base, size_t size, u16 gid) +{ + int ret; + size_t mapped; + u64 addr =3D base + (gid * size); + int nid =3D iommu && iommu->dev ? dev_to_node(&iommu->dev->dev) : NUMA_NO= _NODE; + + *entry =3D (void *)iommu_alloc_pages_node_sz(nid, GFP_KERNEL | __GFP_ZERO= , size); + if (!*entry) + return -ENOMEM; + + ret =3D set_memory_uc((unsigned long)*entry, size >> PAGE_SHIFT); + if (ret) + return ret; + + pr_debug("%s: entry=3D%#llx(%#llx), addr=3D%#llx, size=3D%#lx\n", __func_= _, + (unsigned long long)*entry, iommu_virt_to_phys(*entry), addr, size); + + ret =3D pt_iommu_amdv1_map_pages(&iommu->viommu_pdom->domain, addr, + iommu_virt_to_phys(*entry), PAGE_SIZE, (size / PAGE_SIZE), + IOMMU_PROT_IR | IOMMU_PROT_IW, GFP_KERNEL, &mapped); + if (ret) + return ret; + + return amd_iommu_flush_private_vm_region(iommu, iommu->viommu_pdom, addr,= size); +} + +static void free_private_vm_region(struct amd_iommu *iommu, u64 **entry, + u64 base, size_t size, u16 gid) +{ + size_t ret; + struct iommu_iotlb_gather gather; + u64 addr =3D base + (gid * size); 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charset="utf-8" Introduce amd_viommu_init_one() and amd_viommu_uninit_one(). These functions are called during IOMMUFD vIOMMU initialize and destroy. Currently, it manages the IPA mapping for Device ID and Domain ID mapping tables. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 3 ++ drivers/iommu/amd/amd_viommu.h | 15 +++++++++ drivers/iommu/amd/iommu.c | 1 + drivers/iommu/amd/iommufd.c | 5 +++ drivers/iommu/amd/viommu.c | 52 +++++++++++++++++++++++++++++ 5 files changed, 76 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 2d96c72ba45f..fda7109766f3 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -543,6 +543,9 @@ struct amd_iommu_viommu { * Indexed by guest domain ID. */ struct xarray gdomid_array; + + u64 *devid_table; + u64 *domid_table; }; =20 /* diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h index 8dbb12241e8d..ccdd1cbcec36 100644 --- a/drivers/iommu/amd/amd_viommu.h +++ b/drivers/iommu/amd/amd_viommu.h @@ -11,6 +11,11 @@ int amd_viommu_init(struct amd_iommu *iommu); =20 u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, u16 gid); + +int amd_viommu_init_one(struct amd_iommu *iommu, struct amd_iommu_viommu *= viommu); + +void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viomm= u *viommu); + #else =20 static inline int amd_viommu_init(struct amd_iommu *iommu) @@ -22,6 +27,16 @@ u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, = u16 gid); { return 0; } + +static inline int amd_viommu_init_one(struct amd_iommu *iommu, struct amd_= iommu_viommu *viommu) +{ + return -EOPNOTSUPP; +} + +static inline void amd_viommu_uninit_one(struct amd_iommu *iommu, struct a= md_iommu_viommu *viommu) +{ +} + #endif /* CONFIG_AMD_IOMMU_IOMMUFD */ =20 #endif /* AMD_VIOMMU_H */ diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4be3589b9393..8d8f4f374d5f 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -43,6 +43,7 @@ #include =20 #include "amd_iommu.h" +#include "amd_viommu.h" #include "iommufd.h" #include "../irq_remapping.h" #include "../iommu-pages.h" diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 06d6aa87cdcd..c2281557b3bf 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -82,6 +82,10 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viomm= u, struct iommu_domain * /* Reset vIOMMU MMIOs to initialize the vIOMMU */ iommu_reset_vmmio(iommu, aviommu->gid); =20 + ret =3D amd_viommu_init_one(iommu, aviommu); + if (ret) + goto err_out; + ret =3D iommu_copy_struct_to_user(user_data, &data, IOMMU_VIOMMU_TYPE_AMD, reserved); @@ -116,6 +120,7 @@ static void amd_iommufd_viommu_destroy(struct iommufd_v= iommu *viommu) spin_unlock_irqrestore(&pdom->lock, flags); xa_destroy(&aviommu->gdomid_array); amd_iommu_gid_free(aviommu->gid); + amd_viommu_uninit_one(iommu, aviommu); } =20 /* diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index fbc6b37b2517..53cf6ab2db04 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -26,6 +26,20 @@ #include "amd_viommu.h" #include "../iommu-pages.h" =20 +/* + * Guest Device ID Mapping Table + */ +#define VIOMMU_MAX_GDEVID 0xFFFF +#define VIOMMU_DEVID_MAPPING_BASE 0x1000000000ULL +#define VIOMMU_DEVID_MAPPING_ENTRY_SIZE (1 << 20) + +/* + * Guest Domain ID Mapping Table + */ +#define VIOMMU_MAX_GDOMID 0xFFFF +#define VIOMMU_DOMID_MAPPING_BASE 0x2000000000ULL +#define VIOMMU_DOMID_MAPPING_ENTRY_SIZE (1 << 19) + LIST_HEAD(viommu_devid_map); =20 static int viommu_init_pci_vsc(struct amd_iommu *iommu) @@ -335,3 +349,41 @@ static void free_private_vm_region(struct amd_iommu *i= ommu, u64 **entry, iommu_free_pages(*entry); *entry =3D NULL; } + +void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viomm= u *aviommu) +{ + pr_debug("%s: gid=3D%u\n", __func__, aviommu->gid); + + free_private_vm_region(iommu, &aviommu->devid_table, + VIOMMU_DEVID_MAPPING_BASE, + VIOMMU_DEVID_MAPPING_ENTRY_SIZE, + aviommu->gid); + free_private_vm_region(iommu, &aviommu->domid_table, + VIOMMU_DOMID_MAPPING_BASE, + VIOMMU_DOMID_MAPPING_ENTRY_SIZE, + aviommu->gid); +} + +int amd_viommu_init_one(struct amd_iommu *iommu, struct amd_iommu_viommu *= viommu) +{ + int ret; + + ret =3D alloc_private_vm_region(iommu, &viommu->devid_table, + VIOMMU_DEVID_MAPPING_BASE, + VIOMMU_DEVID_MAPPING_ENTRY_SIZE, + viommu->gid); + if (ret) + goto err_out; + + ret =3D alloc_private_vm_region(iommu, &viommu->domid_table, + VIOMMU_DOMID_MAPPING_BASE, + VIOMMU_DOMID_MAPPING_ENTRY_SIZE, + viommu->gid); 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charset="utf-8" Initialize vDevice for AMD vIOMMU by setting up the Device ID Mapping table using the guest device ID. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 12 +++++++++++ drivers/iommu/amd/iommufd.c | 33 +++++++++++++++++++++++++++++ drivers/iommu/amd/nested.c | 12 +++++++++++ 3 files changed, 57 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index fda7109766f3..c50ba5cda82d 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -386,6 +386,11 @@ #define DTE_GPT_LEVEL_SHIFT 54 #define DTE_GPT_LEVEL_MASK GENMASK_ULL(55, 54) =20 +/* vIOMMU bit fields */ +#define DTE_VIOMMU_EN_SHIFT 15 +#define DTE_VIOMMU_GDEVICEID_MASK GENMASK_ULL(31, 16) +#define DTE_VIOMMU_GUESTID_MASK GENMASK_ULL(47, 32) + #define GCR3_VALID 0x01ULL =20 /* DTE[128:179] | DTE[184:191] */ @@ -887,6 +892,9 @@ struct iommu_dev_data { bool defer_attach; =20 struct ratelimit_state rs; /* Ratelimit IOPF messages */ + + u16 gid; /* Guest ID */ + u16 gDevId; /* Guest Device ID */ }; =20 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ @@ -1113,6 +1121,10 @@ struct amd_irte_ops { void (*clear_allocated)(struct irq_remap_table *, int); }; =20 +struct amd_iommu_vdevice { + struct iommufd_vdevice core; +}; + #ifdef CONFIG_IRQ_REMAP extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index c2281557b3bf..a047bb45aa14 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -9,6 +9,7 @@ #include "amd_iommu.h" #include "amd_viommu.h" #include "amd_iommu_types.h" +#include "../iommufd/iommufd_private.h" =20 static const struct iommufd_viommu_ops amd_viommu_ops; =20 @@ -123,6 +124,36 @@ static void amd_iommufd_viommu_destroy(struct iommufd_= viommu *viommu) amd_viommu_uninit_one(iommu, aviommu); } =20 +/* + * Called from drivers/iommu/iommufd/viommu.c: iommufd_vdevice_alloc_ioctl= () + */ +static int _amd_viommu_vdevice_init(struct iommufd_vdevice *vdev) +{ + struct iommu_dev_data *dev_data; + struct pci_dev *pdev =3D to_pci_dev(vdev->idev->dev); + struct iommufd_viommu *viommu =3D vdev->viommu; + struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); + + if (!pdev) { + pr_err(); + return -EINVAL; + } + + dev_data =3D dev_iommu_priv_get(&pdev->dev); + if (!dev_data) { + pr_err("%s: Device not found (devid=3D%#x)\n", + __func__, pci_dev_id(pdev)); + return -EINVAL; + } + + dev_data->gid =3D aviommu->gid; + dev_data->gDevId =3D vdev->virt_id; + pr_debug("%s: gid=3D%#x, hdev_id=3D%#x, gdev_id=3D%#x\n", __func__, + dev_data->gid, pci_dev_id(pdev), dev_data->gDevId); + + return 0; +} + /* * See include/linux/iommufd.h * struct iommufd_viommu_ops - vIOMMU specific operations @@ -130,4 +161,6 @@ static void amd_iommufd_viommu_destroy(struct iommufd_v= iommu *viommu) static const struct iommufd_viommu_ops amd_viommu_ops =3D { .alloc_domain_nested =3D amd_iommu_alloc_domain_nested, .destroy =3D amd_iommufd_viommu_destroy, + .vdevice_size =3D VDEVICE_STRUCT_SIZE(struct amd_iommu_vdevice, core), + .vdevice_init =3D _amd_viommu_vdevice_init, }; diff --git a/drivers/iommu/amd/nested.c b/drivers/iommu/amd/nested.c index c210b8003fd5..70af39da9360 100644 --- a/drivers/iommu/amd/nested.c +++ b/drivers/iommu/amd/nested.c @@ -227,6 +227,18 @@ static void set_dte_nested(struct amd_iommu *iommu, st= ruct iommu_domain *dom, =20 /* Guest paging mode */ new->data[2] |=3D gdte->dte[2] & DTE_GPT_LEVEL_MASK; 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charset="utf-8" AMD vIOMMU hardware uses the Domain ID mapping table to map Guest Domain ID (GDomID) to Host Domain ID when it virtualises guest IOMMU commands. It uses GID and GDomID to index into the table to look up host domain ID. Linux IOMMU driver programs the table entry using VFCntlMMIO Guest Domain Map Control Register. Introduce amd_viommu_domain_id_update(), which is used to set the entry when attaching the nested device. Clearing the entry is done during VM destroy. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_viommu.h | 2 ++ drivers/iommu/amd/nested.c | 5 ++++ drivers/iommu/amd/viommu.c | 42 ++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h index ccdd1cbcec36..e1387d9ea97d 100644 --- a/drivers/iommu/amd/amd_viommu.h +++ b/drivers/iommu/amd/amd_viommu.h @@ -16,6 +16,8 @@ int amd_viommu_init_one(struct amd_iommu *iommu, struct a= md_iommu_viommu *viommu =20 void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viomm= u *viommu); =20 +int amd_viommu_domain_id_update(struct amd_iommu *iommu, u16 gid, + u16 hdom_id, u16 gdom_id); #else =20 static inline int amd_viommu_init(struct amd_iommu *iommu) diff --git a/drivers/iommu/amd/nested.c b/drivers/iommu/amd/nested.c index 70af39da9360..f38813394a25 100644 --- a/drivers/iommu/amd/nested.c +++ b/drivers/iommu/amd/nested.c @@ -10,6 +10,7 @@ #include =20 #include "amd_iommu.h" +#include "amd_viommu.h" =20 static const struct iommu_domain_ops nested_domain_ops; =20 @@ -245,6 +246,7 @@ static int nested_attach_device(struct iommu_domain *do= m, struct device *dev, struct iommu_domain *old) { struct dev_table_entry new =3D {0}; + struct nested_domain *ndom =3D to_ndomain(dom); struct iommu_dev_data *dev_data =3D dev_iommu_priv_get(dev); struct amd_iommu *iommu =3D get_amd_iommu_from_dev_data(dev_data); int ret =3D 0; @@ -262,6 +264,9 @@ static int nested_attach_device(struct iommu_domain *do= m, struct device *dev, =20 amd_iommu_update_dte(iommu, dev_data, &new); =20 + ret =3D amd_viommu_domain_id_update(iommu, dev_data->gid, + ndom->gdom_info->hdom_id, ndom->gdom_id); + mutex_unlock(&dev_data->mutex); =20 return ret; diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 53cf6ab2db04..80873bd62c52 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -40,6 +40,8 @@ #define VIOMMU_DOMID_MAPPING_BASE 0x2000000000ULL #define VIOMMU_DOMID_MAPPING_ENTRY_SIZE (1 << 19) =20 +#define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET 0x08 + LIST_HEAD(viommu_devid_map); =20 static int viommu_init_pci_vsc(struct amd_iommu *iommu) @@ -350,6 +352,22 @@ static void free_private_vm_region(struct amd_iommu *i= ommu, u64 **entry, *entry =3D NULL; } =20 +static void viommu_clear_mapping(struct amd_iommu *iommu, + struct amd_iommu_viommu *aviommu) +{ + int i; + u16 gid =3D aviommu->gid; + + /* + * IOMMU hardware uses the domain ID mapping table to map gdom ID to hdom= ID. + * If the mapping does not exist, the hardware would generate error in th= e event log. + * Therefore, initialize all gdom ID entries to map to parent domain ID t= o prevent + * unknown mapping scenario. + */ + for (i =3D 0; i <=3D VIOMMU_MAX_GDOMID; i++) + amd_viommu_domain_id_update(iommu, gid, aviommu->parent->id, i); +} + void amd_viommu_uninit_one(struct amd_iommu *iommu, struct amd_iommu_viomm= u *aviommu) { pr_debug("%s: gid=3D%u\n", __func__, aviommu->gid); @@ -362,6 +380,7 @@ void amd_viommu_uninit_one(struct amd_iommu *iommu, str= uct amd_iommu_viommu *avi VIOMMU_DOMID_MAPPING_BASE, VIOMMU_DOMID_MAPPING_ENTRY_SIZE, aviommu->gid); + viommu_clear_mapping(iommu, aviommu); } =20 int amd_viommu_init_one(struct amd_iommu *iommu, struct amd_iommu_viommu *= viommu) @@ -382,8 +401,31 @@ int amd_viommu_init_one(struct amd_iommu *iommu, struc= t amd_iommu_viommu *viommu if (ret) goto err_out; =20 + viommu_clear_mapping(iommu, viommu); + return 0; err_out: amd_viommu_uninit_one(iommu, viommu); return -ENOMEM; } + +/* + * Program the DomID via VFCTRL registers + * This function will be called during VM init via VFIO. + */ +int amd_viommu_domain_id_update(struct amd_iommu *iommu, u16 gid, + u16 hdom_id, u16 gdom_id) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + tmp1 =3D gdom_id; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D hdom_id; + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001UL; + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET); + + return 0; +} +EXPORT_SYMBOL(amd_viommu_domain_id_update); --=20 2.34.1 From nobody Thu Apr 2 10:57:37 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012008.outbound.protection.outlook.com [40.107.200.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1BE6F2C08C8 for ; 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Mon, 30 Mar 2026 03:43:52 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 16/22] iommu/amd: Introduce helper function for updating device ID mapping table Date: Mon, 30 Mar 2026 08:42:00 +0000 Message-ID: <20260330084206.9251-17-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> References: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CD:EE_|DM4PR12MB7597:EE_ X-MS-Office365-Filtering-Correlation-Id: 159ce8ab-f19c-4ad3-d025-08de8e387f10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|376014|82310400026|1800799024|22082099003|18002099003|56012099003; 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charset="utf-8" AMD vIOMMU hardware uses the Device ID mapping table to map Guest Device ID (GDevID) to Host Device ID when it virtualises guest IOMMU commands. It uses GID and GDevID to indexe into the table to look up host device ID. Linux IOMMU driver programs the table entry using VFCntlMMIO Guest Device Map Control Register. Introduce amd_viommu_set/clear_device_mapping(), which are used to set the entry when initialize the IOMMUFD vDevice. Clearing the entry is done during VM destroy. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_viommu.h | 10 ++++++- drivers/iommu/amd/iommufd.c | 3 +++ drivers/iommu/amd/viommu.c | 48 ++++++++++++++++++++++++++++++++++ 3 files changed, 60 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h index e1387d9ea97d..93e44f8b6012 100644 --- a/drivers/iommu/amd/amd_viommu.h +++ b/drivers/iommu/amd/amd_viommu.h @@ -18,6 +18,9 @@ void amd_viommu_uninit_one(struct amd_iommu *iommu, struc= t amd_iommu_viommu *vio =20 int amd_viommu_domain_id_update(struct amd_iommu *iommu, u16 gid, u16 hdom_id, u16 gdom_id); + +void amd_viommu_set_device_mapping(struct amd_iommu *iommu, u16 hDevId, + u16 guestId, u16 gDevId); #else =20 static inline int amd_viommu_init(struct amd_iommu *iommu) @@ -25,7 +28,7 @@ static inline int amd_viommu_init(struct amd_iommu *iommu) return 0; } =20 -u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, u16 gid); +static inline u64 amd_viommu_get_vfmmio_addr(struct amd_iommu *iommu, u16 = gid); { return 0; } @@ -39,6 +42,11 @@ static inline void amd_viommu_uninit_one(struct amd_iomm= u *iommu, struct amd_iom { } =20 +static inline void amd_viommu_set_device_mapping(struct amd_iommu *iommu, = u16 hDevId, + u16 guestId, u16 gDevId) +{ +} + #endif /* CONFIG_AMD_IOMMU_IOMMUFD */ =20 #endif /* AMD_VIOMMU_H */ diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index a047bb45aa14..685748a71b22 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -133,6 +133,7 @@ static int _amd_viommu_vdevice_init(struct iommufd_vdev= ice *vdev) struct pci_dev *pdev =3D to_pci_dev(vdev->idev->dev); struct iommufd_viommu *viommu =3D vdev->viommu; struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); + struct amd_iommu *iommu =3D container_of(viommu->iommu_dev, struct amd_io= mmu, iommu); =20 if (!pdev) { pr_err(); @@ -151,6 +152,8 @@ static int _amd_viommu_vdevice_init(struct iommufd_vdev= ice *vdev) pr_debug("%s: gid=3D%#x, hdev_id=3D%#x, gdev_id=3D%#x\n", __func__, dev_data->gid, pci_dev_id(pdev), dev_data->gDevId); =20 + amd_viommu_set_device_mapping(iommu, pci_dev_id(pdev), dev_data->gid, dev= _data->gDevId); + return 0; } =20 diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 80873bd62c52..28fe92ad9771 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -40,6 +40,7 @@ #define VIOMMU_DOMID_MAPPING_BASE 0x2000000000ULL #define VIOMMU_DOMID_MAPPING_ENTRY_SIZE (1 << 19) =20 +#define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET 0x00 #define VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL1_OFFSET 0x08 =20 LIST_HEAD(viommu_devid_map); @@ -352,6 +353,49 @@ static void free_private_vm_region(struct amd_iommu *i= ommu, u64 **entry, *entry =3D NULL; } =20 +/* + * Program the DevID via VFCTRL registers + * This function will be called during VM init via VFIO. + */ +void amd_viommu_set_device_mapping(struct amd_iommu *iommu, u16 hDevId, + u16 guestId, u16 gDevId) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl; + + pr_debug("%s: iommu_devid=3D%#x, gid=3D%#x, hDevId=3D%#x, gDevId=3D%#x\n", + __func__, pci_dev_id(iommu->dev), guestId, hDevId, gDevId); + + tmp1 =3D gDevId; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D hDevId; + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001ULL; + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId); + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET); +} + +/* + * Clear the DevID via VFCTRL registers + * This function will be called during VM destroy via VFIO. + */ +static void clear_device_mapping(struct amd_iommu *iommu, u16 guestId, u16= gDevId) +{ + u64 val, tmp1, tmp2; + u8 __iomem *vfctrl; + + /* + * Clear the DevID in VFCTRL registers + */ + tmp1 =3D gDevId; + tmp1 =3D ((tmp1 & 0xFFFFULL) << 46); + tmp2 =3D 0; /* hDevId */ + tmp2 =3D ((tmp2 & 0xFFFFULL) << 14); + val =3D tmp1 | tmp2 | 0x8000000000000001ULL; + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, guestId); + writeq(val, vfctrl + VIOMMU_VFCTRL_GUEST_DID_MAP_CONTROL0_OFFSET); +} + static void viommu_clear_mapping(struct amd_iommu *iommu, struct amd_iommu_viommu *aviommu) { @@ -366,6 +410,10 @@ static void viommu_clear_mapping(struct amd_iommu *iom= mu, */ for (i =3D 0; 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charset="utf-8" AMD vIOMMU requires hypervisor to setup a special DTE to store GPA->SPA mapping for each VM. This is used to translate base addresses of guest IOMMU data structures (i.g. Command Buffer, Event Log, PPR Log) and the Completion-wait data store (as part of the Completion-wait command). In Linux kernel, this is referred as vIOMMU Translation DTE (TransDTE), which is unique per VM. (Note that all IOMMU instances within a PCI segment share the same Device Table.) The device ID for the TransDTE is referred to as TransDevID, which must be an unused PCI BDF and must be unique for each VM. Currently, TransDevID is specified by VMM, and passed to the IOMMU driver via struct iommu_viommu_amd during vIOMMU initialization. The driver programs the ID into the DeviceID field of the VFCntlMMIO Guest Miscellaneous Control Register. The register is cleared during VM destroy. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 8 +++++ drivers/iommu/amd/amd_iommu_types.h | 2 ++ drivers/iommu/amd/iommu.c | 51 +++++++++++++++++++++++++++++ drivers/iommu/amd/iommufd.c | 8 +++++ drivers/iommu/amd/viommu.c | 3 ++ include/uapi/linux/iommufd.h | 2 ++ 6 files changed, 74 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index b5a54617a9a1..38694ebdb083 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -209,8 +209,16 @@ void amd_iommu_set_dte_v1(struct iommu_dev_data *dev_d= ata, void amd_iommu_update_dte(struct amd_iommu *iommu, struct iommu_dev_data *dev_data, struct dev_table_entry *new); + int amd_iommu_completion_wait(struct amd_iommu *iommu); =20 +void amd_iommu_set_translate_dte(struct amd_iommu *iommu, u16 gid, + struct protection_domain *pdom, + u32 devid); +void amd_iommu_clear_translate_dte(struct amd_iommu *iommu, u16 gid, u32 d= evid); +void amd_iommu_update_vfctrl_mmio_translate_devid(struct amd_iommu *iommu, + u16 gid, u32 trans_devid); + static inline void amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table= _entry *new) { diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index c50ba5cda82d..2c4844b44caf 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -494,6 +494,7 @@ extern bool amdr_ivrs_remap_support; /* VIOMMU stuff */ #define VIOMMU_VF_MMIO_ENTRY_SIZE 4096 #define VIOMMU_VFCTRL_MMIO_ENTRY_SIZE 64 +#define VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET 0x10 =20 #define VIOMMU_VF_MMIO_BASE(iommu, guestId) \ (iommu->vf_base + (guestId * VIOMMU_VF_MMIO_ENTRY_SIZE)) @@ -551,6 +552,7 @@ struct amd_iommu_viommu { =20 u64 *devid_table; u64 *domid_table; + u16 trans_devid; }; =20 /* diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 8d8f4f374d5f..40a4dc219a84 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3224,6 +3224,57 @@ static bool amd_iommu_enforce_cache_coherency(struct= iommu_domain *domain) return true; } =20 +#if IS_ENABLED(CONFIG_AMD_IOMMU_IOMMUFD) + +void amd_iommu_update_vfctrl_mmio_translate_devid(struct amd_iommu *iommu, + u16 gid, u32 devid) +{ + writeq((devid & 0xFFFFULL) << 16, + VIOMMU_VFCTRL_MMIO_BASE(iommu, gid) + + VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET); +} + +void amd_iommu_set_translate_dte(struct amd_iommu *iommu, u16 gid, + struct protection_domain *pdom, + u32 devid) +{ + u64 tmp0 =3D 0ULL, tmp1 =3D 0ULL; + struct pt_iommu_amdv1_hw_info pt_info; + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + + pt_iommu_amdv1_hw_info(&pdom->amdv1, &pt_info); + + pr_debug("%s: gid=3D%#x, iommu_devid=3D%#x, devid=3D%#x, host_pt_root=3D%= #llx, mode=3D%#x\n", + __func__, gid, iommu->devid, devid, pt_info.host_pt_root, pt_info.mode); + + /* Setup DTE for v1 page table at the offset specified by devid */ + tmp0 |=3D FIELD_PREP(DTE_HOST_TRP, pt_info.host_pt_root >> 12); + tmp0 |=3D FIELD_PREP(DTE_MODE_MASK, pt_info.mode); + tmp0 |=3D (DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_TV | DTE_FLAG_V); + tmp1 |=3D FIELD_PREP(DTE_DOMID_MASK, pdom->id); + + dev_table[devid].data[0] =3D tmp0; + dev_table[devid].data[1] =3D tmp1; + + iommu_flush_dte(iommu, devid); + amd_iommu_completion_wait(iommu); +} + +void amd_iommu_clear_translate_dte(struct amd_iommu *iommu, u16 gid, u32 d= evid) +{ + struct dev_table_entry *dev_table =3D get_dev_table(iommu); + + pr_debug("%s: gid=3D%#x, iommu_devid=3D%#x, devid=3D%#x\n", + __func__, gid, iommu->devid, devid); + + dev_table[devid].data[0] =3D 0ULL; + dev_table[devid].data[1] =3D 0ULL; + + iommu_flush_dte(iommu, devid); + amd_iommu_completion_wait(iommu); +} +#endif /* CONFIG_AMD_IOMMU_IOMMUFD */ + const struct iommu_ops amd_iommu_ops =3D { .capable =3D amd_iommu_capable, .hw_info =3D amd_iommufd_hw_info, diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 685748a71b22..f83d69716eaa 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -83,6 +83,13 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viomm= u, struct iommu_domain * /* Reset vIOMMU MMIOs to initialize the vIOMMU */ iommu_reset_vmmio(iommu, aviommu->gid); =20 + amd_iommu_set_translate_dte(iommu, aviommu->gid, pdom, data.trans_devid); + + /* Set translate devid in vfctrl mmio */ + writeq((data.trans_devid & 0xFFFFULL) << 16, + VIOMMU_VFCTRL_MMIO_BASE(iommu, aviommu->gid) + + VIOMMU_VFCTRL_GUEST_MISC_CONTROL_OFFSET); + ret =3D amd_viommu_init_one(iommu, aviommu); if (ret) goto err_out; @@ -93,6 +100,7 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viomm= u, struct iommu_domain * if (ret) goto free_mmap; =20 + aviommu->trans_devid =3D data.trans_devid; viommu->ops =3D &amd_viommu_ops; =20 spin_lock_irqsave(&pdom->lock, flags); diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 28fe92ad9771..4626134893d6 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -428,6 +428,9 @@ void amd_viommu_uninit_one(struct amd_iommu *iommu, str= uct amd_iommu_viommu *avi VIOMMU_DOMID_MAPPING_BASE, VIOMMU_DOMID_MAPPING_ENTRY_SIZE, aviommu->gid); + + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0); 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Mon, 30 Mar 2026 03:44:01 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 18/22] iommufd: Introduce iommufd_viommu_ops.hw_queue_init Date: Mon, 30 Mar 2026 08:42:02 +0000 Message-ID: <20260330084206.9251-19-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> References: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D1:EE_|CY5PR12MB6645:EE_ X-MS-Office365-Filtering-Correlation-Id: c371c87e-f6c9-4bcd-408c-08de8e3888b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|56012099003|22082099003|18002099003; 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charset="utf-8" This is mainly used by AMD vIOMMU to initialize virtualize hardware queue using guest physical address where the address is specified via @hw_queue->base_addr. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/iommufd/viommu.c | 125 +++++++++++++++++++++++---------- include/linux/iommufd.h | 5 +- 2 files changed, 91 insertions(+), 39 deletions(-) diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c index 462b457ffd0c..59b31b3e36be 100644 --- a/drivers/iommu/iommufd/viommu.c +++ b/drivers/iommu/iommufd/viommu.c @@ -353,62 +353,35 @@ iommufd_hw_queue_alloc_phys(struct iommu_hw_queue_all= oc *cmd, return ERR_PTR(rc); } =20 -int iommufd_hw_queue_alloc_ioctl(struct iommufd_ucmd *ucmd) +static int _iommufd_hw_queue_init_phys(struct iommufd_ucmd *ucmd, + struct iommufd_viommu *viommu) { struct iommu_hw_queue_alloc *cmd =3D ucmd->cmd; struct iommufd_hw_queue *hw_queue; - struct iommufd_viommu *viommu; struct iommufd_access *access; size_t hw_queue_size; phys_addr_t base_pa; - u64 last; int rc; =20 - if (cmd->flags || cmd->type =3D=3D IOMMU_HW_QUEUE_TYPE_DEFAULT) - return -EOPNOTSUPP; - if (!cmd->length) - return -EINVAL; - if (check_add_overflow(cmd->nesting_parent_iova, cmd->length - 1, - &last)) - return -EOVERFLOW; - - viommu =3D iommufd_get_viommu(ucmd, cmd->viommu_id); - if (IS_ERR(viommu)) - return PTR_ERR(viommu); - - if (!viommu->ops || !viommu->ops->get_hw_queue_size || - !viommu->ops->hw_queue_init_phys) { - rc =3D -EOPNOTSUPP; - goto out_put_viommu; - } - hw_queue_size =3D viommu->ops->get_hw_queue_size(viommu, cmd->type); - if (!hw_queue_size) { - rc =3D -EOPNOTSUPP; - goto out_put_viommu; - } + if (!hw_queue_size) + return -EOPNOTSUPP; =20 /* * It is a driver bug for providing a hw_queue_size smaller than the * core HW queue structure size */ - if (WARN_ON_ONCE(hw_queue_size < sizeof(*hw_queue))) { - rc =3D -EOPNOTSUPP; - goto out_put_viommu; - } + if (WARN_ON_ONCE(hw_queue_size < sizeof(*hw_queue))) + return -EOPNOTSUPP; =20 hw_queue =3D (struct iommufd_hw_queue *)_iommufd_object_alloc_ucmd( ucmd, hw_queue_size, IOMMUFD_OBJ_HW_QUEUE); - if (IS_ERR(hw_queue)) { - rc =3D PTR_ERR(hw_queue); - goto out_put_viommu; - } + if (IS_ERR(hw_queue)) + return PTR_ERR(hw_queue); =20 access =3D iommufd_hw_queue_alloc_phys(cmd, viommu, &base_pa); - if (IS_ERR(access)) { - rc =3D PTR_ERR(access); - goto out_put_viommu; - } + if (IS_ERR(access)) + return PTR_ERR(access); =20 hw_queue->viommu =3D viommu; refcount_inc(&viommu->obj.users); @@ -419,9 +392,85 @@ int iommufd_hw_queue_alloc_ioctl(struct iommufd_ucmd *= ucmd) =20 rc =3D viommu->ops->hw_queue_init_phys(hw_queue, cmd->index, base_pa); if (rc) - goto out_put_viommu; + return rc; =20 cmd->out_hw_queue_id =3D hw_queue->obj.id; + return rc; +} + +static int _iommufd_hw_queue_init(struct iommufd_ucmd *ucmd, + struct iommufd_viommu *viommu) +{ + struct iommu_hw_queue_alloc *cmd =3D ucmd->cmd; + struct iommufd_hw_queue *hw_queue; + size_t hw_queue_size; + int rc; + + hw_queue_size =3D viommu->ops->get_hw_queue_size(viommu, cmd->type); + if (!hw_queue_size) + return -EOPNOTSUPP; + + /* + * It is a driver bug for providing a hw_queue_size smaller than the + * core HW queue structure size + */ + if (WARN_ON_ONCE(hw_queue_size < sizeof(*hw_queue))) + return -EOPNOTSUPP; + + hw_queue =3D (struct iommufd_hw_queue *)_iommufd_object_alloc_ucmd( + ucmd, hw_queue_size, IOMMUFD_OBJ_HW_QUEUE); + if (IS_ERR(hw_queue)) + return PTR_ERR(hw_queue); + + hw_queue->viommu =3D viommu; + refcount_inc(&viommu->obj.users); + hw_queue->access =3D NULL; + hw_queue->type =3D cmd->type; + hw_queue->length =3D cmd->length; + hw_queue->base_addr =3D cmd->nesting_parent_iova; + + rc =3D viommu->ops->hw_queue_init(hw_queue, cmd->index); + if (rc) + return rc; + + cmd->out_hw_queue_id =3D hw_queue->obj.id; + return rc; +} + +int iommufd_hw_queue_alloc_ioctl(struct iommufd_ucmd *ucmd) +{ + struct iommu_hw_queue_alloc *cmd =3D ucmd->cmd; + struct iommufd_viommu *viommu; + u64 last; + int rc; + + if (cmd->flags || cmd->type =3D=3D IOMMU_HW_QUEUE_TYPE_DEFAULT) + return -EOPNOTSUPP; + if (!cmd->length) + return -EINVAL; + if (check_add_overflow(cmd->nesting_parent_iova, cmd->length - 1, + &last)) + return -EOVERFLOW; + + viommu =3D iommufd_get_viommu(ucmd, cmd->viommu_id); + if (IS_ERR(viommu)) + return PTR_ERR(viommu); + + if (!viommu->ops || !viommu->ops->get_hw_queue_size) { + rc =3D -EOPNOTSUPP; + goto out_put_viommu; + } + + if (viommu->ops->hw_queue_init_phys) + rc =3D _iommufd_hw_queue_init_phys(ucmd, viommu); + else if (viommu->ops->hw_queue_init) + rc =3D _iommufd_hw_queue_init(ucmd, viommu); + else + rc =3D -EOPNOTSUPP; + + if (rc) + goto out_put_viommu; + rc =3D iommufd_ucmd_respond(ucmd, sizeof(*cmd)); =20 out_put_viommu: diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index 6e7efe83bc5d..c0030677e13c 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -180,6 +180,9 @@ struct iommufd_hw_queue { * the physical location of the guest queue * If driver has a deinit function to revert what thi= s op * does, it should set it to the @hw_queue->destroy p= ointer + * @hw_queue_init: Similar to hw_queue_init_phys, but driver providing thi= s op + * indicates that HW accesses the guest queue memory via + * @hw_queue->baseaddr. */ struct iommufd_viommu_ops { void (*destroy)(struct iommufd_viommu *viommu); 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charset="utf-8" AMD HW vIOMMU supports virtualizing Command buffer, Event log, and PPR log. Each can be initialized using the struct iommufd_viommu_ops.hw_queue_init to communicate base address (GPA) and length of each queue to the AMD IOMMU driver in order to programe the corresponded VF control MMIO registers. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 4 ++ drivers/iommu/amd/iommufd.c | 68 +++++++++++++++++++++++++++++ include/uapi/linux/iommufd.h | 3 ++ 3 files changed, 75 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 2c4844b44caf..1cd50a4008fb 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -1127,6 +1127,10 @@ struct amd_iommu_vdevice { struct iommufd_vdevice core; }; =20 +struct amd_iommu_hw_queue { + struct iommufd_hw_queue core; +}; + #ifdef CONFIG_IRQ_REMAP extern struct amd_irte_ops irte_32_ops; extern struct amd_irte_ops irte_128_ops; diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index f83d69716eaa..6f766254a390 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -165,6 +165,72 @@ static int _amd_viommu_vdevice_init(struct iommufd_vde= vice *vdev) return 0; } =20 +static size_t _amd_viommu_get_hw_queue_size(struct iommufd_viommu *viommu, + enum iommu_hw_queue_type queue_type) +{ + /* Currently do not support Eventlog B and PPRlog B */ + if ((queue_type !=3D IOMMU_HW_QUEUE_TYPE_AMD_CMD) && + (queue_type !=3D IOMMU_HW_QUEUE_TYPE_AMD_EVT) && + (queue_type !=3D IOMMU_HW_QUEUE_TYPE_AMD_PPR)) + return 0; + + return HW_QUEUE_STRUCT_SIZE(struct amd_iommu_hw_queue, core); +} + +static int _amd_viommu_hw_queue_init(struct iommufd_hw_queue *hw_queue, u3= 2 index) +{ + int ret =3D 0; + u64 val, tmp; + u8 __iomem *vfctrl, *vf; + struct iommufd_viommu *viommu =3D hw_queue->viommu; + struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); + struct amd_iommu *iommu =3D container_of(viommu->iommu_dev, struct amd_io= mmu, iommu); + int gid =3D aviommu->gid; + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (hw_queue->type) { + case IOMMU_HW_QUEUE_TYPE_AMD_CMD: + { + val =3D readq(vfctrl + 0x20); + val &=3D ~(0xFFFFFFFFFF00FULL); + tmp =3D (hw_queue->length & 0xFULL); + val =3D tmp | (hw_queue->base_addr & 0xFFFFFFFFFF000ULL); + + writeq(val, vfctrl + 0x20); + break; + } + case IOMMU_HW_QUEUE_TYPE_AMD_EVT: + { + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xFFFFFFFFFF00FULL); + tmp =3D (hw_queue->length & 0xFULL); + val =3D tmp | (hw_queue->base_addr & 0xFFFFFFFFFF000ULL); + writeq(val, vfctrl + 0x28); + break; + } + case IOMMU_HW_QUEUE_TYPE_AMD_PPR: + { + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xFFFFFFFFFF00FULL); + tmp =3D (hw_queue->length & 0xFULL); + val =3D tmp | ((hw_queue->base_addr & 0xFFFFFFFFFF000ULL) << 4); + writeq(val, vfctrl + 0x30); + break; + } + default: + pr_err("%s: Invalid type (%#x)\n", __func__, hw_queue->type); + return -EINVAL; + } + + pr_debug("%s: iommu_devid=3D%#x, gid=3D%#x, type=3D%#x, addr=3D%#llx, len= =3D%#lx, val=3D%#llx\n", + __func__, iommu->devid, gid, hw_queue->type, + hw_queue->base_addr, hw_queue->length, val); + + return ret; +} + /* * See include/linux/iommufd.h * struct iommufd_viommu_ops - vIOMMU specific operations @@ -174,4 +240,6 @@ static const struct iommufd_viommu_ops amd_viommu_ops = =3D { .destroy =3D amd_iommufd_viommu_destroy, .vdevice_size =3D VDEVICE_STRUCT_SIZE(struct amd_iommu_vdevice, core), .vdevice_init =3D _amd_viommu_vdevice_init, + .get_hw_queue_size =3D _amd_viommu_get_hw_queue_size, + .hw_queue_init =3D _amd_viommu_hw_queue_init, }; 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charset="utf-8" Introduce a new iommufd_option enum value, IOMMU_OPTION_VIOMMU, to support vIOMMU-specific options. Extend the existing IOMMU_OPTION ioctl to accept key-value style input, enabling access to data arrays such as hardware registers. Additionally, introduce struct iommufd_viommu_ops with set_option and get_option callbacks to support IOMMUFD vIOMMU options. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/iommufd/ioas.c | 2 +- drivers/iommu/iommufd/iommufd_private.h | 1 + drivers/iommu/iommufd/main.c | 6 +++--- drivers/iommu/iommufd/viommu.c | 18 ++++++++++++++++++ include/linux/iommufd.h | 5 +++++ include/uapi/linux/iommufd.h | 8 ++++++-- 6 files changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/iommufd/ioas.c b/drivers/iommu/iommufd/ioas.c index f4721afedadc..95547630fd3a 100644 --- a/drivers/iommu/iommufd/ioas.c +++ b/drivers/iommu/iommufd/ioas.c @@ -643,7 +643,7 @@ int iommufd_ioas_option(struct iommufd_ucmd *ucmd) struct iommufd_ioas *ioas; int rc =3D 0; =20 - if (cmd->__reserved) + if (cmd->key) return -EOPNOTSUPP; =20 ioas =3D iommufd_get_ioas(ucmd->ictx, cmd->object_id); diff --git a/drivers/iommu/iommufd/iommufd_private.h b/drivers/iommu/iommuf= d/iommufd_private.h index eb6d1a70f673..0306f2b8236f 100644 --- a/drivers/iommu/iommufd/iommufd_private.h +++ b/drivers/iommu/iommufd/iommufd_private.h @@ -698,6 +698,7 @@ void iommufd_vdevice_destroy(struct iommufd_object *obj= ); void iommufd_vdevice_abort(struct iommufd_object *obj); int iommufd_hw_queue_alloc_ioctl(struct iommufd_ucmd *ucmd); void iommufd_hw_queue_destroy(struct iommufd_object *obj); +int iommufd_viommu_option(struct iommufd_ucmd *ucmd); =20 static inline struct iommufd_vdevice * iommufd_get_vdevice(struct iommufd_ctx *ictx, u32 id) diff --git a/drivers/iommu/iommufd/main.c b/drivers/iommu/iommufd/main.c index 5cc4b08c25f5..ae36a6e8042d 100644 --- a/drivers/iommu/iommufd/main.c +++ b/drivers/iommu/iommufd/main.c @@ -391,9 +391,6 @@ static int iommufd_option(struct iommufd_ucmd *ucmd) struct iommu_option *cmd =3D ucmd->cmd; int rc; =20 - if (cmd->__reserved) - return -EOPNOTSUPP; - switch (cmd->option_id) { case IOMMU_OPTION_RLIMIT_MODE: rc =3D iommufd_option_rlimit_mode(cmd, ucmd->ictx); @@ -401,6 +398,9 @@ static int iommufd_option(struct iommufd_ucmd *ucmd) case IOMMU_OPTION_HUGE_PAGES: rc =3D iommufd_ioas_option(ucmd); break; + case IOMMU_OPTION_VIOMMU: + rc =3D iommufd_viommu_option(ucmd); + break; default: return -EOPNOTSUPP; } diff --git a/drivers/iommu/iommufd/viommu.c b/drivers/iommu/iommufd/viommu.c index 59b31b3e36be..51585337b8e4 100644 --- a/drivers/iommu/iommufd/viommu.c +++ b/drivers/iommu/iommufd/viommu.c @@ -477,3 +477,21 @@ int iommufd_hw_queue_alloc_ioctl(struct iommufd_ucmd *= ucmd) iommufd_put_object(ucmd->ictx, &viommu->obj); return rc; } + +int iommufd_viommu_option(struct iommufd_ucmd *ucmd) +{ + int ret =3D -EOPNOTSUPP; + struct iommu_option *cmd =3D ucmd->cmd; + struct iommufd_viommu *viommu =3D iommufd_get_viommu(ucmd, cmd->object_id= ); + + if (cmd->op =3D=3D IOMMU_OPTION_OP_SET) { + if (!viommu->ops->set_option) + return ret; + ret =3D viommu->ops->set_option(viommu, cmd->key, cmd->val64); + } else if (cmd->op =3D=3D IOMMU_OPTION_OP_GET) { + if (!viommu->ops->get_option) + return ret; + ret =3D viommu->ops->get_option(viommu, cmd->key, &cmd->val64); + } + return ret; +} diff --git a/include/linux/iommufd.h b/include/linux/iommufd.h index c0030677e13c..8096b7e59088 100644 --- a/include/linux/iommufd.h +++ b/include/linux/iommufd.h @@ -183,6 +183,9 @@ struct iommufd_hw_queue { * @hw_queue_init: Similar to hw_queue_init_phys, but driver providing thi= s op * indicates that HW accesses the guest queue memory via * @hw_queue->baseaddr. + * @set_option: Set the key-value option for the specified vIOMMU. + * @get_option: Get the key-value option for the specified vIOMMU. + * On success, the value is returned via the provided value. */ struct iommufd_viommu_ops { void (*destroy)(struct iommufd_viommu *viommu); @@ -198,6 +201,8 @@ struct iommufd_viommu_ops { int (*hw_queue_init_phys)(struct iommufd_hw_queue *hw_queue, u32 index, phys_addr_t base_addr_pa); int (*hw_queue_init)(struct iommufd_hw_queue *hw_queue, u32 index); + int (*set_option)(struct iommufd_viommu *viommu, u16 key, u64 value); + int (*get_option)(struct iommufd_viommu *viommu, u16 key, u64 *value); }; =20 #if IS_ENABLED(CONFIG_IOMMUFD) diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index f71a4b979d52..922bb7511045 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -306,10 +306,14 @@ struct iommu_ioas_unmap { * iommu mappings. Value 0 disables combining, everything is mapped to * PAGE_SIZE. This can be useful for benchmarking. This is a per-IOAS * option, the object_id must be the IOAS ID. + * @IOMMU_KEY_VAL_OPTION_VIOMMU: + * Specifies key-value option for vIOMMU object. The caller must specify + * vIOMMU ID for object_id. The allowed ops are set and get. */ enum iommufd_option { IOMMU_OPTION_RLIMIT_MODE =3D 0, IOMMU_OPTION_HUGE_PAGES =3D 1, + IOMMU_OPTION_VIOMMU =3D 2, }; =20 /** @@ -328,7 +332,7 @@ enum iommufd_option_ops { * @size: sizeof(struct iommu_option) * @option_id: One of enum iommufd_option * @op: One of enum iommufd_option_ops - * @__reserved: Must be 0 + * @key: Option key to match with the value * @object_id: ID of the object if required * @val64: Option value to set or value returned on get * @@ -340,7 +344,7 @@ struct iommu_option { __u32 size; __u32 option_id; __u16 op; - __u16 __reserved; + __u16 key; __u32 object_id; __aligned_u64 val64; }; --=20 2.34.1 From nobody Thu Apr 2 10:57:37 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012044.outbound.protection.outlook.com [52.101.48.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBB9D3B0AC5 for ; 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Mon, 30 Mar 2026 03:44:16 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 21/22] iommu/amd: Handle set/get option for AMD vIOMMU hw_queue Date: Mon, 30 Mar 2026 08:42:05 +0000 Message-ID: <20260330084206.9251-22-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> References: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|BY5PR12MB4194:EE_ X-MS-Office365-Filtering-Correlation-Id: 9723698d-cbeb-4967-fb1d-08de8e388dba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|7416014|376014|1800799024|22082099003|56012099003|18002099003; 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charset="utf-8" Guest kernel programs guest Command Buffer, Event Log, and PPR Log (a.k.a hardware queue) settings via guest control MMIO register (guest MMIO offset 0x18). Accesses to the register is trapped by VMM (QEMU) and information is passed as IOMMU_VIOMMU_OPTION to host IOMMU driver via struct iommufd_viommu_ops set_option() and get_option(). Provides AMD IOMMU driver hooks to handle set/get operations for the guest control MMIO register, which uses key parameter as AMD IOMMU MMIO offset. The value parameter contains the value of the corresponding guest MMIO register, which is converted to the format of AMD vIOMMU VF Control MMIO registers then programed onto the hardware. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/Makefile | 2 +- drivers/iommu/amd/amd_iommu_types.h | 5 + drivers/iommu/amd/amd_viommu.h | 15 +++ drivers/iommu/amd/iommufd.c | 2 + drivers/iommu/amd/vfctrl_mmio.c | 145 ++++++++++++++++++++++++++++ 5 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 drivers/iommu/amd/vfctrl_mmio.c diff --git a/drivers/iommu/amd/Makefile b/drivers/iommu/amd/Makefile index e1e824b9c7b0..a5049fd7f789 100644 --- a/drivers/iommu/amd/Makefile +++ b/drivers/iommu/amd/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-y +=3D iommu.o init.o quirks.o ppr.o pasid.o -obj-$(CONFIG_AMD_IOMMU_IOMMUFD) +=3D iommufd.o nested.o viommu.o +obj-$(CONFIG_AMD_IOMMU_IOMMUFD) +=3D iommufd.o nested.o viommu.o vfctrl_mm= io.o obj-$(CONFIG_AMD_IOMMU_DEBUGFS) +=3D debugfs.o diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 1cd50a4008fb..ff72023fa512 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -194,10 +194,15 @@ #define CONTROL_GAM_EN 25 #define CONTROL_GALOG_EN 28 #define CONTROL_GAINT_EN 29 +#define CONTROL_DUALPPRLOG_EN 30 +#define CONTROL_DUALEVTLOG_EN 32 +#define CONTROL_PPR_AUTO_RSP_EN 39 +#define CONTROL_BLKSTOPMRK_EN 41 #define CONTROL_NUM_INT_REMAP_MODE 43 #define CONTROL_NUM_INT_REMAP_MODE_MASK 0x03 #define CONTROL_NUM_INT_REMAP_MODE_2K 0x01 #define CONTROL_EPH_EN 45 +#define CONTROL_PPR_AUTO_RSP_AON 48 #define CONTROL_XT_EN 50 #define CONTROL_INTCAPXT_EN 51 #define CONTROL_GCR3TRPMODE 58 diff --git a/drivers/iommu/amd/amd_viommu.h b/drivers/iommu/amd/amd_viommu.h index 93e44f8b6012..bd4e7481ee0c 100644 --- a/drivers/iommu/amd/amd_viommu.h +++ b/drivers/iommu/amd/amd_viommu.h @@ -21,6 +21,11 @@ int amd_viommu_domain_id_update(struct amd_iommu *iommu,= u16 gid, =20 void amd_viommu_set_device_mapping(struct amd_iommu *iommu, u16 hDevId, u16 guestId, u16 gDevId); + +int amd_viommu_guest_mmio_write(struct iommufd_viommu *viommu, u16 offset,= u64 value); + +int amd_viommu_guest_mmio_read(struct iommufd_viommu *viommu, u16 offset, = u64 *value); + #else =20 static inline int amd_viommu_init(struct amd_iommu *iommu) @@ -47,6 +52,16 @@ static inline void amd_viommu_set_device_mapping(struct = amd_iommu *iommu, u16 hD { } =20 +static inline int amd_viommu_guest_mmio_write(struct iommufd_viommu *viomm= u, u16 offset, u64 value) +{ + return -EOPNOTSUPP; +} + +static inline int amd_viommu_guest_mmio_read(struct iommufd_viommu *viommu= , u16 offset, u64 *value) +{ + return -EOPNOTSUPP; +} + #endif /* CONFIG_AMD_IOMMU_IOMMUFD */ =20 #endif /* AMD_VIOMMU_H */ diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 6f766254a390..b10cbff02288 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -242,4 +242,6 @@ static const struct iommufd_viommu_ops amd_viommu_ops = =3D { .vdevice_init =3D _amd_viommu_vdevice_init, .get_hw_queue_size =3D _amd_viommu_get_hw_queue_size, .hw_queue_init =3D _amd_viommu_hw_queue_init, + .set_option =3D amd_viommu_guest_mmio_write, + .get_option =3D amd_viommu_guest_mmio_read, }; diff --git a/drivers/iommu/amd/vfctrl_mmio.c b/drivers/iommu/amd/vfctrl_mmi= o.c new file mode 100644 index 000000000000..1dcccc24e847 --- /dev/null +++ b/drivers/iommu/amd/vfctrl_mmio.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Advanced Micro Devices, Inc. + * Author: Suravee Suthikulpanit + */ + +#define pr_fmt(fmt) "AMD-Vi: " fmt +#define dev_fmt(fmt) pr_fmt(fmt) + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "amd_iommu.h" +#include "amd_iommu_types.h" +#include "amd_viommu.h" +#include "../iommu-pages.h" + +#define GET_CTRL_BITS(reg, bit, msk) (((reg) >> (bit)) & (ULL(msk))) +#define SET_CTRL_BITS(reg, bit1, bit2, msk) \ + ((((reg) >> (bit1)) & (ULL(msk))) << (bit2)) + +int amd_viommu_guest_mmio_read(struct iommufd_viommu *viommu, u16 offset, = u64 *value) +{ + u8 __iomem *vfctrl, *vf; + u64 val, tmp =3D 0; + struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); + struct amd_iommu *iommu =3D container_of(viommu->iommu_dev, struct amd_io= mmu, iommu); + int gid =3D aviommu->gid; + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (offset) { + case MMIO_CONTROL_OFFSET: + { + /* VFCTRL offset 20h */ + val =3D readq(vfctrl + 0x20); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_CMDBUF_EN, 1); // [12] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_COMWAIT_EN, 1); // [4] + + /* VFCTRL offset 28h */ + val =3D readq(vfctrl + 0x28); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_EVT_LOG_EN, 1); // [2] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_EVT_INT_EN, 1); // [3] + tmp |=3D SET_CTRL_BITS(val, 10, CONTROL_DUALEVTLOG_EN, 3); // [33:32] + + /* VFCTRL offset 30h */ + val =3D readq(vfctrl + 0x30); + tmp |=3D SET_CTRL_BITS(val, 8, CONTROL_PPRLOG_EN, 1); // [13] + tmp |=3D SET_CTRL_BITS(val, 9, CONTROL_PPRINT_EN, 1); // [14] + tmp |=3D SET_CTRL_BITS(val, 10, CONTROL_PPR_EN, 1); // [15] + tmp |=3D SET_CTRL_BITS(val, 11, CONTROL_DUALPPRLOG_EN, 3); // [31:30] + tmp |=3D SET_CTRL_BITS(val, 13, CONTROL_PPR_AUTO_RSP_EN, 1); // [39] + tmp |=3D SET_CTRL_BITS(val, 14, CONTROL_BLKSTOPMRK_EN, 1); // [41] + tmp |=3D SET_CTRL_BITS(val, 15, CONTROL_PPR_AUTO_RSP_AON, 1); // [42] + + *value =3D tmp; + break; + } + default: + WARN_ON(1); + break; + } + + pr_debug("%s: iommu_devid=3D%#x, gid=3D%u, offset=3D%#x, value=3D%#llx\n", + __func__, iommu->devid, gid, offset, *value); + return 0; +} +EXPORT_SYMBOL(amd_viommu_guest_mmio_read); + +int amd_viommu_guest_mmio_write(struct iommufd_viommu *viommu, u16 offset,= u64 value) +{ + u8 __iomem *vfctrl, *vf; + u64 val, tmp, ctrl =3D value; + struct amd_iommu_viommu *aviommu =3D container_of(viommu, struct amd_iomm= u_viommu, core); + struct amd_iommu *iommu =3D container_of(viommu->iommu_dev, struct amd_io= mmu, iommu); + int gid =3D aviommu->gid; + + pr_debug("%s: iommu_devid=3D%#x, gid=3D%u, offset=3D%#x, value=3D%#llx\n", + __func__, iommu->devid, gid, offset, value); + + vf =3D VIOMMU_VF_MMIO_BASE(iommu, gid); + vfctrl =3D VIOMMU_VFCTRL_MMIO_BASE(iommu, gid); + + switch (offset) { + case MMIO_CONTROL_OFFSET: + { + /* VFCTRL offset 20h */ + val =3D readq(vfctrl + 0x20); + val &=3D ~(0x3ULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_CMDBUF_EN, 1); // [12] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_COMWAIT_EN, 1); // [4] + val |=3D (tmp << 9); + writeq(val, vfctrl + 0x20); + + /* VFCTRL offset 28h */ + val =3D readq(vfctrl + 0x28); + val &=3D ~(0xFULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_EVT_LOG_EN, 1); // [2] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_EVT_INT_EN, 1); // [3] + val |=3D (tmp << 9); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_DUALEVTLOG_EN, 3); // [33:32] + val |=3D (tmp << 10); + writeq(val, vfctrl + 0x28); + + /* VFCTRL offset 30h */ + val =3D readq(vfctrl + 0x30); + val &=3D ~(0xFFULL << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPRLOG_EN, 1); // [13] + val |=3D (tmp << 8); + tmp =3D GET_CTRL_BITS(ctrl, CONTROL_PPRINT_EN, 1); // [14] + val |=3D (tmp << 9); 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Mon, 30 Mar 2026 03:44:21 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH 22/22] iommu/amd: Introduce logic to check and enable vIOMMU feature Date: Mon, 30 Mar 2026 08:42:06 +0000 Message-ID: <20260330084206.9251-23-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> References: <20260330084206.9251-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D0:EE_|IA1PR12MB6044:EE_ X-MS-Office365-Filtering-Correlation-Id: dd61a066-a3b4-4cea-31f7-08de8e388f29 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|7416014|376014|82310400026|18002099003|22082099003|56012099003; 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charset="utf-8" Also switch to enable vIOMMU by default, and provide kernel boot option to disable the feature. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu.h | 1 + drivers/iommu/amd/amd_iommu_types.h | 3 +++ drivers/iommu/amd/init.c | 14 +++++++++++++- drivers/iommu/amd/viommu.c | 16 ++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h index 38694ebdb083..2b057ab77ce8 100644 --- a/drivers/iommu/amd/amd_iommu.h +++ b/drivers/iommu/amd/amd_iommu.h @@ -25,6 +25,7 @@ void amd_iommu_restart_ga_log(struct amd_iommu *iommu); void amd_iommu_restart_ppr_log(struct amd_iommu *iommu); void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid); void iommu_feature_enable(struct amd_iommu *iommu, u8 bit); +bool iommu_feature_enable_and_check(struct amd_iommu *iommu, u8 bit); void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, gfp_t gfp, size_t size); u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end); diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index ff72023fa512..4667efcfb8e9 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -204,9 +204,12 @@ #define CONTROL_EPH_EN 45 #define CONTROL_PPR_AUTO_RSP_AON 48 #define CONTROL_XT_EN 50 +#define CONTROL_VCMD_EN 52 +#define CONTROL_VIOMMU_EN 53 #define CONTROL_INTCAPXT_EN 51 #define CONTROL_GCR3TRPMODE 58 #define CONTROL_IRTCACHEDIS 59 +#define CONTROL_GSTBUFFERTRPMODE 60 #define CONTROL_SNPAVIC_EN 61 =20 #define CTRL_INV_TO_MASK 7 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 0018ae804ab4..63271f4305de 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -195,7 +195,7 @@ bool amdr_ivrs_remap_support __read_mostly; bool amd_iommu_force_isolation __read_mostly; =20 /* VIOMMU enabling flag */ -bool amd_iommu_viommu; +bool amd_iommu_viommu =3D true; =20 unsigned long amd_iommu_pgsize_bitmap __ro_after_init =3D AMD_IOMMU_PGSIZE= S; =20 @@ -436,6 +436,16 @@ void iommu_feature_enable(struct amd_iommu *iommu, u8 = bit) iommu_feature_set(iommu, 1ULL, 1ULL, bit); } =20 +bool iommu_feature_enable_and_check(struct amd_iommu *iommu, u8 bit) +{ + u64 ctrl; + + iommu_feature_enable(iommu, bit); + + ctrl =3D readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); + return (ctrl & (1ULL << bit)); +} + static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) { iommu_feature_set(iommu, 0ULL, 1ULL, bit); @@ -3702,6 +3712,8 @@ static int __init parse_amd_iommu_options(char *str) } else if (strncmp(str, "v2_pgsizes_only", 15) =3D=3D 0) { pr_info("Restricting V1 page-sizes to 4KiB/2MiB/1GiB"); amd_iommu_pgsize_bitmap =3D AMD_IOMMU_PGSIZES_V2; + } else if (strncmp(str, "viommu_disable", 14) =3D=3D 0) { + amd_iommu_viommu =3D false; } else { pr_notice("Unknown option - '%s'\n", str); } diff --git a/drivers/iommu/amd/viommu.c b/drivers/iommu/amd/viommu.c index 4626134893d6..5c744de729d5 100644 --- a/drivers/iommu/amd/viommu.c +++ b/drivers/iommu/amd/viommu.c @@ -45,6 +45,18 @@ =20 LIST_HEAD(viommu_devid_map); =20 +static int viommu_enable(struct amd_iommu *iommu) +{ + /* The GstBufferTRPMode feature is checked by set and test */ + if (!iommu_feature_enable_and_check(iommu, CONTROL_GSTBUFFERTRPMODE)) + return -EINVAL; + + iommu_feature_enable(iommu, CONTROL_VCMD_EN); + iommu_feature_enable(iommu, CONTROL_VIOMMU_EN); + + return 0; +} + static int viommu_init_pci_vsc(struct amd_iommu *iommu) { iommu->vsc_offset =3D pci_find_capability(iommu->dev, PCI_CAP_ID_VNDR); @@ -298,6 +310,10 @@ int __init amd_viommu_init(struct amd_iommu *iommu) =20 set_iommu_dte(iommu); =20 + ret =3D viommu_enable(iommu); + if (ret) + return ret; + return 0; } =20 --=20 2.34.1