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Mon, 30 Mar 2026 01:34:57 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Fabien Parent , Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Linus Walleij , Liam Girdwood , Mark Brown , Louis-Alexis Eyraud , Gary Bisson , Julien Massot , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 1/9] dt-bindings: mfd: mt6397: Add MT6392 PMIC Date: Mon, 30 Mar 2026 09:29:35 +0100 Message-ID: <20260330083429.359819-2-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add the currently supported bindings for the MT6392 PMIC. Remove the required constraint for the regulators node compatible property to fix a dtbs_check error. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- .../devicetree/bindings/mfd/mediatek,mt6397.yaml | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/D= ocumentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 05c121b0cb3d..bfad018cfbf3 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -40,6 +40,10 @@ properties: - mediatek,mt6358 - mediatek,mt6359 - mediatek,mt6397 + - items: + - enum: + - mediatek,mt6392 + - const: mediatek,mt6323 - items: - enum: - mediatek,mt6366 @@ -68,6 +72,10 @@ properties: - mediatek,mt6331-rtc - mediatek,mt6358-rtc - mediatek,mt6397-rtc + - items: + - enum: + - mediatek,mt6392-rtc + - const: mediatek,mt6323-rtc - items: - enum: - mediatek,mt6366-rtc @@ -99,9 +107,6 @@ properties: - mediatek,mt6366-regulator - const: mediatek,mt6358-regulator =20 - required: - - compatible - adc: type: object $ref: /schemas/iio/adc/mediatek,mt6359-auxadc.yaml# --=20 2.43.0 From nobody Thu Apr 2 05:49:35 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24FFF3AD519 for ; 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charset="utf-8" From: Fabien Parent Add the binding documentation of mtk-pmic-keys for the MT6392 PMIC. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno Acked-by: Dmitry Torokhov Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yam= l b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index b95435bd6a9b..2d3c4161a7f8 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -30,6 +30,7 @@ properties: - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6359-keys + - mediatek,mt6392-keys - mediatek,mt6397-keys =20 power-off-time-sec: true --=20 2.43.0 From nobody Thu Apr 2 05:49:35 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 704052AE78 for ; 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Mon, 30 Mar 2026 01:35:20 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48722c6b495sm508329995e9.2.2026.03.30.01.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2026 01:35:20 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Linus Walleij , Liam Girdwood , Mark Brown , Julien Massot , Gary Bisson , Louis-Alexis Eyraud , Val Packett , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 3/9] regulator: dt-bindings: Add MediaTek MT6392 PMIC Date: Mon, 30 Mar 2026 09:29:37 +0100 Message-ID: <20260330083429.359819-4-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bindings for the regulators found in the MediaTek MT6392 PMIC, usually found in board designs using the MediaTek MT8516/MT8167 SoCs. Signed-off-by: Luca Leonardo Scorcia --- .../regulator/mediatek,mt6392-regulator.yaml | 74 +++++++++++++++++++ .../regulator/mediatek,mt6392-regulator.h | 24 ++++++ 2 files changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/mediatek,mt= 6392-regulator.yaml create mode 100644 include/dt-bindings/regulator/mediatek,mt6392-regulator= .h diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6392-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6392-= regulator.yaml new file mode 100644 index 000000000000..24fbaef0e717 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6392-regulator= .yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6392-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6392 regulator + +description: + Regulator node of the PMIC. This node should under the PMIC's device nod= e. + MT6392 is a power management system chip containing three buck converter= s and + 23 LDOs. All voltage regulators provided by the PMIC are described as + sub-nodes of this node. + +properties: + vproc-supply: + description: Supply for buck regulator vproc + vcore-supply: + description: Supply for buck regulator vcore + vsys-supply: + description: Supply for buck regulator vsys + avddldo-supply: + description: | + Supply for AVDD LDOs (vm, vio18, vcn18, vcamd, vcamio). According to= the data sheet + this is an internal supply derived from vsys. + ldo1-supply: + description: Supply for LDOs group 1 (vaud28, vxo22, vaud22, vadc18, v= cama, vrtc) + ldo2-supply: + description: Supply for LDOs group 2 (vcn35, vio28, vmc, vmch, vefuse,= vdig18) + ldo3-supply: + description: Supply for LDOs group 3 (vusb, vemc3v3, vcamaf, vgp1, vgp= 2, vm25) + +patternProperties: + "^v(core|proc|sys)$": + description: Buck regulators + type: object + $ref: regulator.yaml# + properties: + regulator-allowed-modes: + description: | + BUCK regulators can set regulator-initial-mode and regulator-all= owed-modes to + values specified in dt-bindings/regulator/mediatek,mt6392-regula= tor.h + items: + enum: [0, 1] + unevaluatedProperties: false + + "^v(adc18|camio|cn18|io18|xo22|m25|aud28|io28|rtc|vusb)$": + description: LDOs with fixed output and mode setting + type: object + $ref: regulator.yaml# + properties: + regulator-allowed-modes: + description: | + LDO regulators can set regulator-initial-mode and regulator-allo= wed-modes to + values specified in dt-bindings/regulator/mediatek,mt6392-regula= tor.h + items: + enum: [0, 1] + unevaluatedProperties: false + + "^v(cama|dig18)$": + description: LDOs with fixed output without mode setting + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^v(aud22|camaf|camd|cn35|efuse|emc3v3|gp1|gp2|m|mc|mch)$": + description: LDOs with adjustable output + type: object + $ref: regulator.yaml# + properties: + regulator-allowed-modes: false + unevaluatedProperties: false + +additionalProperties: false diff --git a/include/dt-bindings/regulator/mediatek,mt6392-regulator.h b/in= clude/dt-bindings/regulator/mediatek,mt6392-regulator.h new file mode 100644 index 000000000000..8bd1a13faad8 --- /dev/null +++ b/include/dt-bindings/regulator/mediatek,mt6392-regulator.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_REGULATOR_MEDIATEK_MT6392_H_ +#define _DT_BINDINGS_REGULATOR_MEDIATEK_MT6392_H_ + +/* + * Buck mode constants which may be used in devicetree properties (eg. + * regulator-initial-mode, regulator-allowed-modes). + * See the manufacturer's datasheet for more information on these modes. + */ + +#define MT6392_BUCK_MODE_AUTO 0 +#define MT6392_BUCK_MODE_FORCE_PWM 1 + +/* + * LDO mode constants which may be used in devicetree properties (eg. + * regulator-initial-mode, regulator-allowed-modes). + * See the manufacturer's datasheet for more information on these modes. + */ + +#define MT6392_LDO_MODE_NORMAL 0 +#define MT6392_LDO_MODE_LP 1 + +#endif --=20 2.43.0 From nobody Thu Apr 2 05:49:35 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE5543A7581 for ; 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Mon, 30 Mar 2026 01:35:32 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48722c6b495sm508329995e9.2.2026.03.30.01.35.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2026 01:35:31 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , Linus Walleij , Liam Girdwood , Mark Brown , Val Packett , Louis-Alexis Eyraud , Julien Massot , Gary Bisson , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 4/9] dt-bindings: pinctrl: mediatek,mt65xx: Add MT6392 pinctrl Date: Mon, 30 Mar 2026 09:29:38 +0100 Message-ID: <20260330083429.359819-5-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a compatible for the pinctrl device of the MT6392 PMIC, a variant of the already supported MT6397. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- .../pinctrl/mediatek,mt65xx-pinctrl.yaml | 1 + .../pinctrl/mediatek,mt6392-pinfunc.h | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinc= trl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctr= l.yaml index aa71398cf522..1468c6f87cfa 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -17,6 +17,7 @@ properties: enum: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl + - mediatek,mt6392-pinctrl - mediatek,mt6397-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl diff --git a/include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h b/includ= e/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h new file mode 100644 index 000000000000..c65278c8103d --- /dev/null +++ b/include/dt-bindings/pinctrl/mediatek,mt6392-pinfunc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +#ifndef __DTS_MT6392_PINFUNC_H +#define __DTS_MT6392_PINFUNC_H + +#include + +#define MT6392_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT6392_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1) +#define MT6392_PIN_0_INT__FUNC_TEST_CK2 (MTK_PIN_NO(0) | 5) +#define MT6392_PIN_0_INT__FUNC_TEST_IN1 (MTK_PIN_NO(0) | 6) +#define MT6392_PIN_0_INT__FUNC_TEST_OUT1 (MTK_PIN_NO(0) | 7) + +#define MT6392_PIN_1_SRCLKEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT6392_PIN_1_SRCLKEN__FUNC_SRCLKEN (MTK_PIN_NO(1) | 1) +#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_CK0 (MTK_PIN_NO(1) | 5) +#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_IN2 (MTK_PIN_NO(1) | 6) +#define MT6392_PIN_1_SRCLKEN__FUNC_TEST_OUT2 (MTK_PIN_NO(1) | 7) + +#define MT6392_PIN_2_RTC_32K1V8__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT6392_PIN_2_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(2) | 1) +#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_CK1 (MTK_PIN_NO(2) | 5) +#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_IN3 (MTK_PIN_NO(2) | 6) +#define MT6392_PIN_2_RTC_32K1V8__FUNC_TEST_OUT3 (MTK_PIN_NO(2) | 7) + +#define MT6392_PIN_3_SPI_CLK__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT6392_PIN_3_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(3) | 1) + +#define MT6392_PIN_4_SPI_CSN__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT6392_PIN_4_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(4) | 1) + +#define MT6392_PIN_5_SPI_MOSI__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT6392_PIN_5_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(5) | 1) + +#define MT6392_PIN_6_SPI_MISO__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT6392_PIN_6_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(6) | 1) +#define MT6392_PIN_6_SPI_MISO__FUNC_TEST_IN4 (MTK_PIN_NO(6) | 6) +#define MT6392_PIN_6_SPI_MISO__FUNC_TEST_OUT4 (MTK_PIN_NO(6) | 7) + +#endif /* __DTS_MT6392_PINFUNC_H */ --=20 2.43.0 From nobody Thu Apr 2 05:49:35 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C8433AD51B for ; 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Mon, 30 Mar 2026 01:35:44 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48722c6b495sm508329995e9.2.2026.03.30.01.35.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2026 01:35:43 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Fabien Parent , Val Packett , Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , Linus Walleij , Liam Girdwood , Mark Brown , Gary Bisson , Julien Massot , Louis-Alexis Eyraud , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 5/9] mfd: mt6397: Add support for MT6392 PMIC Date: Mon, 30 Mar 2026 09:29:39 +0100 Message-ID: <20260330083429.359819-6-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fabien Parent Align the MT6397 PMIC driver to other MFD drivers by passing only an identifier through mt6397_of_match[*].data and add support for the MT6392 PMIC. Signed-off-by: Fabien Parent Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- drivers/mfd/mt6397-core.c | 118 +++++-- drivers/mfd/mt6397-irq.c | 8 + include/linux/mfd/mt6392/core.h | 42 +++ include/linux/mfd/mt6392/registers.h | 487 +++++++++++++++++++++++++++ include/linux/mfd/mt6397/core.h | 1 + 5 files changed, 630 insertions(+), 26 deletions(-) create mode 100644 include/linux/mfd/mt6392/core.h create mode 100644 include/linux/mfd/mt6392/registers.h diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c index 3e58d0764c7e..f141759216cf 100644 --- a/drivers/mfd/mt6397-core.c +++ b/drivers/mfd/mt6397-core.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -25,8 +26,20 @@ #include #include #include +#include #include =20 +enum mfd_match_data { + MATCH_DATA_MT6323 =3D 23, + MATCH_DATA_MT6328 =3D 28, + MATCH_DATA_MT6331 =3D 31, + MATCH_DATA_MT6357 =3D 57, + MATCH_DATA_MT6358 =3D 58, + MATCH_DATA_MT6359 =3D 59, + MATCH_DATA_MT6392 =3D 92, + MATCH_DATA_MT6397 =3D 97, +}; + #define MT6323_RTC_BASE 0x8000 #define MT6323_RTC_SIZE 0x40 =20 @@ -39,6 +52,9 @@ #define MT6358_RTC_BASE 0x0588 #define MT6358_RTC_SIZE 0x3c =20 +#define MT6392_RTC_BASE 0x8000 +#define MT6392_RTC_SIZE 0x3e + #define MT6397_RTC_BASE 0xe000 #define MT6397_RTC_SIZE 0x3e =20 @@ -65,6 +81,11 @@ static const struct resource mt6358_rtc_resources[] =3D { DEFINE_RES_IRQ(MT6358_IRQ_RTC), }; =20 +static const struct resource mt6392_rtc_resources[] =3D { + DEFINE_RES_MEM(MT6392_RTC_BASE, MT6392_RTC_SIZE), + DEFINE_RES_IRQ(MT6392_IRQ_RTC), +}; + static const struct resource mt6397_rtc_resources[] =3D { DEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE), DEFINE_RES_IRQ(MT6397_IRQ_RTC), @@ -114,6 +135,11 @@ static const struct resource mt6331_keys_resources[] = =3D { DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"), }; =20 +static const struct resource mt6392_keys_resources[] =3D { + DEFINE_RES_IRQ_NAMED(MT6392_IRQ_PWRKEY, "powerkey"), + DEFINE_RES_IRQ_NAMED(MT6392_IRQ_FCHRKEY, "homekey"), +}; + static const struct resource mt6397_keys_resources[] =3D { DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"), DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"), @@ -253,6 +279,25 @@ static const struct mfd_cell mt6359_devs[] =3D { }, }; =20 +static const struct mfd_cell mt6392_devs[] =3D { + { + .name =3D "mt6392-rtc", + .num_resources =3D ARRAY_SIZE(mt6392_rtc_resources), + .resources =3D mt6392_rtc_resources, + .of_compatible =3D "mediatek,mt6392-rtc", + }, { + .name =3D "mt6392-regulator", + }, { + .name =3D "mt6392-pinctrl", + .of_compatible =3D "mediatek,mt6392-pinctrl", + }, { + .name =3D "mt6392-keys", + .num_resources =3D ARRAY_SIZE(mt6392_keys_resources), + .resources =3D mt6392_keys_resources, + .of_compatible =3D "mediatek,mt6392-keys" + }, +}; + static const struct mfd_cell mt6397_devs[] =3D { { .name =3D "mt6397-rtc", @@ -335,6 +380,14 @@ static const struct chip_data mt6359_core =3D { .irq_init =3D mt6358_irq_init, }; =20 +static const struct chip_data mt6392_core =3D { + .cid_addr =3D MT6392_CID, + .cid_shift =3D 0, + .cells =3D mt6392_devs, + .cell_size =3D ARRAY_SIZE(mt6392_devs), + .irq_init =3D mt6397_irq_init, +}; + static const struct chip_data mt6397_core =3D { .cid_addr =3D MT6397_CID, .cid_shift =3D 0, @@ -349,6 +402,7 @@ static int mt6397_probe(struct platform_device *pdev) unsigned int id =3D 0; struct mt6397_chip *pmic; const struct chip_data *pmic_core; + enum mfd_match_data device_data; =20 pmic =3D devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); if (!pmic) @@ -364,9 +418,36 @@ static int mt6397_probe(struct platform_device *pdev) if (!pmic->regmap) return -ENODEV; =20 - pmic_core =3D of_device_get_match_data(&pdev->dev); - if (!pmic_core) + device_data =3D (enum mfd_match_data)of_device_get_match_data(&pdev->dev); + switch (device_data) { + case MATCH_DATA_MT6323: + pmic_core =3D &mt6323_core; + break; + case MATCH_DATA_MT6328: + pmic_core =3D &mt6328_core; + break; + case MATCH_DATA_MT6331: + pmic_core =3D &mt6331_mt6332_core; + break; + case MATCH_DATA_MT6357: + pmic_core =3D &mt6357_core; + break; + case MATCH_DATA_MT6358: + pmic_core =3D &mt6358_core; + break; + case MATCH_DATA_MT6359: + pmic_core =3D &mt6359_core; + break; + case MATCH_DATA_MT6392: + pmic_core =3D &mt6392_core; + break; + case MATCH_DATA_MT6397: + pmic_core =3D &mt6397_core; + break; + default: + dev_err(&pdev->dev, "Unknown device match data %u\n", device_data); return -ENODEV; + } =20 ret =3D regmap_read(pmic->regmap, pmic_core->cid_addr, &id); if (ret) { @@ -398,30 +479,15 @@ static int mt6397_probe(struct platform_device *pdev) } =20 static const struct of_device_id mt6397_of_match[] =3D { - { - .compatible =3D "mediatek,mt6323", - .data =3D &mt6323_core, - }, { - .compatible =3D "mediatek,mt6328", - .data =3D &mt6328_core, - }, { - .compatible =3D "mediatek,mt6331", - .data =3D &mt6331_mt6332_core, - }, { - .compatible =3D "mediatek,mt6357", - .data =3D &mt6357_core, - }, { - .compatible =3D "mediatek,mt6358", - .data =3D &mt6358_core, - }, { - .compatible =3D "mediatek,mt6359", - .data =3D &mt6359_core, - }, { - .compatible =3D "mediatek,mt6397", - .data =3D &mt6397_core, - }, { - /* sentinel */ - } + { .compatible =3D "mediatek,mt6323", .data =3D (void *)MATCH_DATA_MT6323,= }, + { .compatible =3D "mediatek,mt6328", .data =3D (void *)MATCH_DATA_MT6328,= }, + { .compatible =3D "mediatek,mt6331", .data =3D (void *)MATCH_DATA_MT6331,= }, + { .compatible =3D "mediatek,mt6357", .data =3D (void *)MATCH_DATA_MT6357,= }, + { .compatible =3D "mediatek,mt6358", .data =3D (void *)MATCH_DATA_MT6358,= }, + { .compatible =3D "mediatek,mt6359", .data =3D (void *)MATCH_DATA_MT6359,= }, + { .compatible =3D "mediatek,mt6392", .data =3D (void *)MATCH_DATA_MT6392,= }, + { .compatible =3D "mediatek,mt6397", .data =3D (void *)MATCH_DATA_MT6397,= }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mt6397_of_match); =20 diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c index 5d2e5459f744..80ea5b92d232 100644 --- a/drivers/mfd/mt6397-irq.c +++ b/drivers/mfd/mt6397-irq.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include =20 @@ -203,6 +205,12 @@ int mt6397_irq_init(struct mt6397_chip *chip) chip->int_status[0] =3D MT6397_INT_STATUS0; chip->int_status[1] =3D MT6397_INT_STATUS1; break; + case MT6392_CHIP_ID: + chip->int_con[0] =3D MT6392_INT_CON0; + chip->int_con[1] =3D MT6392_INT_CON1; + chip->int_status[0] =3D MT6392_INT_STATUS0; + chip->int_status[1] =3D MT6392_INT_STATUS1; + break; =20 default: dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id); diff --git a/include/linux/mfd/mt6392/core.h b/include/linux/mfd/mt6392/cor= e.h new file mode 100644 index 000000000000..4780dab4da92 --- /dev/null +++ b/include/linux/mfd/mt6392/core.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __MFD_MT6392_CORE_H__ +#define __MFD_MT6392_CORE_H__ + +enum mt6392_irq_numbers { + MT6392_IRQ_SPKL_AB =3D 0, + MT6392_IRQ_SPKL, + MT6392_IRQ_BAT_L, + MT6392_IRQ_BAT_H, + MT6392_IRQ_WATCHDOG, + MT6392_IRQ_PWRKEY, + MT6392_IRQ_THR_L, + MT6392_IRQ_THR_H, + MT6392_IRQ_VBATON_UNDET, + MT6392_IRQ_BVALID_DET, + MT6392_IRQ_CHRDET, + MT6392_IRQ_OV, + MT6392_IRQ_LDO =3D 16, + MT6392_IRQ_FCHRKEY, + MT6392_IRQ_RELEASE_PWRKEY, + MT6392_IRQ_RELEASE_FCHRKEY, + MT6392_IRQ_RTC, + MT6392_IRQ_VPROC, + MT6392_IRQ_VSYS, + MT6392_IRQ_VCORE, + MT6392_IRQ_TYPE_C_CC, + MT6392_IRQ_TYPEC_H_MAX, + MT6392_IRQ_TYPEC_H_MIN, + MT6392_IRQ_TYPEC_L_MAX, + MT6392_IRQ_TYPEC_L_MIN, + MT6392_IRQ_THR_MAX, + MT6392_IRQ_THR_MIN, + MT6392_IRQ_NAG_C_DLTV, + MT6392_IRQ_NR, +}; + +#endif /* __MFD_MT6392_CORE_H__ */ diff --git a/include/linux/mfd/mt6392/registers.h b/include/linux/mfd/mt639= 2/registers.h new file mode 100644 index 000000000000..4f3a6db830d1 --- /dev/null +++ b/include/linux/mfd/mt6392/registers.h @@ -0,0 +1,487 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __MFD_MT6392_REGISTERS_H__ +#define __MFD_MT6392_REGISTERS_H__ + +/* PMIC Registers */ +#define MT6392_CHR_CON0 0x0000 +#define MT6392_CHR_CON1 0x0002 +#define MT6392_CHR_CON2 0x0004 +#define MT6392_CHR_CON3 0x0006 +#define MT6392_CHR_CON4 0x0008 +#define MT6392_CHR_CON5 0x000A +#define MT6392_CHR_CON6 0x000C +#define MT6392_CHR_CON7 0x000E +#define MT6392_CHR_CON8 0x0010 +#define MT6392_CHR_CON9 0x0012 +#define MT6392_CHR_CON10 0x0014 +#define MT6392_CHR_CON11 0x0016 +#define MT6392_CHR_CON12 0x0018 +#define MT6392_CHR_CON13 0x001A +#define MT6392_CHR_CON14 0x001C +#define MT6392_CHR_CON15 0x001E +#define MT6392_CHR_CON16 0x0020 +#define MT6392_CHR_CON17 0x0022 +#define MT6392_CHR_CON18 0x0024 +#define MT6392_CHR_CON19 0x0026 +#define MT6392_CHR_CON20 0x0028 +#define MT6392_CHR_CON21 0x002A +#define MT6392_CHR_CON22 0x002C +#define MT6392_CHR_CON23 0x002E +#define MT6392_CHR_CON24 0x0030 +#define MT6392_CHR_CON25 0x0032 +#define MT6392_CHR_CON26 0x0034 +#define MT6392_CHR_CON27 0x0036 +#define MT6392_CHR_CON28 0x0038 +#define MT6392_CHR_CON29 0x003A +#define MT6392_STRUP_CON0 0x003C +#define MT6392_STRUP_CON2 0x003E +#define MT6392_STRUP_CON3 0x0040 +#define MT6392_STRUP_CON4 0x0042 +#define MT6392_STRUP_CON5 0x0044 +#define MT6392_STRUP_CON6 0x0046 +#define MT6392_STRUP_CON7 0x0048 +#define MT6392_STRUP_CON8 0x004A +#define MT6392_STRUP_CON9 0x004C +#define MT6392_STRUP_CON10 0x004E +#define MT6392_STRUP_CON11 0x0050 +#define MT6392_SPK_CON0 0x0052 +#define MT6392_SPK_CON1 0x0054 +#define MT6392_SPK_CON2 0x0056 +#define MT6392_SPK_CON6 0x005E +#define MT6392_SPK_CON7 0x0060 +#define MT6392_SPK_CON8 0x0062 +#define MT6392_SPK_CON9 0x0064 +#define MT6392_SPK_CON10 0x0066 +#define MT6392_SPK_CON11 0x0068 +#define MT6392_SPK_CON12 0x006A +#define MT6392_STRUP_CON12 0x006E +#define MT6392_STRUP_CON13 0x0070 +#define MT6392_STRUP_CON14 0x0072 +#define MT6392_STRUP_CON15 0x0074 +#define MT6392_STRUP_CON16 0x0076 +#define MT6392_STRUP_CON17 0x0078 +#define MT6392_STRUP_CON18 0x007A +#define MT6392_STRUP_CON19 0x007C +#define MT6392_STRUP_CON20 0x007E +#define MT6392_CID 0x0100 +#define MT6392_TOP_CKPDN0 0x0102 +#define MT6392_TOP_CKPDN0_SET 0x0104 +#define MT6392_TOP_CKPDN0_CLR 0x0106 +#define MT6392_TOP_CKPDN1 0x0108 +#define MT6392_TOP_CKPDN1_SET 0x010A +#define MT6392_TOP_CKPDN1_CLR 0x010C +#define MT6392_TOP_CKPDN2 0x010E +#define MT6392_TOP_CKPDN2_SET 0x0110 +#define MT6392_TOP_CKPDN2_CLR 0x0112 +#define MT6392_TOP_RST_CON 0x0114 +#define MT6392_TOP_RST_CON_SET 0x0116 +#define MT6392_TOP_RST_CON_CLR 0x0118 +#define MT6392_TOP_RST_MISC 0x011A +#define MT6392_TOP_RST_MISC_SET 0x011C +#define MT6392_TOP_RST_MISC_CLR 0x011E +#define MT6392_TOP_CKCON0 0x0120 +#define MT6392_TOP_CKCON0_SET 0x0122 +#define MT6392_TOP_CKCON0_CLR 0x0124 +#define MT6392_TOP_CKCON1 0x0126 +#define MT6392_TOP_CKCON1_SET 0x0128 +#define MT6392_TOP_CKCON1_CLR 0x012A +#define MT6392_TOP_CKTST0 0x012C +#define MT6392_TOP_CKTST1 0x012E +#define MT6392_TOP_CKTST2 0x0130 +#define MT6392_TEST_OUT 0x0132 +#define MT6392_TEST_CON0 0x0134 +#define MT6392_TEST_CON1 0x0136 +#define MT6392_EN_STATUS0 0x0138 +#define MT6392_EN_STATUS1 0x013A +#define MT6392_OCSTATUS0 0x013C +#define MT6392_OCSTATUS1 0x013E +#define MT6392_PGSTATUS 0x0140 +#define MT6392_CHRSTATUS 0x0142 +#define MT6392_TDSEL_CON 0x0144 +#define MT6392_RDSEL_CON 0x0146 +#define MT6392_SMT_CON0 0x0148 +#define MT6392_SMT_CON1 0x014A +#define MT6392_DRV_CON0 0x0152 +#define MT6392_DRV_CON1 0x0154 +#define MT6392_INT_CON0 0x0160 +#define MT6392_INT_CON0_SET 0x0162 +#define MT6392_INT_CON0_CLR 0x0164 +#define MT6392_INT_CON1 0x0166 +#define MT6392_INT_CON1_SET 0x0168 +#define MT6392_INT_CON1_CLR 0x016A +#define MT6392_INT_MISC_CON 0x016C +#define MT6392_INT_MISC_CON_SET 0x016E +#define MT6392_INT_MISC_CON_CLR 0x0170 +#define MT6392_INT_STATUS0 0x0172 +#define MT6392_INT_STATUS1 0x0174 +#define MT6392_OC_GEAR_0 0x0176 +#define MT6392_OC_GEAR_1 0x0178 +#define MT6392_OC_GEAR_2 0x017A +#define MT6392_OC_CTL_VPROC 0x017C +#define MT6392_OC_CTL_VSYS 0x017E +#define MT6392_OC_CTL_VCORE 0x0180 +#define MT6392_FQMTR_CON0 0x0182 +#define MT6392_FQMTR_CON1 0x0184 +#define MT6392_FQMTR_CON2 0x0186 +#define MT6392_RG_SPI_CON 0x0188 +#define MT6392_DEW_DIO_EN 0x018A +#define MT6392_DEW_READ_TEST 0x018C +#define MT6392_DEW_WRITE_TEST 0x018E +#define MT6392_DEW_CRC_SWRST 0x0190 +#define MT6392_DEW_CRC_EN 0x0192 +#define MT6392_DEW_CRC_VAL 0x0194 +#define MT6392_DEW_DBG_MON_SEL 0x0196 +#define MT6392_DEW_CIPHER_KEY_SEL 0x0198 +#define MT6392_DEW_CIPHER_IV_SEL 0x019A +#define MT6392_DEW_CIPHER_EN 0x019C +#define MT6392_DEW_CIPHER_RDY 0x019E +#define MT6392_DEW_CIPHER_MODE 0x01A0 +#define MT6392_DEW_CIPHER_SWRST 0x01A2 +#define MT6392_DEW_RDDMY_NO 0x01A4 +#define MT6392_DEW_RDATA_DLY_SEL 0x01A6 +#define MT6392_CLK_TRIM_CON0 0x01A8 +#define MT6392_BUCK_CON0 0x0200 +#define MT6392_BUCK_CON1 0x0202 +#define MT6392_BUCK_CON2 0x0204 +#define MT6392_BUCK_CON3 0x0206 +#define MT6392_BUCK_CON4 0x0208 +#define MT6392_BUCK_CON5 0x020A +#define MT6392_VPROC_CON0 0x020C +#define MT6392_VPROC_CON1 0x020E +#define MT6392_VPROC_CON2 0x0210 +#define MT6392_VPROC_CON3 0x0212 +#define MT6392_VPROC_CON4 0x0214 +#define MT6392_VPROC_CON5 0x0216 +#define MT6392_VPROC_CON7 0x021A +#define MT6392_VPROC_CON8 0x021C +#define MT6392_VPROC_CON9 0x021E +#define MT6392_VPROC_CON10 0x0220 +#define MT6392_VPROC_CON11 0x0222 +#define MT6392_VPROC_CON12 0x0224 +#define MT6392_VPROC_CON13 0x0226 +#define MT6392_VPROC_CON14 0x0228 +#define MT6392_VPROC_CON15 0x022A +#define MT6392_VPROC_CON18 0x0230 +#define MT6392_VSYS_CON0 0x0232 +#define MT6392_VSYS_CON1 0x0234 +#define MT6392_VSYS_CON2 0x0236 +#define MT6392_VSYS_CON3 0x0238 +#define MT6392_VSYS_CON4 0x023A +#define MT6392_VSYS_CON5 0x023C +#define MT6392_VSYS_CON7 0x0240 +#define MT6392_VSYS_CON8 0x0242 +#define MT6392_VSYS_CON9 0x0244 +#define MT6392_VSYS_CON10 0x0246 +#define MT6392_VSYS_CON11 0x0248 +#define MT6392_VSYS_CON12 0x024A +#define MT6392_VSYS_CON13 0x024C +#define MT6392_VSYS_CON14 0x024E +#define MT6392_VSYS_CON15 0x0250 +#define MT6392_VSYS_CON18 0x0256 +#define MT6392_BUCK_OC_CON0 0x0258 +#define MT6392_BUCK_OC_CON1 0x025A +#define MT6392_BUCK_OC_CON2 0x025C +#define MT6392_BUCK_OC_CON3 0x025E +#define MT6392_BUCK_OC_CON4 0x0260 +#define MT6392_BUCK_OC_VPROC_CON0 0x0262 +#define MT6392_BUCK_OC_VCORE_CON0 0x0264 +#define MT6392_BUCK_OC_VSYS_CON0 0x0266 +#define MT6392_BUCK_ANA_MON_CON0 0x0268 +#define MT6392_BUCK_EFUSE_OC_CON0 0x026A +#define MT6392_VCORE_CON0 0x0300 +#define MT6392_VCORE_CON1 0x0302 +#define MT6392_VCORE_CON2 0x0304 +#define MT6392_VCORE_CON3 0x0306 +#define MT6392_VCORE_CON4 0x0308 +#define MT6392_VCORE_CON5 0x030A +#define MT6392_VCORE_CON7 0x030E +#define MT6392_VCORE_CON8 0x0310 +#define MT6392_VCORE_CON9 0x0312 +#define MT6392_VCORE_CON10 0x0314 +#define MT6392_VCORE_CON11 0x0316 +#define MT6392_VCORE_CON12 0x0318 +#define MT6392_VCORE_CON13 0x031A +#define MT6392_VCORE_CON14 0x031C +#define MT6392_VCORE_CON15 0x031E +#define MT6392_VCORE_CON18 0x0324 +#define MT6392_BUCK_K_CON0 0x032A +#define MT6392_BUCK_K_CON1 0x032C +#define MT6392_BUCK_K_CON2 0x032E +#define MT6392_ANALDO_CON0 0x0400 +#define MT6392_ANALDO_CON1 0x0402 +#define MT6392_ANALDO_CON2 0x0404 +#define MT6392_ANALDO_CON3 0x0406 +#define MT6392_ANALDO_CON4 0x0408 +#define MT6392_ANALDO_CON6 0x040C +#define MT6392_ANALDO_CON7 0x040E +#define MT6392_ANALDO_CON8 0x0410 +#define MT6392_ANALDO_CON10 0x0412 +#define MT6392_ANALDO_CON15 0x0414 +#define MT6392_ANALDO_CON16 0x0416 +#define MT6392_ANALDO_CON17 0x0418 +#define MT6392_ANALDO_CON21 0x0420 +#define MT6392_ANALDO_CON22 0x0422 +#define MT6392_ANALDO_CON23 0x0424 +#define MT6392_ANALDO_CON24 0x0426 +#define MT6392_ANALDO_CON25 0x0428 +#define MT6392_ANALDO_CON26 0x042A +#define MT6392_ANALDO_CON27 0x042C +#define MT6392_ANALDO_CON28 0x042E +#define MT6392_ANALDO_CON29 0x0430 +#define MT6392_DIGLDO_CON0 0x0500 +#define MT6392_DIGLDO_CON2 0x0502 +#define MT6392_DIGLDO_CON3 0x0504 +#define MT6392_DIGLDO_CON5 0x0506 +#define MT6392_DIGLDO_CON6 0x0508 +#define MT6392_DIGLDO_CON7 0x050A +#define MT6392_DIGLDO_CON8 0x050C +#define MT6392_DIGLDO_CON10 0x0510 +#define MT6392_DIGLDO_CON11 0x0512 +#define MT6392_DIGLDO_CON12 0x0514 +#define MT6392_DIGLDO_CON15 0x051A +#define MT6392_DIGLDO_CON20 0x0524 +#define MT6392_DIGLDO_CON21 0x0526 +#define MT6392_DIGLDO_CON23 0x0528 +#define MT6392_DIGLDO_CON24 0x052A +#define MT6392_DIGLDO_CON26 0x052C +#define MT6392_DIGLDO_CON27 0x052E +#define MT6392_DIGLDO_CON28 0x0530 +#define MT6392_DIGLDO_CON29 0x0532 +#define MT6392_DIGLDO_CON30 0x0534 +#define MT6392_DIGLDO_CON31 0x0536 +#define MT6392_DIGLDO_CON32 0x0538 +#define MT6392_DIGLDO_CON33 0x053A +#define MT6392_DIGLDO_CON36 0x0540 +#define MT6392_DIGLDO_CON41 0x0546 +#define MT6392_DIGLDO_CON44 0x054C +#define MT6392_DIGLDO_CON47 0x0552 +#define MT6392_DIGLDO_CON48 0x0554 +#define MT6392_DIGLDO_CON49 0x0556 +#define MT6392_DIGLDO_CON50 0x0558 +#define MT6392_DIGLDO_CON51 0x055A +#define MT6392_DIGLDO_CON52 0x055C +#define MT6392_DIGLDO_CON53 0x055E +#define MT6392_DIGLDO_CON54 0x0560 +#define MT6392_DIGLDO_CON55 0x0562 +#define MT6392_DIGLDO_CON56 0x0564 +#define MT6392_DIGLDO_CON57 0x0566 +#define MT6392_DIGLDO_CON58 0x0568 +#define MT6392_DIGLDO_CON59 0x056A +#define MT6392_DIGLDO_CON60 0x056C +#define MT6392_DIGLDO_CON61 0x056E +#define MT6392_DIGLDO_CON62 0x0570 +#define MT6392_DIGLDO_CON63 0x0572 +#define MT6392_EFUSE_CON0 0x0600 +#define MT6392_EFUSE_CON1 0x0602 +#define MT6392_EFUSE_CON2 0x0604 +#define MT6392_EFUSE_CON3 0x0606 +#define MT6392_EFUSE_CON4 0x0608 +#define MT6392_EFUSE_CON5 0x060A +#define MT6392_EFUSE_CON6 0x060C +#define MT6392_EFUSE_VAL_0_15 0x060E +#define MT6392_EFUSE_VAL_16_31 0x0610 +#define MT6392_EFUSE_VAL_32_47 0x0612 +#define MT6392_EFUSE_VAL_48_63 0x0614 +#define MT6392_EFUSE_VAL_64_79 0x0616 +#define MT6392_EFUSE_VAL_80_95 0x0618 +#define MT6392_EFUSE_VAL_96_111 0x061A +#define MT6392_EFUSE_VAL_112_127 0x061C +#define MT6392_EFUSE_VAL_128_143 0x061E +#define MT6392_EFUSE_VAL_144_159 0x0620 +#define MT6392_EFUSE_VAL_160_175 0x0622 +#define MT6392_EFUSE_VAL_176_191 0x0624 +#define MT6392_EFUSE_VAL_192_207 0x0626 +#define MT6392_EFUSE_VAL_208_223 0x0628 +#define MT6392_EFUSE_VAL_224_239 0x062A +#define MT6392_EFUSE_VAL_240_255 0x062C +#define MT6392_EFUSE_VAL_256_271 0x062E +#define MT6392_EFUSE_VAL_272_287 0x0630 +#define MT6392_EFUSE_VAL_288_303 0x0632 +#define MT6392_EFUSE_VAL_304_319 0x0634 +#define MT6392_EFUSE_VAL_320_335 0x0636 +#define MT6392_EFUSE_VAL_336_351 0x0638 +#define MT6392_EFUSE_VAL_352_367 0x063A +#define MT6392_EFUSE_VAL_368_383 0x063C +#define MT6392_EFUSE_VAL_384_399 0x063E +#define MT6392_EFUSE_VAL_400_415 0x0640 +#define MT6392_EFUSE_VAL_416_431 0x0642 +#define MT6392_RTC_MIX_CON0 0x0644 +#define MT6392_RTC_MIX_CON1 0x0646 +#define MT6392_EFUSE_VAL_432_447 0x0648 +#define MT6392_EFUSE_VAL_448_463 0x064A +#define MT6392_EFUSE_VAL_464_479 0x064C +#define MT6392_EFUSE_VAL_480_495 0x064E +#define MT6392_EFUSE_VAL_496_511 0x0650 +#define MT6392_EFUSE_DOUT_0_15 0x0652 +#define MT6392_EFUSE_DOUT_16_31 0x0654 +#define MT6392_EFUSE_DOUT_32_47 0x0656 +#define MT6392_EFUSE_DOUT_48_63 0x0658 +#define MT6392_EFUSE_DOUT_64_79 0x065A +#define MT6392_EFUSE_DOUT_80_95 0x065C +#define MT6392_EFUSE_DOUT_96_111 0x065E +#define MT6392_EFUSE_DOUT_112_127 0x0660 +#define MT6392_EFUSE_DOUT_128_143 0x0662 +#define MT6392_EFUSE_DOUT_144_159 0x0664 +#define MT6392_EFUSE_DOUT_160_175 0x0666 +#define MT6392_EFUSE_DOUT_176_191 0x0668 +#define MT6392_EFUSE_DOUT_192_207 0x066A +#define MT6392_EFUSE_DOUT_208_223 0x066C +#define MT6392_EFUSE_DOUT_224_239 0x066E +#define MT6392_EFUSE_DOUT_240_255 0x0670 +#define MT6392_EFUSE_DOUT_256_271 0x0672 +#define MT6392_EFUSE_DOUT_272_287 0x0674 +#define MT6392_EFUSE_DOUT_288_303 0x0676 +#define MT6392_EFUSE_DOUT_304_319 0x0678 +#define MT6392_EFUSE_DOUT_320_335 0x067A +#define MT6392_EFUSE_DOUT_336_351 0x067C +#define MT6392_EFUSE_DOUT_352_367 0x067E +#define MT6392_EFUSE_DOUT_368_383 0x0680 +#define MT6392_EFUSE_DOUT_384_399 0x0682 +#define MT6392_EFUSE_DOUT_400_415 0x0684 +#define MT6392_EFUSE_DOUT_416_431 0x0686 +#define MT6392_EFUSE_DOUT_432_447 0x0688 +#define MT6392_EFUSE_DOUT_448_463 0x068A +#define MT6392_EFUSE_DOUT_464_479 0x068C +#define MT6392_EFUSE_DOUT_480_495 0x068E +#define MT6392_EFUSE_DOUT_496_511 0x0690 +#define MT6392_EFUSE_CON7 0x0692 +#define MT6392_EFUSE_CON8 0x0694 +#define MT6392_EFUSE_CON9 0x0696 +#define MT6392_AUXADC_ADC0 0x0700 +#define MT6392_AUXADC_ADC1 0x0702 +#define MT6392_AUXADC_ADC2 0x0704 +#define MT6392_AUXADC_ADC3 0x0706 +#define MT6392_AUXADC_ADC4 0x0708 +#define MT6392_AUXADC_ADC5 0x070A +#define MT6392_AUXADC_ADC6 0x070C +#define MT6392_AUXADC_ADC7 0x070E +#define MT6392_AUXADC_ADC8 0x0710 +#define MT6392_AUXADC_ADC9 0x0712 +#define MT6392_AUXADC_ADC10 0x0714 +#define MT6392_AUXADC_ADC11 0x0716 +#define MT6392_AUXADC_ADC12 0x0718 +#define MT6392_AUXADC_ADC13 0x071A +#define MT6392_AUXADC_ADC14 0x071C +#define MT6392_AUXADC_ADC15 0x071E +#define MT6392_AUXADC_ADC16 0x0720 +#define MT6392_AUXADC_ADC17 0x0722 +#define MT6392_AUXADC_ADC18 0x0724 +#define MT6392_AUXADC_ADC19 0x0726 +#define MT6392_AUXADC_ADC20 0x0728 +#define MT6392_AUXADC_ADC21 0x072A +#define MT6392_AUXADC_ADC22 0x072C +#define MT6392_AUXADC_STA0 0x072E +#define MT6392_AUXADC_STA1 0x0730 +#define MT6392_AUXADC_RQST0 0x0732 +#define MT6392_AUXADC_RQST0_SET 0x0734 +#define MT6392_AUXADC_RQST0_CLR 0x0736 +#define MT6392_AUXADC_CON0 0x0738 +#define MT6392_AUXADC_CON0_SET 0x073A +#define MT6392_AUXADC_CON0_CLR 0x073C +#define MT6392_AUXADC_CON1 0x073E +#define MT6392_AUXADC_CON2 0x0740 +#define MT6392_AUXADC_CON3 0x0742 +#define MT6392_AUXADC_CON4 0x0744 +#define MT6392_AUXADC_CON5 0x0746 +#define MT6392_AUXADC_CON6 0x0748 +#define MT6392_AUXADC_CON7 0x074A +#define MT6392_AUXADC_CON8 0x074C +#define MT6392_AUXADC_CON9 0x074E +#define MT6392_AUXADC_CON10 0x0750 +#define MT6392_AUXADC_CON11 0x0752 +#define MT6392_AUXADC_CON12 0x0754 +#define MT6392_AUXADC_CON13 0x0756 +#define MT6392_AUXADC_CON14 0x0758 +#define MT6392_AUXADC_CON15 0x075A +#define MT6392_AUXADC_CON16 0x075C +#define MT6392_AUXADC_AUTORPT0 0x075E +#define MT6392_AUXADC_LBAT0 0x0760 +#define MT6392_AUXADC_LBAT1 0x0762 +#define MT6392_AUXADC_LBAT2 0x0764 +#define MT6392_AUXADC_LBAT3 0x0766 +#define MT6392_AUXADC_LBAT4 0x0768 +#define MT6392_AUXADC_LBAT5 0x076A +#define MT6392_AUXADC_LBAT6 0x076C +#define MT6392_AUXADC_THR0 0x076E +#define MT6392_AUXADC_THR1 0x0770 +#define MT6392_AUXADC_THR2 0x0772 +#define MT6392_AUXADC_THR3 0x0774 +#define MT6392_AUXADC_THR4 0x0776 +#define MT6392_AUXADC_THR5 0x0778 +#define MT6392_AUXADC_THR6 0x077A +#define MT6392_AUXADC_EFUSE0 0x077C +#define MT6392_AUXADC_EFUSE1 0x077E +#define MT6392_AUXADC_EFUSE2 0x0780 +#define MT6392_AUXADC_EFUSE3 0x0782 +#define MT6392_AUXADC_EFUSE4 0x0784 +#define MT6392_AUXADC_EFUSE5 0x0786 +#define MT6392_AUXADC_NAG_0 0x0788 +#define MT6392_AUXADC_NAG_1 0x078A +#define MT6392_AUXADC_NAG_2 0x078C +#define MT6392_AUXADC_NAG_3 0x078E +#define MT6392_AUXADC_NAG_4 0x0790 +#define MT6392_AUXADC_NAG_5 0x0792 +#define MT6392_AUXADC_NAG_6 0x0794 +#define MT6392_AUXADC_NAG_7 0x0796 +#define MT6392_AUXADC_NAG_8 0x0798 +#define MT6392_AUXADC_TYPEC_H_1 0x079A +#define MT6392_AUXADC_TYPEC_H_2 0x079C +#define MT6392_AUXADC_TYPEC_H_3 0x079E +#define MT6392_AUXADC_TYPEC_H_4 0x07A0 +#define MT6392_AUXADC_TYPEC_H_5 0x07A2 +#define MT6392_AUXADC_TYPEC_H_6 0x07A4 +#define MT6392_AUXADC_TYPEC_H_7 0x07A6 +#define MT6392_AUXADC_TYPEC_L_1 0x07A8 +#define MT6392_AUXADC_TYPEC_L_2 0x07AA +#define MT6392_AUXADC_TYPEC_L_3 0x07AC +#define MT6392_AUXADC_TYPEC_L_4 0x07AE +#define MT6392_AUXADC_TYPEC_L_5 0x07B0 +#define MT6392_AUXADC_TYPEC_L_6 0x07B2 +#define MT6392_AUXADC_TYPEC_L_7 0x07B4 +#define MT6392_AUXADC_NAG_9 0x07B6 +#define MT6392_TYPE_C_PHY_RG_0 0x0800 +#define MT6392_TYPE_C_PHY_RG_CC_RESERVE_CSR 0x0802 +#define MT6392_TYPE_C_VCMP_CTRL 0x0804 +#define MT6392_TYPE_C_CTRL 0x0806 +#define MT6392_TYPE_C_CC_SW_CTRL 0x080a +#define MT6392_TYPE_C_CC_VOL_PERIODIC_MEAS_VAL 0x080c +#define MT6392_TYPE_C_CC_VOL_DEBOUNCE_CNT_VAL 0x080e +#define MT6392_TYPE_C_DRP_SRC_CNT_VAL_0 0x0810 +#define MT6392_TYPE_C_DRP_SNK_CNT_VAL_0 0x0814 +#define MT6392_TYPE_C_DRP_TRY_CNT_VAL_0 0x0818 +#define MT6392_TYPE_C_CC_SRC_DEFAULT_DAC_VAL 0x0820 +#define MT6392_TYPE_C_CC_SRC_15_DAC_VAL 0x0822 +#define MT6392_TYPE_C_CC_SRC_30_DAC_VAL 0x0824 +#define MT6392_TYPE_C_CC_SNK_DAC_VAL_0 0x0828 +#define MT6392_TYPE_C_CC_SNK_DAC_VAL_1 0x082a +#define MT6392_TYPE_C_INTR_EN_0 0x0830 +#define MT6392_TYPE_C_INTR_EN_2 0x0834 +#define MT6392_TYPE_C_INTR_0 0x0838 +#define MT6392_TYPE_C_INTR_2 0x083C +#define MT6392_TYPE_C_CC_STATUS 0x0840 +#define MT6392_TYPE_C_PWR_STATUS 0x0842 +#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_0 0x0844 +#define MT6392_TYPE_C_PHY_RG_CC1_RESISTENCE_1 0x0846 +#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_0 0x0848 +#define MT6392_TYPE_C_PHY_RG_CC2_RESISTENCE_1 0x084a +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_0 0x0860 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_0 0x0864 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_1 0x0866 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_ENABLE_1 0x0868 +#define MT6392_TYPE_C_CC_SW_FORCE_MODE_VAL_2 0x086c +#define MT6392_TYPE_C_CC_DAC_CALI_CTRL 0x0870 +#define MT6392_TYPE_C_CC_DAC_CALI_RESULT 0x0872 +#define MT6392_TYPE_C_DEBUG_PORT_SELECT_0 0x0880 +#define MT6392_TYPE_C_DEBUG_PORT_SELECT_1 0x0882 +#define MT6392_TYPE_C_DEBUG_MODE_SELECT 0x0884 +#define MT6392_TYPE_C_DEBUG_OUT_READ_0 0x0888 +#define MT6392_TYPE_C_DEBUG_OUT_READ_1 0x088a +#define MT6392_TYPE_C_SW_DEBUG_PORT_0 0x088c +#define MT6392_TYPE_C_SW_DEBUG_PORT_1 0x088e + +#endif /* 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AngeloGioacchino Del Regno , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , Linus Walleij , Liam Girdwood , Mark Brown , Julien Massot , Gary Bisson , Louis-Alexis Eyraud , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 6/9] input: keyboard: mtk-pmic-keys: Add MT6392 support Date: Mon, 30 Mar 2026 09:29:40 +0100 Message-ID: <20260330083429.359819-7-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Val Packett Add support for the MT6392 PMIC to the keys driver. Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno Acked-by: Dmitry Torokhov --- drivers/input/keyboard/mtk-pmic-keys.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboar= d/mtk-pmic-keys.c index c78d9f6d97c4..8b4a89fce4fb 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -69,6 +70,19 @@ static const struct mtk_pmic_regs mt6397_regs =3D { .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, }; =20 +static const struct mtk_pmic_regs mt6392_regs =3D { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6392_CHRSTATUS, 0x2, + MT6392_INT_MISC_CON, 0x10, + MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6392_CHRSTATUS, 0x4, + MT6392_INT_MISC_CON, 0x8, + MTK_PMIC_HOMEKEY_RST), + .pmic_rst_reg =3D MT6392_TOP_RST_MISC, + .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6323_regs =3D { .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D MTK_PMIC_KEYS_REGS(MT6323_CHRSTATUS, @@ -301,6 +315,9 @@ static const struct of_device_id of_mtk_pmic_keys_match= _tbl[] =3D { { .compatible =3D "mediatek,mt6397-keys", .data =3D &mt6397_regs, + }, { + .compatible =3D "mediatek,mt6392-keys", + .data =3D &mt6392_regs, }, { .compatible =3D "mediatek,mt6323-keys", .data =3D &mt6323_regs, --=20 2.43.0 From nobody Thu Apr 2 05:49:35 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 219FA3AEF5D for ; Mon, 30 Mar 2026 08:36:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774859775; cv=none; b=qnRiYR/YNshY4Po1LETN4X1pYEBn2EOMVUFg6ZpYzCzUAiK7nNen4Sei88rNlLSz9WavXEbKGnXzIKK7R3CEbGuxXDscJusuf6/niO1zg6api4EQrlfaLAVMlLjuX3J0ru7Zpvjr4kDViYsM3DUip5zoaGTab0acv4AZUf/rwDc= ARC-Message-Signature: i=1; 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Mon, 30 Mar 2026 01:36:08 -0700 (PDT) Received: from luca-vm.lan ([154.61.61.58]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48722c6b495sm508329995e9.2.2026.03.30.01.36.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Mar 2026 01:36:08 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Fabien Parent , Val Packett , Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , Linus Walleij , Liam Girdwood , Mark Brown , Julien Massot , Louis-Alexis Eyraud , Gary Bisson , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 7/9] regulator: Add MediaTek MT6392 regulator Date: Mon, 30 Mar 2026 09:29:41 +0100 Message-ID: <20260330083429.359819-8-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Fabien Parent The MT6392 is a regulator found on boards based on the MediaTek MT8167, MT8516, and probably other SoCs. It is a so called PMIC and connects as a slave to a SoC using SPI, wrapped inside PWRAP. Signed-off-by: Fabien Parent Co-developed-by: Val Packett Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6392-regulator.c | 509 +++++++++++++++++++++ include/linux/regulator/mt6392-regulator.h | 42 ++ 4 files changed, 561 insertions(+) create mode 100644 drivers/regulator/mt6392-regulator.c create mode 100644 include/linux/regulator/mt6392-regulator.h diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index d10b6f9243d5..7ae06634a12b 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -1000,6 +1000,15 @@ config REGULATOR_MT6380 This driver supports the control of different power rails of device through regulator interface. =20 +config REGULATOR_MT6392 + tristate "MediaTek MT6392 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6392 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6397 tristate "MediaTek MT6397 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 35639f3115fd..e5f1fa91b967 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -118,6 +118,7 @@ obj-$(CONFIG_REGULATOR_MT6360) +=3D mt6360-regulator.o obj-$(CONFIG_REGULATOR_MT6363) +=3D mt6363-regulator.o obj-$(CONFIG_REGULATOR_MT6370) +=3D mt6370-regulator.o obj-$(CONFIG_REGULATOR_MT6380) +=3D mt6380-regulator.o +obj-$(CONFIG_REGULATOR_MT6392) +=3D mt6392-regulator.o obj-$(CONFIG_REGULATOR_MT6397) +=3D mt6397-regulator.o obj-$(CONFIG_REGULATOR_MTK_DVFSRC) +=3D mtk-dvfsrc-regulator.o obj-$(CONFIG_REGULATOR_QCOM_LABIBB) +=3D qcom-labibb-regulator.o diff --git a/drivers/regulator/mt6392-regulator.c b/drivers/regulator/mt639= 2-regulator.c new file mode 100644 index 000000000000..6e0278bded92 --- /dev/null +++ b/drivers/regulator/mt6392-regulator.c @@ -0,0 +1,509 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2020 MediaTek Inc. +// Copyright (c) 2020 BayLibre, SAS. +// Author: Chen Zhong +// Author: Fabien Parent +// +// Based on mt6397-regulator.c + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * MT6392 regulators' information + * + * @desc: standard fields of regulator description. + * @qi: Mask for query enable signal status of regulators + * @vselon_reg: Register sections for hardware control mode of bucks + * @vselctrl_reg: Register for controlling the buck control mode. + * @vselctrl_mask: Mask for query buck's voltage control mode. + */ +struct mt6392_regulator_info { + struct regulator_desc desc; + u32 qi; + u32 vselon_reg; + u32 vselctrl_reg; + u32 vselctrl_mask; + u32 modeset_reg; + u32 modeset_mask; +}; + +#define MT6392_BUCK(match, vreg, supply, min, max, step, volt_ranges, \ + enreg, vosel_reg, vosel_mask, voselon_reg, vosel_ctrl, \ + _modeset_reg, _modeset_mask, rampdelay) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .supply_name =3D supply, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .ops =3D &mt6392_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ((max) - (min)) / (step) + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel_reg, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + .ramp_delay =3D rampdelay, \ + }, \ + .qi =3D BIT(13), \ + .vselon_reg =3D voselon_reg, \ + .vselctrl_reg =3D vosel_ctrl, \ + .vselctrl_mask =3D BIT(1), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_LDO(match, vreg, supply, ldo_volt_table, enreg, enbit, \ + vosel_reg, vosel_mask, _modeset_reg, _modeset_mask, \ + entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .supply_name =3D supply, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .ops =3D &mt6392_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel_reg, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_LDO_LINEAR(match, vreg, supply, min, max, step, \ + volt_ranges, enreg, enbit, vosel_reg, vosel_mask, \ + _modeset_reg, _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .supply_name =3D supply, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .ops =3D &mt6392_volt_ldo_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ((max) - (min)) / (step) + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel_reg, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_REG_FIXED(match, vreg, supply, enreg, enbit, volt, \ + _modeset_reg, _modeset_mask, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .supply_name =3D supply, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .ops =3D &mt6392_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ + .modeset_reg =3D _modeset_reg, \ + .modeset_mask =3D _modeset_mask, \ +} + +#define MT6392_REG_FIXED_NO_MODE(match, vreg, supply, enreg, enbit, \ + volt, entime) \ +[MT6392_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .supply_name =3D supply, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .ops =3D &mt6392_volt_fixed_no_mode_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6392_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(enbit), \ + .enable_time =3D entime, \ + .min_uV =3D volt, \ + }, \ + .qi =3D BIT(15), \ +} + +static const struct linear_range buck_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500), +}; + +static const u32 ldo_volt_table1[] =3D { + 1800000, 1900000, 2000000, 2200000, +}; + +static const u32 ldo_volt_table1b[] =3D { + 1500000, 1800000, 2500000, 2800000, +}; + +static const struct linear_range ldo_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(3300000, 0, 3, 100000), +}; + +static const u32 ldo_volt_table3[] =3D { + 1800000, 3300000, +}; + +static const u32 ldo_volt_table4[] =3D { + 3000000, 3300000, +}; + +static const u32 ldo_volt_table5[] =3D { + 1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000, +}; + +static const u32 ldo_volt_table6[] =3D { + 1240000, 1390000, +}; + +static const u32 ldo_volt_table7[] =3D { + 1200000, 1300000, 1500000, 1800000, +}; + +static const u32 ldo_volt_table8[] =3D { + 1800000, 2000000, +}; + +static int mt6392_buck_set_mode(struct regulator_dev *rdev, unsigned int m= ode) +{ + int ret, val =3D 0; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_FAST: + val =3D MT6392_BUCK_MODE_FORCE_PWM; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6392_BUCK_MODE_AUTO; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_buck_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_FAST; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static int mt6392_ldo_set_mode(struct regulator_dev *rdev, unsigned int mo= de) +{ + int ret, val =3D 0; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + switch (mode) { + case REGULATOR_MODE_STANDBY: + val =3D MT6392_LDO_MODE_LP; + break; + case REGULATOR_MODE_NORMAL: + val =3D MT6392_LDO_MODE_NORMAL; + break; + default: + return -EINVAL; + } + + val <<=3D ffs(info->modeset_mask) - 1; + + ret =3D regmap_update_bits(rdev->regmap, info->modeset_reg, + info->modeset_mask, val); + + return ret; +} + +static unsigned int mt6392_ldo_get_mode(struct regulator_dev *rdev) +{ + unsigned int val; + unsigned int mode; + int ret; + struct mt6392_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->modeset_reg, &val); + if (ret < 0) + return ret; + + val &=3D info->modeset_mask; + val >>=3D ffs(info->modeset_mask) - 1; + + if (val & 0x1) + mode =3D REGULATOR_MODE_STANDBY; + else + mode =3D REGULATOR_MODE_NORMAL; + + return mode; +} + +static const struct regulator_ops mt6392_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_buck_set_mode, + .get_mode =3D mt6392_buck_get_mode, +}; + +static const struct regulator_ops mt6392_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_ldo_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, + .set_mode =3D mt6392_ldo_set_mode, + .get_mode =3D mt6392_ldo_get_mode, +}; + +static const struct regulator_ops mt6392_volt_fixed_no_mode_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, +}; + +/* The array is indexed by id(MT6392_ID_XXX) */ +static struct mt6392_regulator_info mt6392_regulators[] =3D { + MT6392_BUCK("vproc", VPROC, "vproc", 700000, 1493750, 6250, + buck_volt_range1, MT6392_VPROC_CON7, MT6392_VPROC_CON9, 0x7f, + MT6392_VPROC_CON10, MT6392_VPROC_CON5, MT6392_VPROC_CON2, 0x100, + 12500), + MT6392_BUCK("vsys", VSYS, "vsys", 1400000, 2987500, 12500, + buck_volt_range2, MT6392_VSYS_CON7, MT6392_VSYS_CON9, 0x7f, + MT6392_VSYS_CON10, MT6392_VSYS_CON5, MT6392_VSYS_CON2, 0x100, + 25000), + MT6392_BUCK("vcore", VCORE, "vcore", 700000, 1493750, 6250, + buck_volt_range1, MT6392_VCORE_CON7, MT6392_VCORE_CON9, 0x7f, + MT6392_VCORE_CON10, MT6392_VCORE_CON5, MT6392_VCORE_CON2, 0x100, + 12500), + MT6392_REG_FIXED("vxo22", VXO22, "ldo1", MT6392_ANALDO_CON1, 10, 2200000, + MT6392_ANALDO_CON1, 0x2, 110), + MT6392_LDO("vaud22", VAUD22, "ldo1", ldo_volt_table1, + MT6392_ANALDO_CON2, 14, MT6392_ANALDO_CON8, 0x60, + MT6392_ANALDO_CON2, 0x2, 264), + MT6392_REG_FIXED_NO_MODE("vcama", VCAMA, "ldo1", MT6392_ANALDO_CON4, 15, + 2800000, 264), + MT6392_REG_FIXED("vaud28", VAUD28, "ldo1", MT6392_ANALDO_CON23, 14, 28000= 00, + MT6392_ANALDO_CON23, 0x2, 264), + MT6392_REG_FIXED("vadc18", VADC18, "ldo1", MT6392_ANALDO_CON25, 14, 18000= 00, + MT6392_ANALDO_CON25, 0x2, 264), + MT6392_LDO_LINEAR("vcn35", VCN35, "ldo2", 3300000, 3600000, 100000, + ldo_volt_range2, MT6392_ANALDO_CON21, 12, + MT6392_ANALDO_CON16, 0xC, MT6392_ANALDO_CON21, 0x2, 264), + MT6392_REG_FIXED("vio28", VIO28, "ldo2", MT6392_DIGLDO_CON0, 14, 2800000, + MT6392_DIGLDO_CON0, 0x2, 264), + MT6392_REG_FIXED("vusb", VUSB, "ldo3", MT6392_DIGLDO_CON2, 14, 3300000, + MT6392_DIGLDO_CON2, 0x2, 264), + MT6392_LDO("vmc", VMC, "ldo2", ldo_volt_table3, + MT6392_DIGLDO_CON3, 12, MT6392_DIGLDO_CON24, 0x10, + MT6392_DIGLDO_CON3, 0x2, 264), + MT6392_LDO("vmch", VMCH, "ldo2", ldo_volt_table4, + MT6392_DIGLDO_CON5, 14, MT6392_DIGLDO_CON26, 0x80, + MT6392_DIGLDO_CON5, 0x2, 264), + MT6392_LDO("vemc3v3", VEMC3V3, "ldo3", ldo_volt_table4, + MT6392_DIGLDO_CON6, 14, MT6392_DIGLDO_CON27, 0x80, + MT6392_DIGLDO_CON6, 0x2, 264), + MT6392_LDO("vgp1", VGP1, "ldo3", ldo_volt_table5, + MT6392_DIGLDO_CON7, 15, MT6392_DIGLDO_CON28, 0xE0, + MT6392_DIGLDO_CON7, 0x2, 264), + MT6392_LDO("vgp2", VGP2, "ldo3", ldo_volt_table5, + MT6392_DIGLDO_CON8, 15, MT6392_DIGLDO_CON29, 0xE0, + MT6392_DIGLDO_CON8, 0x2, 264), + MT6392_REG_FIXED("vcn18", VCN18, "avddldo", MT6392_DIGLDO_CON11, 14, 1800= 000, + MT6392_DIGLDO_CON11, 0x2, 264), + MT6392_LDO("vcamaf", VCAMAF, "ldo3", ldo_volt_table5, + MT6392_DIGLDO_CON31, 15, MT6392_DIGLDO_CON32, 0xE0, + MT6392_DIGLDO_CON31, 0x2, 264), + MT6392_LDO("vm", VM, "avddldo", ldo_volt_table6, + MT6392_DIGLDO_CON47, 14, MT6392_DIGLDO_CON48, 0x30, + MT6392_DIGLDO_CON47, 0x2, 264), + MT6392_REG_FIXED("vio18", VIO18, "avddldo", MT6392_DIGLDO_CON49, 14, 1800= 000, + MT6392_DIGLDO_CON49, 0x2, 264), + MT6392_LDO("vcamd", VCAMD, "avddldo", ldo_volt_table7, + MT6392_DIGLDO_CON51, 14, MT6392_DIGLDO_CON52, 0x60, + MT6392_DIGLDO_CON51, 0x2, 264), + MT6392_REG_FIXED("vcamio", VCAMIO, "avddldo", MT6392_DIGLDO_CON53, 14, 18= 00000, + MT6392_DIGLDO_CON53, 0x2, 264), + MT6392_REG_FIXED("vm25", VM25, "ldo3", MT6392_DIGLDO_CON55, 14, 2500000, + MT6392_DIGLDO_CON55, 0x2, 264), + MT6392_LDO("vefuse", VEFUSE, "ldo2", ldo_volt_table8, + MT6392_DIGLDO_CON57, 14, MT6392_DIGLDO_CON58, 0x10, + MT6392_DIGLDO_CON57, 0x2, 264), + MT6392_REG_FIXED_NO_MODE("vdig18", VDIG18, "ldo2", MT6392_DIGLDO_CON12, 1= 5, + 1800000, 264), + MT6392_REG_FIXED_NO_MODE("vrtc", VRTC, "ldo1", MT6392_DIGLDO_CON15, 15, + 2800000, 264) +}; + +static int mt6392_set_buck_vosel_reg(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 =3D dev_get_drvdata(pdev->dev.parent); + int i; + u32 regval; + + for (i =3D 0; i < MT6392_MAX_REGULATOR; i++) { + if (mt6392_regulators[i].vselctrl_reg) { + if (regmap_read(mt6392->regmap, + mt6392_regulators[i].vselctrl_reg, + ®val) < 0) { + dev_err(&pdev->dev, + "Failed to read buck ctrl\n"); + return -EIO; + } + + if (regval & mt6392_regulators[i].vselctrl_mask) { + mt6392_regulators[i].desc.vsel_reg =3D + mt6392_regulators[i].vselon_reg; + } + } + } + + return 0; +} + +static int mt6392_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6392 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + + pdev->dev.of_node =3D pdev->dev.parent->of_node; + + /* Query buck controller to select activated voltage register part */ + if (mt6392_set_buck_vosel_reg(pdev)) + return -EIO; + + config.dev =3D mt6392->dev; + config.regmap =3D mt6392->regmap; + for (i =3D 0; i < MT6392_MAX_REGULATOR; i++) { + config.driver_data =3D &mt6392_regulators[i]; + + rdev =3D devm_regulator_register(&pdev->dev, + &mt6392_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6392_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6392_platform_ids[] =3D { + {"mt6392-regulator", 0}, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6392_platform_ids); + +static struct platform_driver mt6392_regulator_driver =3D { + .driver =3D { + .name =3D "mt6392-regulator", + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, + .probe =3D mt6392_regulator_probe, + .id_table =3D mt6392_platform_ids, +}; + +module_platform_driver(mt6392_regulator_driver); + +MODULE_AUTHOR("Chen Zhong "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6392 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6392-regulator.h b/include/linux/reg= ulator/mt6392-regulator.h new file mode 100644 index 000000000000..0eccd085b062 --- /dev/null +++ b/include/linux/regulator/mt6392-regulator.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019 MediaTek Inc. + * Author: Chen Zhong + */ + +#ifndef __LINUX_REGULATOR_MT6392_H +#define __LINUX_REGULATOR_MT6392_H + +enum { + MT6392_ID_VPROC =3D 0, + MT6392_ID_VSYS, + MT6392_ID_VCORE, + MT6392_ID_VXO22, + MT6392_ID_VAUD22, + MT6392_ID_VCAMA, + MT6392_ID_VAUD28, + MT6392_ID_VADC18, + MT6392_ID_VCN35, + MT6392_ID_VIO28, + MT6392_ID_VUSB =3D 10, + MT6392_ID_VMC, + MT6392_ID_VMCH, + MT6392_ID_VEMC3V3, + MT6392_ID_VGP1, + MT6392_ID_VGP2, + MT6392_ID_VCN18, + MT6392_ID_VCAMAF, + MT6392_ID_VM, + MT6392_ID_VIO18, + MT6392_ID_VCAMD, + MT6392_ID_VCAMIO, + MT6392_ID_VM25, + MT6392_ID_VEFUSE, + MT6392_ID_VDIG18, + MT6392_ID_VRTC, + MT6392_ID_RG_MAX, +}; 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Mon, 30 Mar 2026 01:36:21 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Luca Leonardo Scorcia , AngeloGioacchino Del Regno , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , Linus Walleij , Liam Girdwood , Mark Brown , Louis-Alexis Eyraud , Val Packett , Julien Massot , Gary Bisson , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 8/9] pinctrl: mediatek: mt6397: Add MediaTek MT6392 Date: Mon, 30 Mar 2026 09:29:42 +0100 Message-ID: <20260330083429.359819-9-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the MT6392 pinctrl device, which is very similar to MT6397 with a handful of different property values and its own pins definition. Update the MT6397 driver to retrieve device data from the match table and use it for driver init. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-mt6397.c | 37 ++++++++++- drivers/pinctrl/mediatek/pinctrl-mtk-mt6392.h | 64 +++++++++++++++++++ 2 files changed, 99 insertions(+), 2 deletions(-) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6392.h diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/me= diatek/pinctrl-mt6397.c index 03d0f65d7bcc..8ba02e70595c 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -12,10 +12,32 @@ #include =20 #include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt6392.h" #include "pinctrl-mtk-mt6397.h" =20 #define MT6397_PIN_REG_BASE 0xc000 =20 +static const struct mtk_pinctrl_devdata mt6392_pinctrl_data =3D { + .pins =3D mtk_pins_mt6392, + .npins =3D ARRAY_SIZE(mtk_pins_mt6392), + .dir_offset =3D (MT6397_PIN_REG_BASE + 0x000), + .ies_offset =3D MTK_PINCTRL_NOT_SUPPORT, + .smt_offset =3D MTK_PINCTRL_NOT_SUPPORT, + .pullen_offset =3D (MT6397_PIN_REG_BASE + 0x020), + .pullsel_offset =3D (MT6397_PIN_REG_BASE + 0x040), + .dout_offset =3D (MT6397_PIN_REG_BASE + 0x080), + .din_offset =3D (MT6397_PIN_REG_BASE + 0x0a0), + .pinmux_offset =3D (MT6397_PIN_REG_BASE + 0x0c0), + .type1_start =3D 7, + .type1_end =3D 7, + .port_shf =3D 3, + .port_mask =3D 0x3, + .port_align =3D 2, + .mode_mask =3D 0xf, + .mode_per_reg =3D 5, + .mode_shf =3D 4, +}; + static const struct mtk_pinctrl_devdata mt6397_pinctrl_data =3D { .pins =3D mtk_pins_mt6397, .npins =3D ARRAY_SIZE(mtk_pins_mt6397), @@ -40,13 +62,24 @@ static const struct mtk_pinctrl_devdata mt6397_pinctrl_= data =3D { static int mt6397_pinctrl_probe(struct platform_device *pdev) { struct mt6397_chip *mt6397; + const struct mtk_pinctrl_devdata *data; + + data =3D device_get_match_data(&pdev->dev); + if (!data) + return -ENOENT; =20 mt6397 =3D dev_get_drvdata(pdev->dev.parent); - return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap); + return mtk_pctrl_init(pdev, data, mt6397->regmap); } =20 static const struct of_device_id mt6397_pctrl_match[] =3D { - { .compatible =3D "mediatek,mt6397-pinctrl", }, + { + .compatible =3D "mediatek,mt6392-pinctrl", + .data =3D &mt6392_pinctrl_data + }, { + .compatible =3D "mediatek,mt6397-pinctrl", + .data =3D &mt6397_pinctrl_data + }, { } }; =20 diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6392.h b/drivers/pinctr= l/mediatek/pinctrl-mtk-mt6392.h new file mode 100644 index 000000000000..e7241af28fdb --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6392.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __PINCTRL_MTK_MT6392_H +#define __PINCTRL_MTK_MT6392_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt6392[] =3D { + MTK_PIN(PINCTRL_PIN(0, "INT"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "INT"), + MTK_FUNCTION(5, "TEST_CK2"), + MTK_FUNCTION(6, "TEST_IN1"), + MTK_FUNCTION(7, "TEST_OUT1") + ), + MTK_PIN(PINCTRL_PIN(1, "SRCLKEN"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SRCLKEN"), + MTK_FUNCTION(5, "TEST_CK0"), + MTK_FUNCTION(6, "TEST_IN2"), + MTK_FUNCTION(7, "TEST_OUT2") + ), + MTK_PIN(PINCTRL_PIN(2, "RTC_32K1V8"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "RTC_32K1V8"), + MTK_FUNCTION(5, "TEST_CK1"), + MTK_FUNCTION(6, "TEST_IN3"), + MTK_FUNCTION(7, "TEST_OUT3") + ), + MTK_PIN(PINCTRL_PIN(3, "SPI_CLK"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SPI_CLK") + ), + MTK_PIN(PINCTRL_PIN(4, "SPI_CSN"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "SPI_CSN") + ), + MTK_PIN(PINCTRL_PIN(5, "SPI_MOSI"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI_MOSI") + ), + MTK_PIN(PINCTRL_PIN(6, "SPI_MISO"), + NULL, "mt6392", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI_MISO"), + MTK_FUNCTION(6, "TEST_IN4"), + MTK_FUNCTION(7, "TEST_OUT4") + ), +}; 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Mon, 30 Mar 2026 01:36:33 -0700 (PDT) From: Luca Leonardo Scorcia To: linux-mediatek@lists.infradead.org Cc: Val Packett , Luca Leonardo Scorcia , Dmitry Torokhov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Matthias Brugger , AngeloGioacchino Del Regno , Linus Walleij , Liam Girdwood , Mark Brown , Julien Massot , Louis-Alexis Eyraud , Gary Bisson , Fabien Parent , Chen Zhong , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org Subject: [PATCH v4 9/9] arm64: dts: mediatek: Add MediaTek MT6392 PMIC dtsi Date: Mon, 30 Mar 2026 09:29:43 +0100 Message-ID: <20260330083429.359819-10-l.scorcia@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260330083429.359819-1-l.scorcia@gmail.com> References: <20260330083429.359819-1-l.scorcia@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Val Packett Add the dts to be included by all boards using the MT6392 PMIC. Signed-off-by: Val Packett Signed-off-by: Luca Leonardo Scorcia --- arch/arm64/boot/dts/mediatek/mt6392.dtsi | 73 ++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6392.dtsi diff --git a/arch/arm64/boot/dts/mediatek/mt6392.dtsi b/arch/arm64/boot/dts= /mediatek/mt6392.dtsi new file mode 100644 index 000000000000..750ee9b2856f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6392.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. + * Copyright (c) 2024 Val Packett + */ + +#include + +&pwrap { + pmic: pmic { + compatible =3D "mediatek,mt6392", "mediatek,mt6323"; + interrupt-controller; + #interrupt-cells =3D <2>; + + keys { + compatible =3D "mediatek,mt6392-keys"; + + key-power { + linux,keycodes =3D ; + wakeup-source; + }; + + key-home { + linux,keycodes =3D ; + wakeup-source; + }; + }; + + pio6392: pinctrl { + compatible =3D "mediatek,mt6392-pinctrl"; + + gpio-controller; + #gpio-cells =3D <2>; + }; + + rtc { + compatible =3D "mediatek,mt6392-rtc", + "mediatek,mt6323-rtc"; + }; + + mt6392regulators: regulators { + /* Fixed supply defined in the data sheet */ + avddldo-supply =3D <&mt6392_vsys_reg>; + + mt6392_vcore_reg: vcore { }; + mt6392_vproc_reg: vproc { }; + mt6392_vsys_reg: vsys { }; + mt6392_vaud28_reg: vaud28 { }; + mt6392_vxo22_reg: vxo22 { }; + mt6392_vaud22_reg: vaud22 { }; + mt6392_vadc18_reg: vadc18 { }; + mt6392_vcama_reg: vcama { }; + mt6392_vcn35_reg: vcn35 { }; + mt6392_vio28_reg: vio28 { }; + mt6392_vusb_reg: vusb { }; + mt6392_vmc_reg: vmc { }; + mt6392_vmch_reg: vmch { }; + mt6392_vemc3v3_reg: vemc3v3 { }; + mt6392_vcamaf_reg: vcamaf { }; + mt6392_vgp1_reg: vgp1 { }; + mt6392_vgp2_reg: vgp2 { }; + mt6392_vefuse_reg: vefuse { }; + mt6392_vm25_reg: vm25 { }; + mt6392_vdig18_reg: vdig18 { }; + mt6392_vm_reg: vm { }; + mt6392_vio18_reg: vio18 { }; + mt6392_vcn18_reg: vcn18 { }; + mt6392_vcamd_reg: vcamd { }; + mt6392_vcamio_reg: vcamio { }; + mt6392_vrtc_reg: vrtc { }; + }; + }; +}; --=20 2.43.0