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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260330-t264-pwm-v3-5-5714427d5976@nvidia.com> References: <20260330-t264-pwm-v3-0-5714427d5976@nvidia.com> In-Reply-To: <20260330-t264-pwm-v3-0-5714427d5976@nvidia.com> To: Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Yi-Wei Wang , Thierry Reding , Mikko Perttunen X-Mailer: b4 0.14.3 X-ClientProxiedBy: MW4PR03CA0243.namprd03.prod.outlook.com (2603:10b6:303:b4::8) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ2PR12MB9161:EE_|DM6PR12MB4281:EE_ X-MS-Office365-Filtering-Correlation-Id: f78e1590-283a-4e6a-e9b0-08de8e39e87d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|10070799003|366016|1800799024|22082099003|56012099003|18002099003; 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Parameterize the driver in preparation. The depth value also becomes disconnected from the width of the duty field, so define it separately. Co-developed-by: Yi-Wei Wang Signed-off-by: Yi-Wei Wang Reviewed-by: Thierry Reding Signed-off-by: Mikko Perttunen --- drivers/pwm/pwm-tegra.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 22d709986e8c..857301baad51 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -52,16 +52,19 @@ #include =20 #define PWM_ENABLE (1 << 31) -#define PWM_DUTY_WIDTH 8 #define PWM_DUTY_SHIFT 16 -#define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 =20 #define PWM_CSR_0 0 =20 +#define PWM_DEPTH 256 + struct tegra_pwm_soc { unsigned int num_channels; unsigned int enable_reg; + + unsigned int duty_width; + unsigned int scale_width; }; =20 struct tegra_pwm_chip { @@ -106,22 +109,22 @@ static int tegra_pwm_config(struct pwm_chip *chip, st= ruct pwm_device *pwm, =20 /* * Convert from duty_ns / period_ns to a fixed number of duty ticks - * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the + * per PWM_DEPTH cycles and make sure to round to the * nearest integer during division. */ - c *=3D (1 << PWM_DUTY_WIDTH); + c *=3D PWM_DEPTH; c =3D DIV_ROUND_CLOSEST_ULL(c, period_ns); =20 val =3D (u32)c << PWM_DUTY_SHIFT; =20 /* - * min period =3D max clock limit >> PWM_DUTY_WIDTH + * min period =3D max clock limit / PWM_DEPTH */ if (period_ns < pc->min_period_ns) return -EINVAL; =20 /* - * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH) + * Compute the prescaler value for which PWM_DEPTH * cycles at the PWM clock rate will take period_ns nanoseconds. * * num_channels: If single instance of PWM controller has multiple @@ -135,7 +138,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, */ if (pc->soc->num_channels =3D=3D 1) { /* - * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches + * Rate is multiplied with PWM_DEPTH so that it matches * with the maximum possible rate that the controller can * provide. Any further lower value can be derived by setting * PFM bits[0:12]. @@ -145,7 +148,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, * source clock rate as required_clk_rate, PWM controller will * be able to configure the requested period. */ - required_clk_rate =3D DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC << PWM_DUTY_WID= TH, + required_clk_rate =3D DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * PWM_DEPTH, period_ns); =20 if (required_clk_rate > clk_round_rate(pc->clk, required_clk_rate)) @@ -169,7 +172,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, =20 /* Consider precision in PWM_SCALE_WIDTH rate calculation */ rate =3D mul_u64_u64_div_u64(pc->clk_rate, period_ns, - (u64)NSEC_PER_SEC << PWM_DUTY_WIDTH); + (u64)NSEC_PER_SEC * PWM_DEPTH); =20 /* * Since the actual PWM divider is the register's frequency divider @@ -185,7 +188,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, stru= ct pwm_device *pwm, * Make sure that the rate will fit in the register's frequency * divider field. */ - if (rate >> PWM_SCALE_WIDTH) + if (rate >> pc->soc->scale_width) return -EINVAL; =20 val |=3D rate << PWM_SCALE_SHIFT; @@ -324,7 +327,7 @@ static int tegra_pwm_probe(struct platform_device *pdev) =20 /* Set minimum limit of PWM period for the IP */ pc->min_period_ns =3D - (NSEC_PER_SEC / (pc->clk_rate >> PWM_DUTY_WIDTH)) + 1; + (NSEC_PER_SEC / (pc->clk_rate / PWM_DEPTH)) + 1; =20 pc->rst =3D devm_reset_control_get_exclusive(&pdev->dev, "pwm"); if (IS_ERR(pc->rst)) { @@ -404,11 +407,15 @@ static int __maybe_unused tegra_pwm_runtime_resume(st= ruct device *dev) static const struct tegra_pwm_soc tegra20_pwm_soc =3D { .num_channels =3D 4, .enable_reg =3D PWM_CSR_0, + .duty_width =3D 8, + .scale_width =3D 13, }; =20 static const struct tegra_pwm_soc tegra186_pwm_soc =3D { .num_channels =3D 1, .enable_reg =3D PWM_CSR_0, + .duty_width =3D 8, + .scale_width =3D 13, }; =20 static const struct of_device_id tegra_pwm_of_match[] =3D { --=20 2.53.0