From nobody Thu Apr 2 09:13:07 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A560B393DF7; Mon, 30 Mar 2026 06:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774852645; cv=none; b=q2ASOdA+ig+Y6QZ9JmQm2Nwyc3+cxmDYwelCqXizriR3ZeafN9mBeUC7E1B2siHKdklunb9BtnMcd0ZrNavrFna/icpkI/3qhpz8PaPAeph1JDfVErLBG94SynHYRkStyIyxGTkulIM8Jx7x8M+2ZvxcB7VQEQuW+OIA5E6qRPg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774852645; c=relaxed/simple; bh=kQvAzVUVrDuNhd8V/zx0ZUqXw5mMTgMh6/foOcGUKZk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GH3x6+8F9uXjmyWPUi9LxJ46FvFd11I0sQE+nU0S+Gd5afkkvvTuF7HyoUIDlXDXooZ+jAyPMscV2kwFCZ2wtTBUZk6XHk8aa9eZ9NgfCR4lG0fHRuL2l80aXa8/Z1l2M5j9ZNp4kYaBAkO1UE4zb60VFjVMyfI62J21Eep9CmU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 30 Mar 2026 14:32:10 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 30 Mar 2026 14:32:10 +0800 From: Ryan Chen Date: Mon, 30 Mar 2026 14:32:10 +0800 Subject: [PATCH v4 1/4] dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260330-irqchip-v4-1-3c0f1620cc06@aspeedtech.com> References: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , "Alexandre Ghiti" , Thomas Gleixner , Thomas Gleixner CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774852330; l=13458; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=kQvAzVUVrDuNhd8V/zx0ZUqXw5mMTgMh6/foOcGUKZk=; b=r0q19cTU3ABJeNS3VIGq0kmV7gDDde459WXHRl2a0J0jQDbshPG2Cl+1TF++ywLXcSa1qQDeQ m8PeCPLfAR4B2vhQxCUKd4xJXTYI1NFVINBBneEv6p9on4I0QlWQNyP X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= Introduce a new binding describing the AST2700 interrupt controller architecture implemented in the A2 production silicon. The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2) prior to mass production. The interrupt architecture was substantially reworked after the A0 revision for A1, and the A1 design is retained unchanged in the A2 production silicon. The existing AST2700 interrupt controller binding ("aspeed,ast2700-intc-ic")was written against the pre-production A0 design. That binding does not accurately describe the interrupt hierarchy and routing model present in A1/A2, where interrupts can be routed to multiple processor-local interrupt controllers (Primary Service Processor (PSP) GIC, Secondary Service Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU APLIC) depending on the execution context. Remove the binding for the pre-production A0 design in favour of the binding for the A2 production design. There is no significant user impact from the removal as there are no existing devicetrees in any of Linux, u-boot or Zephyr that make use of the A0 binding. Hardware connectivity between interrupt controllers is expressed using the aspeed,interrupt-ranges property. Signed-off-by: Ryan Chen --- Changes in v3: - squash patch 5/5. - modify wrap lines at 80 char. - modify maintainers name and email. - modify typo Sevice-> Service Changes in v2: - Describe AST2700 A0/A1/A2 design evolution. - Drop the redundant '-ic' suffix from compatible strings. - Expand commit message to match the series cover letter context. - fix ascii diagram - remove intc0 label - remove spaces before > - drop intc1 example --- .../interrupt-controller/aspeed,ast2700-intc.yaml | 90 ---------- .../aspeed,ast2700-interrupt.yaml | 188 +++++++++++++++++= ++++ 2 files changed, 188 insertions(+), 90 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/= aspeed,ast2700-intc.yaml deleted file mode 100644 index 258d21fe6e35..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -intc.yaml +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= c.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Aspeed AST2700 Interrupt Controller - -description: - This interrupt controller hardware is second level interrupt controller = that - is hooked to a parent interrupt controller. It's useful to combine multi= ple - interrupt sources into 1 interrupt to parent interrupt controller. - -maintainers: - - Kevin Chen - -properties: - compatible: - enum: - - aspeed,ast2700-intc-ic - - reg: - maxItems: 1 - - interrupt-controller: true - - '#interrupt-cells': - const: 1 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - minItems: 1 - maxItems: 10 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable an= d raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 - -required: - - compatible - - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts - -additionalProperties: false - -examples: - - | - #include - - bus { - #address-cells =3D <2>; - #size-cells =3D <2>; - - interrupt-controller@12101b00 { - compatible =3D "aspeed,ast2700-intc-ic"; - reg =3D <0 0x12101b00 0 0x10>; - #interrupt-cells =3D <1>; - interrupt-controller; - interrupts =3D , - , - , - , - , - , - , - , - , - ; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,= ast2700-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-contro= ller/aspeed,ast2700-interrupt.yaml new file mode 100644 index 000000000000..a62f0fd2435b --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700= -interrupt.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int= errupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1) + +description: | + The ASPEED AST2700 SoC integrates two interrupt controller designs: + + - INTC0: Primary controller that routes interrupt sources to upstream, + processor-specific interrupt controllers + + - INTC1: Secondary controller whose interrupt outputs feed into INTC0 + + The SoC contains four processors to which interrupts can be routed: + + - PSP: Primary Service Processor (Cortex-A35) + - SSP: Secondary Service Processor (Cortex-M4) + - TSP: Tertiary Service Processor (Cortex-M4) + - BMCU: Boot MCU (a RISC-V microcontroller) + + The following diagram illustrates the overall architecture of the + ASPEED AST2700 interrupt controllers: + + +-----------+ +-----------+ + | INTC0 | | INTC1(0) | + +-----------+ +-----------+ + | Router | +-----------+ | Router | + | out int | +Peripheral + | out int | + +-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+ + |PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral + + +-----------+ | . . | | . . | +Controllers+ + +-----------+ | . . | | . . | +-----------+ + |SSP NVIC <-|---+ . . <----------------+ . . | + +-----------+ | . . | | . . | + +-----------+ | . . <-------- | . . | + |TSP NVIC <-|---+ . . | | ----+ . . | + +-----------+ | . . | | | | O P | + | . . | | | +-----------+ + | . . <---- | -------------------- + | . . | | | +-----------+ | + | M N | | ---------+ INTC1(1) | | + +-----------+ | +-----------+ | + | . | + | +-----------+ | + -------------+ INTC1(N) | | + +-----------+ | + +--------------+ | + + BMCU APLIC <-+--------------------------------------------- + +--------------+ + + INTC0 supports: + - 128 local peripheral interrupt inputs + - Fan-in from up to three INTC1 instances via banked interrupt lines (= INTM) + - Local peripheral interrupt outputs + - Merged interrupt outputs + - Software interrupt outputs (SWINT) + - Configurable interrupt routes targeting the PSP, SSP, and TSP + + INTC1 supports: + - 192 local peripheral interrupt inputs + - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank) + - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU + + One INTC1 instance is always present, on the SoC's IO die. A further two + instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS + Tunneling Protocol & Interface). + + Interrupt numbering model + ------------------------- + The binding uses a controller-local numbering model. Peripheral device + nodes use the INTCx local interrupt number (hwirq) in their 'interrupts'= or + 'interrupts-extended' properties. + + For AST2700, INTC0 exposes the following (inclusive) input ranges: + + - 000..479: Independent interrupts + - 480..489: INTM0-INTM9 + - 490..499: INTM10-INTM19 + - 500..509: INTM20-INTM29 + - 510..519: INTM30-INTM39 + - 520..529: INTM40-INTM49 + + INTC0's (inclusive) output ranges are as follows: + + - 000..127: 1:1 local peripheral interrupt output to PSP + - 144..151: Software interrupts from the SSP output to PSP + - 152..159: Software interrupts from the TSP output to PSP + - 192..201: INTM0-INTM9 banked outputs to PSP + - 208..217: INTM30-INTM39 banked outputs to PSP + - 224..233: INTM40-INTM49 banked outputs to PSP + - 256..383: 1:1 local peripheral interrupt output to SSP + - 384..393: INTM10-INTM19 banked outputs to SSP + - 400..407: Software interrupts from the PSP output to SSP + - 408..415: Software interrupts from the TSP output to SSP + - 426..553: 1:1 local peripheral interrupt output to TSP + - 554..563: INTM20-INTM29 banked outputs to TSP + - 570..577: Software interrupts from the PSP output to TSP + - 578..585: Software interrupts from the SSP output to TSP + + Inputs and outputs for INTC1 instances are context-dependent. However, f= or the + first instance of INTC1, the (inclusive) output ranges are: + + - 00..05: INTM0-INTM5 + - 10..15: INTM10-INTM15 + - 20..25: INTM20-INTM25 + - 30..35: INTM30-INTM35 + - 40..45: INTM40-INTM45 + - 50..50: BootMCU + +maintainers: + - Ryan Chen + - Andrew Jeffery + +properties: + compatible: + enum: + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: Single cell encoding the INTC local interrupt number (hwi= rq). + + aspeed,interrupt-ranges: + description: | + Describes how ranges of controller output pins are routed to a parent + interrupt controller. + + Each range entry is encoded as: + + + + where: + - out: First controller interrupt output index in the range. + - count: Number of consecutive controller interrupt outputs and = parent + interrupt inputs in this range. + - phandle: Phandle to the parent interrupt controller node. + - parent-specifier: Interrupt specifier, as defined by the parent + interrupt controller binding. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + items: + description: Range descriptors with a parent interrupt specifier. + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - aspeed,interrupt-ranges + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@12100000 { + compatible =3D "aspeed,ast2700-intc0"; + reg =3D <0x12100000 0x3b00>; + interrupt-parent =3D <&gic>; + interrupt-controller; + #interrupt-cells =3D <1>; + + aspeed,interrupt-ranges =3D + <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <256 128 &ssp_nvic 0 0>, + <384 10 &ssp_nvic 160 0>, + <400 8 &ssp_nvic 144 0>, + <408 8 &ssp_nvic 152 0>, + <426 128 &tsp_nvic 0 0>, + <554 10 &tsp_nvic 160 0>, + <570 8 &tsp_nvic 144 0>, + <578 8 &tsp_nvic 152 0>; + }; --=20 2.34.1 From nobody Thu Apr 2 09:13:07 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01EB73947B0; Mon, 30 Mar 2026 06:37:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 30 Mar 2026 14:32:11 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 30 Mar 2026 14:32:11 +0800 From: Ryan Chen Date: Mon, 30 Mar 2026 14:32:11 +0800 Subject: [PATCH v4 2/4] irqchip/ast2700-intc: Add AST2700-A2 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260330-irqchip-v4-2-3c0f1620cc06@aspeedtech.com> References: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , "Alexandre Ghiti" , Thomas Gleixner , Thomas Gleixner CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774852330; l=34895; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=i6Tc0HPlSQ37VLfqIrBKNmzPPeiMl9bG5qF5c4NSnmA=; b=D/K3MwJiDxmKpkBuXuudbApu7akT8dOj8zPrPxnC+C+kPIznqcwjhKZnvXScvRut7JIh187Qw lR+dyeySJgkAQzVHGMyY2/BHTvcYbrl7zeiaIEQ8JN/fGjj6HPDUdHR X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= The AST2700 interrupt fabric is shared by multiple integrated processors (PSP/SSP/TSP/BootMCU), each with its own interrupt controller and its own devicetree view of the system. As a result, interrupt routing cannot be treated as fixed: the valid route for a peripheral interrupt depends on which processor is consuming it. The INTC0 driver models this by creating a hierarchical irqdomain under the upstream interrupt controller selected by the interrupt-parent property in the devicetree. Information derived from this relationship is incorporated into the route resolution logic for the controller. The INTC1 driver implements the banked INTM-fed controller and forwards interrupts toward INTC0, without embedding assumptions about the final destination processor. Signed-off-by: Ryan Chen --- Changes in v2: - remove typedef u32 aspeed_intc_output_t - modify #include to - add newline after include "irq-ast2700.h" - make defines tabular - Struct declarations should align the struct member names in a table - modify raw_spinlock_irqsave() to raw_spin_lock() - use u32 ier replace mask/unmask - remove pointless line break - refine aspeed_intc0_routes, aspeed_intc1_routes array - remove range_contains_element(), use in_range32() - remove dev_dbg() - remove EXPORT_SYMBOL_GPL(aspeed_intc0_resolve_route); - make irq_set_chip_and_handler() with one line - replace magic constants to macro define - move struct aspeed_intc0 to irq-ast2700.h - add mcro define for upstream param --- drivers/irqchip/Kconfig | 12 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ast2700-intc0.c | 584 ++++++++++++++++++++++++++++++++= ++++ drivers/irqchip/irq-ast2700-intc1.c | 282 +++++++++++++++++ drivers/irqchip/irq-ast2700.c | 106 +++++++ drivers/irqchip/irq-ast2700.h | 47 +++ 6 files changed, 1032 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f07b00d7fef9..0156fee89b2c 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -110,6 +110,18 @@ config AL_FIC help Support Amazon's Annapurna Labs Fabric Interrupt Controller. =20 +config ASPEED_AST2700_INTC + bool "ASPEED AST2700 Interrupt Controller support" + depends on OF + depends on ARCH_ASPEED || COMPILE_TEST + select IRQ_DOMAIN_HIERARCHY + help + Enable support for the ASPEED AST2700 interrupt controller. + This driver handles interrupt, routing and merged interrupt + sources to upstream parent interrupt controllers. + + If unsure, say N. + config ATMEL_AIC_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 26aa3b6ec99f..62790663f982 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -89,6 +89,7 @@ obj-$(CONFIG_MVEBU_PIC) +=3D irq-mvebu-pic.o obj-$(CONFIG_MVEBU_SEI) +=3D irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o +obj-$(CONFIG_ASPEED_AST2700_INTC) +=3D irq-ast2700.o irq-ast2700-intc0.o i= rq-ast2700-intc1.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o diff --git a/drivers/irqchip/irq-ast2700-intc0.c b/drivers/irqchip/irq-ast2= 700-intc0.c new file mode 100644 index 000000000000..66e2fb108281 --- /dev/null +++ b/drivers/irqchip/irq-ast2700-intc0.c @@ -0,0 +1,584 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Aspeed AST2700 Interrupt Controller. + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-ast2700.h" + +#define INT_NUM 480 +#define INTM_NUM 50 +#define SWINT_NUM 16 + +#define INTM_BASE (INT_NUM) +#define SWINT_BASE (INT_NUM + INTM_NUM) +#define INT0_NUM (INT_NUM + INTM_NUM + SWINT_NUM) + +#define INTC0_IN_NUM 480 +#define INTC0_ROUTE_NUM 5 +#define INTC0_INTM_NUM 50 +#define INTC0_ROUTE_BITS 3 + +#define GIC_P2P_SPI_END 128 +#define INTC0_SWINT_OUT_BASE 144 + +#define INTC0_SWINT_IER 0x10 +#define INTC0_SWINT_ISR 0x14 +#define INTC0_INTBANKX_IER 0x1000 +#define INTC0_INTBANK_SIZE 0x100 +#define INTC0_INTBANK_GROUPS 11 +#define INTC0_INTBANKS_PER_GRP 3 +#define INTC0_INTMX_IER 0x1b00 +#define INTC0_INTMX_ISR 0x1b04 +#define INTC0_INTMX_BANK_SIZE 0x10 +#define INTC0_INTM_BANK_NUM 3 +#define INTC0_IRQS_PER_BANK 32 +#define INTM_IRQS_PER_BANK 10 +#define INTC0_SEL_BASE 0x200 +#define INTC0_SEL_BANK_SIZE 0x4 +#define INTC0_SEL_ROUTE_SIZE 0x100 + +static void aspeed_swint_irq_mask(struct irq_data *data) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + int bit =3D data->hwirq - SWINT_BASE; + u32 ier; + + guard(raw_spinlock)(&intc0->intc_lock); + ier =3D readl(intc0->base + INTC0_SWINT_IER) & ~BIT(bit); + writel(ier, intc0->base + INTC0_SWINT_IER); + irq_chip_mask_parent(data); +} + +static void aspeed_swint_irq_unmask(struct irq_data *data) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + int bit =3D data->hwirq - SWINT_BASE; + u32 ier; + + guard(raw_spinlock)(&intc0->intc_lock); + ier =3D readl(intc0->base + INTC0_SWINT_IER) | BIT(bit); + writel(ier, intc0->base + INTC0_SWINT_IER); + irq_chip_unmask_parent(data); +} + +static void aspeed_swint_irq_eoi(struct irq_data *data) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + int bit =3D data->hwirq - SWINT_BASE; + + writel(BIT(bit), intc0->base + INTC0_SWINT_ISR); + irq_chip_eoi_parent(data); +} + +static struct irq_chip aspeed_swint_chip =3D { + .name =3D "ast2700-swint", + .irq_eoi =3D aspeed_swint_irq_eoi, + .irq_mask =3D aspeed_swint_irq_mask, + .irq_unmask =3D aspeed_swint_irq_unmask, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_SET_TYPE_MASKED, +}; + +static void aspeed_intc0_irq_mask(struct irq_data *data) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + int bank =3D (data->hwirq - INTM_BASE) / INTM_IRQS_PER_BANK; + int bit =3D (data->hwirq - INTM_BASE) % INTM_IRQS_PER_BANK; + u32 ier; + + guard(raw_spinlock)(&intc0->intc_lock); + ier =3D readl(intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZ= E) & ~BIT(bit); + writel(ier, intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZE); + irq_chip_mask_parent(data); +} + +static void aspeed_intc0_irq_unmask(struct irq_data *data) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + int bank =3D (data->hwirq - INTM_BASE) / INTM_IRQS_PER_BANK; + int bit =3D (data->hwirq - INTM_BASE) % INTM_IRQS_PER_BANK; + u32 ier; + + guard(raw_spinlock)(&intc0->intc_lock); + ier =3D readl(intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZ= E) | BIT(bit); + writel(ier, intc0->base + INTC0_INTMX_IER + bank * INTC0_INTMX_BANK_SIZE); + irq_chip_unmask_parent(data); +} + +static void aspeed_intc0_irq_eoi(struct irq_data *data) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + int bank =3D (data->hwirq - INTM_BASE) / INTM_IRQS_PER_BANK; + int bit =3D (data->hwirq - INTM_BASE) % INTM_IRQS_PER_BANK; + + writel(BIT(bit), intc0->base + INTC0_INTMX_ISR + bank * INTC0_INTMX_BANK_= SIZE); + irq_chip_eoi_parent(data); +} + +static struct irq_chip aspeed_intm_chip =3D { + .name =3D "ast2700-intmerge", + .irq_eoi =3D aspeed_intc0_irq_eoi, + .irq_mask =3D aspeed_intc0_irq_mask, + .irq_unmask =3D aspeed_intc0_irq_unmask, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_SET_TYPE_MASKED, +}; + +static struct irq_chip linear_intr_irq_chip =3D { + .name =3D "ast2700-int", + .irq_eoi =3D irq_chip_eoi_parent, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_SET_TYPE_MASKED, +}; + +static const u32 aspeed_intc0_routes[INTC0_IN_NUM / INTC0_IRQS_PER_BANK][I= NTC0_ROUTE_NUM] =3D { + { 0, 256, 426, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE }, + { 32, 288, 458, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE }, + { 64, 320, 490, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE }, + { 96, 352, 522, AST2700_INTC_INVALID_ROUTE, AST2700_INTC_INVALID_ROUTE }, + { 128, 384, 554, 160, 176 }, + { 129, 385, 555, 161, 177 }, + { 130, 386, 556, 162, 178 }, + { 131, 387, 557, 163, 179 }, + { 132, 388, 558, 164, 180 }, + { 133, 544, 714, 165, 181 }, + { 134, 545, 715, 166, 182 }, + { 135, 546, 706, 167, 183 }, + { 136, 547, 707, 168, 184 }, + { 137, 548, 708, 169, 185 }, + { 138, 549, 709, 170, 186 }, +}; + +static const u32 aspeed_intc0_intm_routes[INTC0_INTM_NUM / INTM_IRQS_PER_B= ANK] =3D { + 192, 416, 586, 208, 224 +}; + +static int resolve_input_from_child_ranges(const struct aspeed_intc0 *intc= 0, + const struct aspeed_intc_interrupt_range *range, + u32 outpin, u32 *input) +{ + u32 offset, base; + + if (!in_range32(outpin, range->start, range->count)) + return -ENOENT; + + if (range->upstream.param_count =3D=3D 0) + return -EINVAL; + + base =3D range->upstream.param[ASPEED_INTC_RANGES_BASE]; + offset =3D outpin - range->start; + if (check_add_overflow(base, offset, input)) { + dev_warn(intc0->dev, "%s: Arithmetic overflow for input derivation: %u += %u\n", + __func__, base, offset); + return -EINVAL; + } + return 0; +} + +static int resolve_parent_range_for_output(const struct aspeed_intc0 *intc= 0, + const struct fwnode_handle *parent, + u32 output, + struct aspeed_intc_interrupt_range *resolved) +{ + for (size_t i =3D 0; i < intc0->ranges.nranges; i++) { + struct aspeed_intc_interrupt_range range =3D + intc0->ranges.ranges[i]; + + if (!in_range32(output, range.start, range.count)) + continue; + + if (range.upstream.fwnode !=3D parent) + continue; + + if (resolved) { + resolved->start =3D output; + resolved->count =3D 1; + resolved->upstream =3D range.upstream; + resolved->upstream.param[ASPEED_INTC_RANGES_COUNT] +=3D + output - range.start; + } + + return 0; + } + + return -ENOENT; +} + +static int resolve_parent_route_for_input(const struct aspeed_intc0 *intc0, + const struct fwnode_handle *parent, u32 input, + struct aspeed_intc_interrupt_range *resolved) +{ + int rc =3D -ENOENT; + u32 c0o; + + if (input < INT_NUM) { + static_assert(INTC0_ROUTE_NUM < INT_MAX, "Broken cast"); + for (size_t i =3D 0; rc =3D=3D -ENOENT && i < INTC0_ROUTE_NUM; i++) { + c0o =3D aspeed_intc0_routes[input / INTC0_IRQS_PER_BANK][i]; + if (c0o =3D=3D AST2700_INTC_INVALID_ROUTE) + continue; + + if (input < GIC_P2P_SPI_END) + c0o +=3D input % INTC0_IRQS_PER_BANK; + + rc =3D resolve_parent_range_for_output(intc0, parent, c0o, resolved); + if (!rc) + return (int)i; + } + } else if (input < (INT_NUM + INTM_NUM)) { + c0o =3D aspeed_intc0_intm_routes[(input - INT_NUM) / INTM_IRQS_PER_BANK]; + c0o +=3D ((input - INT_NUM) % INTM_IRQS_PER_BANK); + return resolve_parent_range_for_output(intc0, parent, c0o, resolved); + } else if (input < (INT_NUM + INTM_NUM + SWINT_NUM)) { + c0o =3D input - SWINT_BASE + INTC0_SWINT_OUT_BASE; + return resolve_parent_range_for_output(intc0, parent, c0o, resolved); + } else { + return -ENOENT; + } + + return rc; +} + +/** + * aspeed_intc0_resolve_route - Determine the necessary interrupt output a= t intc1 + * @c0domain: The pointer to intc0's irq_domain + * @nc1outs: The number of valid intc1 outputs available for the input + * @c1outs: The array of available intc1 output indices for the input + * @nc1ranges: The number of interrupt range entries for intc1 + * @c1ranges: The array of configured intc1 interrupt ranges + * @resolved: The fully resolved range entry after applying the resolution + * algorithm + * + * Returns: The intc1 route index associated with the intc1 output identif= ied in + * @resolved on success. Otherwise, a negative errno value. + * + * The AST2700 interrupt architecture allows any peripheral interrupt sour= ce + * to be routed to one of up to four processors running in the SoC. A proc= essor + * binding a driver for a peripheral that requests an interrupt is (without + * further design and effort) the destination for the requested interrupt. + * + * Routing a peripheral interrupt to its destination processor requires + * coordination between INTC0 on the CPU die and one or more INTC1 instanc= es. + * At least one INTC1 instance exists in the SoC on the IO-die, however up + * to two more instances may be integrated via LTPI (LVDS Tunneling Protoc= ol + * & Interface). + * + * Between the multiple destinations, various route constraints, and the + * devicetree binding design, some information that's needed at INTC1 inst= ances + * to route inbound interrupts correctly to the destination processor is o= nly + * available at INTC0. + * + * aspeed_intc0_resolve_route() is to be invoked by INTC1 driver instances= to + * perform the route resolution. The implementation in INTC0 allows INTC0 = to + * encapsulate the information used to perform route selection, and provid= es it + * with an opportunity to apply policy as part of the selection process. S= uch + * policy may, for instance, choose to de-prioritise some interrupts desti= ned + * for the PSP (Primary Service Processor) GIC. + */ +int aspeed_intc0_resolve_route(const struct irq_domain *c0domain, size_t n= c1outs, + const u32 *c1outs, size_t nc1ranges, + const struct aspeed_intc_interrupt_range *c1ranges, + struct aspeed_intc_interrupt_range *resolved) +{ + struct fwnode_handle *parent_fwnode; + struct aspeed_intc0 *intc0; + int ret; + + if (!c0domain || !resolved) + return -EINVAL; + + if (nc1outs > INT_MAX) + return -EINVAL; + + if (nc1outs =3D=3D 0 || nc1ranges =3D=3D 0) + return -ENOENT; + + if (!fwnode_device_is_compatible(c0domain->fwnode, "aspeed,ast2700-intc0"= )) + return -ENODEV; + + intc0 =3D c0domain->host_data; + if (!intc0) + return -EINVAL; + + parent_fwnode =3D of_fwnode_handle(intc0->parent); + + for (size_t i =3D 0; i < nc1outs; i++) { + u32 c1o =3D c1outs[i]; + + if (c1o =3D=3D AST2700_INTC_INVALID_ROUTE) + continue; + + for (size_t j =3D 0; j < nc1ranges; j++) { + struct aspeed_intc_interrupt_range c1r =3D c1ranges[j]; + u32 input; + + /* + * Range match for intc1 output pin + * + * Assume a failed match is still a match for the purpose of testing, + * saves a bunch of mess in the test fixtures + */ + if (!(c0domain =3D=3D irq_find_matching_fwspec(&c1r.upstream, + c0domain->bus_token) || + IS_ENABLED(CONFIG_ASPEED_AST2700_INTC_TEST))) + continue; + + ret =3D resolve_input_from_child_ranges(intc0, &c1r, c1o, &input); + if (ret) + continue; + + /* + * INTC1 should never request routes for peripheral interrupt sources + * directly attached to INTC0. + */ + if (input < GIC_P2P_SPI_END) + continue; + + ret =3D resolve_parent_route_for_input(intc0, parent_fwnode, input, NUL= L); + if (ret < 0) + continue; + + /* Route resolution succeeded */ + resolved->start =3D c1o; + resolved->count =3D 1; + resolved->upstream =3D c1r.upstream; + resolved->upstream.param[ASPEED_INTC_RANGES_BASE] =3D input; + /* Cast protected by prior test against nc1outs */ + return (int)i; + } + } + + return -ENOENT; +} + +static int aspeed_intc0_irq_domain_map(struct irq_domain *domain, + unsigned int irq, irq_hw_number_t hwirq) +{ + if (hwirq < GIC_P2P_SPI_END) + irq_set_chip_and_handler(irq, &linear_intr_irq_chip, handle_level_irq); + else if (hwirq < INTM_BASE) + return -EINVAL; + else if (hwirq < SWINT_BASE) + irq_set_chip_and_handler(irq, &aspeed_intm_chip, handle_level_irq); + else if (hwirq < INT0_NUM) + irq_set_chip_and_handler(irq, &aspeed_swint_chip, handle_level_irq); + else + return -EINVAL; + + irq_set_chip_data(irq, domain->host_data); + return 0; +} + +static int aspeed_intc0_irq_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (fwspec->param_count !=3D 1) + return -EINVAL; + + *hwirq =3D fwspec->param[0]; + *type =3D IRQ_TYPE_NONE; + return 0; +} + +static int aspeed_intc0_irq_domain_alloc(struct irq_domain *domain, + unsigned int virq, + unsigned int nr_irqs, void *data) +{ + struct aspeed_intc0 *intc0 =3D domain->host_data; + struct aspeed_intc_interrupt_range resolved; + struct irq_fwspec *fwspec =3D data; + struct irq_fwspec parent_fwspec; + struct irq_chip *chip; + unsigned long hwirq; + unsigned int type; + int ret; + + ret =3D aspeed_intc0_irq_domain_translate(domain, fwspec, &hwirq, &type); + if (ret) + return ret; + + if (hwirq >=3D GIC_P2P_SPI_END && hwirq < INT_NUM) + return -EINVAL; + + if (hwirq < INTM_BASE) + chip =3D &linear_intr_irq_chip; + else if (hwirq < SWINT_BASE) + chip =3D &aspeed_intm_chip; + else + chip =3D &aspeed_swint_chip; + + ret =3D resolve_parent_route_for_input(intc0, domain->parent->fwnode, + (u32)hwirq, &resolved); + if (ret) + return ret; + + parent_fwspec =3D resolved.upstream; + ret =3D irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, + &parent_fwspec); + if (ret) + return ret; + + for (int i =3D 0; i < nr_irqs; ++i, ++hwirq, ++virq) { + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, + domain->host_data); + if (ret) + return ret; + } + + return 0; +} + +static int aspeed_intc0_irq_domain_activate(struct irq_domain *domain, + struct irq_data *data, bool reserve) +{ + struct aspeed_intc0 *intc0 =3D irq_data_get_irq_chip_data(data); + unsigned long hwirq =3D data->hwirq; + int route, bank, bit; + u32 mask; + + if (hwirq >=3D INT0_NUM) + return -EINVAL; + + if (in_range32(hwirq, INTM_BASE, INTM_NUM + SWINT_NUM)) + return 0; + + bank =3D hwirq / INTC0_IRQS_PER_BANK; + bit =3D hwirq % INTC0_IRQS_PER_BANK; + mask =3D BIT(bit); + + route =3D resolve_parent_route_for_input(intc0, intc0->local->parent->fwn= ode, + hwirq, NULL); + if (route < 0) + return route; + + guard(raw_spinlock)(&intc0->intc_lock); + for (int i =3D 0; i < INTC0_ROUTE_BITS; i++) { + void __iomem *sel =3D intc0->base + INTC0_SEL_BASE + + (bank * INTC0_SEL_BANK_SIZE) + + (INTC0_SEL_ROUTE_SIZE * i); + u32 reg =3D readl(sel); + + if (route & BIT(i)) + reg |=3D mask; + else + reg &=3D ~mask; + + writel(reg, sel); + if (readl(sel) !=3D reg) + return -EACCES; + } + + return 0; +} + +static const struct irq_domain_ops aspeed_intc0_irq_domain_ops =3D { + .translate =3D aspeed_intc0_irq_domain_translate, + .activate =3D aspeed_intc0_irq_domain_activate, + .alloc =3D aspeed_intc0_irq_domain_alloc, + .free =3D irq_domain_free_irqs_common, + .map =3D aspeed_intc0_irq_domain_map, +}; + +static void aspeed_intc0_disable_swint(struct aspeed_intc0 *intc0) +{ + writel(0, intc0->base + INTC0_SWINT_IER); +} + +static void aspeed_intc0_disable_intbank(struct aspeed_intc0 *intc0) +{ + for (int i =3D 0; i < INTC0_INTBANK_GROUPS; i++) { + for (int j =3D 0; j < INTC0_INTBANKS_PER_GRP; j++) { + u32 base =3D INTC0_INTBANKX_IER + + (INTC0_INTBANK_SIZE * i) + + (INTC0_INTMX_BANK_SIZE * j); + + writel(0, intc0->base + base); + } + } +} + +static void aspeed_intc0_disable_intm(struct aspeed_intc0 *intc0) +{ + for (int i =3D 0; i < INTC0_INTM_BANK_NUM; i++) + writel(0, intc0->base + INTC0_INTMX_IER + (INTC0_INTMX_BANK_SIZE * i)); +} + +static int aspeed_intc0_probe(struct platform_device *pdev, + struct device_node *parent) +{ + struct device_node *node =3D pdev->dev.of_node; + struct irq_domain *parent_domain; + struct aspeed_intc0 *intc0; + int ret; + + if (!parent) { + pr_err("missing parent interrupt node\n"); + return -ENODEV; + } + + intc0 =3D devm_kzalloc(&pdev->dev, sizeof(*intc0), GFP_KERNEL); + if (!intc0) + return -ENOMEM; + + intc0->dev =3D &pdev->dev; + intc0->parent =3D parent; + intc0->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(intc0->base)) + return PTR_ERR(intc0->base); + + aspeed_intc0_disable_swint(intc0); + aspeed_intc0_disable_intbank(intc0); + aspeed_intc0_disable_intm(intc0); + + raw_spin_lock_init(&intc0->intc_lock); + + parent_domain =3D irq_find_host(parent); + if (!parent_domain) { + pr_err("unable to obtain parent domain\n"); + return -ENODEV; + } + + if (!of_device_is_compatible(parent, "arm,gic-v3")) + return -ENODEV; + + intc0->local =3D irq_domain_create_hierarchy(parent_domain, 0, INT0_NUM, + of_fwnode_handle(node), + &aspeed_intc0_irq_domain_ops, + intc0); + if (!intc0->local) + return -ENOMEM; + + ret =3D aspeed_intc_populate_ranges(&pdev->dev, &intc0->ranges); + if (ret < 0) { + irq_domain_remove(intc0->local); + return ret; + } + + return 0; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(ast2700_intc0) +IRQCHIP_MATCH("aspeed,ast2700-intc0", aspeed_intc0_probe) +IRQCHIP_PLATFORM_DRIVER_END(ast2700_intc0) diff --git a/drivers/irqchip/irq-ast2700-intc1.c b/drivers/irqchip/irq-ast2= 700-intc1.c new file mode 100644 index 000000000000..09b9d5d743e6 --- /dev/null +++ b/drivers/irqchip/irq-ast2700-intc1.c @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Aspeed AST2700 Interrupt Controller. + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "irq-ast2700.h" + +#define INTC1_IER 0x100 +#define INTC1_ISR 0x104 +#define INTC1_BANK_SIZE 0x10 +#define INTC1_SEL_BASE 0x80 +#define INTC1_SEL_BANK_SIZE 0x4 +#define INTC1_SEL_ROUTE_SIZE 0x20 +#define INTC1_IRQS_PER_BANK 32 +#define INTC1_BANK_NUM 6 +#define INTC1_ROUTE_NUM 7 +#define INTC1_IN_NUM 192 +#define INTC1_BOOTMCU_ROUTE 6 +#define INTC1_ROUTE_SELECTOR_BITS 3 +#define INTC1_ROUTE_IRQS_PER_GROUP 32 +#define INTC1_ROUTE_SHIFT 5 + +struct aspeed_intc1 { + struct device *dev; + void __iomem *base; + raw_spinlock_t intc_lock; + struct irq_domain *local; + struct irq_domain *upstream; + struct aspeed_intc_interrupt_ranges ranges; +}; + +static void aspeed_intc1_disable_int(struct aspeed_intc1 *intc1) +{ + for (int i =3D 0; i < INTC1_BANK_NUM; i++) + writel(0, intc1->base + INTC1_IER + (INTC1_BANK_SIZE * i)); +} + +static void aspeed_intc1_irq_handler(struct irq_desc *desc) +{ + struct aspeed_intc1 *intc1 =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned long bit, status; + + chained_irq_enter(chip, desc); + + for (int bank =3D 0; bank < INTC1_BANK_NUM; bank++) { + status =3D readl(intc1->base + INTC1_ISR + (INTC1_BANK_SIZE * bank)); + if (!status) + continue; + + for_each_set_bit(bit, &status, INTC1_IRQS_PER_BANK) { + generic_handle_domain_irq(intc1->local, (bank * INTC1_IRQS_PER_BANK) + = bit); + writel(BIT(bit), intc1->base + INTC1_ISR + (INTC1_BANK_SIZE * bank)); + } + } + + chained_irq_exit(chip, desc); +} + +static void aspeed_intc1_irq_mask(struct irq_data *data) +{ + struct aspeed_intc1 *intc1 =3D irq_data_get_irq_chip_data(data); + int bank =3D data->hwirq / INTC1_IRQS_PER_BANK; + int bit =3D data->hwirq % INTC1_IRQS_PER_BANK; + u32 ier; + + guard(raw_spinlock)(&intc1->intc_lock); + ier =3D readl(intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank)) & ~BIT(= bit); + writel(ier, intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank)); +} + +static void aspeed_intc1_irq_unmask(struct irq_data *data) +{ + struct aspeed_intc1 *intc1 =3D irq_data_get_irq_chip_data(data); + int bank =3D data->hwirq / INTC1_IRQS_PER_BANK; + int bit =3D data->hwirq % INTC1_IRQS_PER_BANK; + u32 ier; + + guard(raw_spinlock)(&intc1->intc_lock); + ier =3D readl(intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank)) | BIT(b= it); + writel(ier, intc1->base + INTC1_IER + (INTC1_BANK_SIZE * bank)); +} + +static struct irq_chip aspeed_intc_chip =3D { + .name =3D "ASPEED INTC1", + .irq_mask =3D aspeed_intc1_irq_mask, + .irq_unmask =3D aspeed_intc1_irq_unmask, +}; + +static int aspeed_intc1_irq_domain_translate(struct irq_domain *domain, + struct irq_fwspec *fwspec, + unsigned long *hwirq, + unsigned int *type) +{ + if (fwspec->param_count !=3D 1) + return -EINVAL; + + *hwirq =3D fwspec->param[0]; + *type =3D IRQ_TYPE_LEVEL_HIGH; + return 0; +} + +static int aspeed_intc1_map_irq_domain(struct irq_domain *domain, + unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_domain_set_info(domain, irq, hwirq, &aspeed_intc_chip, + domain->host_data, handle_level_irq, NULL, NULL); + return 0; +} + +/* + * In-bound interrupts are progressively merged into one out-bound interru= pt in + * groups of 32. Apply this fact to compress the route table in correspond= ing + * groups of 32. + */ +static const u32 +aspeed_intc1_routes[INTC1_IN_NUM / INTC1_ROUTE_IRQS_PER_GROUP][INTC1_ROUTE= _NUM] =3D { + { 0, AST2700_INTC_INVALID_ROUTE, 10, 20, 30, 40, 50 }, + { 1, AST2700_INTC_INVALID_ROUTE, 11, 21, 31, 41, 50 }, + { 2, AST2700_INTC_INVALID_ROUTE, 12, 22, 32, 42, 50 }, + { 3, AST2700_INTC_INVALID_ROUTE, 13, 23, 33, 43, 50 }, + { 4, AST2700_INTC_INVALID_ROUTE, 14, 24, 34, 44, 50 }, + { 5, AST2700_INTC_INVALID_ROUTE, 15, 25, 35, 45, 50 }, +}; + +static int aspeed_intc1_irq_domain_activate(struct irq_domain *domain, + struct irq_data *data, bool reserve) +{ + struct aspeed_intc1 *intc1 =3D irq_data_get_irq_chip_data(data); + struct aspeed_intc_interrupt_range resolved; + int rc, bank, bit; + u32 mask; + + if (WARN_ON_ONCE((data->hwirq >> INTC1_ROUTE_SHIFT) >=3D ARRAY_SIZE(aspee= d_intc1_routes))) + return -EINVAL; + + /* + * outpin may be an error if the upstream is the BootMCU APLIC node, or + * anything except a valid intc0 driver instance + */ + rc =3D aspeed_intc0_resolve_route(intc1->upstream, INTC1_ROUTE_NUM, + aspeed_intc1_routes[data->hwirq >> INTC1_ROUTE_SHIFT], + intc1->ranges.nranges, + intc1->ranges.ranges, &resolved); + if (rc < 0) { + if (!fwnode_device_is_compatible(intc1->upstream->fwnode, "riscv,aplic")= ) { + dev_warn(intc1->dev, + "Failed to resolve interrupt route for hwirq %lu in domain %s\n", + data->hwirq, domain->name); + return rc; + } + rc =3D INTC1_BOOTMCU_ROUTE; + } + + bank =3D data->hwirq / INTC1_IRQS_PER_BANK; + bit =3D data->hwirq % INTC1_IRQS_PER_BANK; + mask =3D BIT(bit); + + guard(raw_spinlock)(&intc1->intc_lock); + for (int i =3D 0; i < INTC1_ROUTE_SELECTOR_BITS; i++) { + void __iomem *sel =3D intc1->base + INTC1_SEL_BASE + + (bank * INTC1_SEL_BANK_SIZE) + + (INTC1_SEL_ROUTE_SIZE * i); + u32 reg =3D readl(sel); + + if (rc & BIT(i)) + reg |=3D mask; + else + reg &=3D ~mask; + + writel(reg, sel); + if (readl(sel) !=3D reg) + return -EACCES; + } + + return 0; +} + +static const struct irq_domain_ops aspeed_intc1_irq_domain_ops =3D { + .map =3D aspeed_intc1_map_irq_domain, + .translate =3D aspeed_intc1_irq_domain_translate, + .activate =3D aspeed_intc1_irq_domain_activate, +}; + +static void aspeed_intc1_request_interrupts(struct aspeed_intc1 *intc1) +{ + for (unsigned int i =3D 0; i < intc1->ranges.nranges; i++) { + struct aspeed_intc_interrupt_range *r =3D + &intc1->ranges.ranges[i]; + + if (intc1->upstream !=3D + irq_find_matching_fwspec(&r->upstream, + intc1->upstream->bus_token)) + continue; + + for (u32 k =3D 0; k < r->count; k++) { + struct of_phandle_args parent_irq; + int irq; + + parent_irq.np =3D to_of_node(r->upstream.fwnode); + parent_irq.args_count =3D 1; + parent_irq.args[0] =3D + intc1->ranges.ranges[i].upstream.param[ASPEED_INTC_RANGES_BASE] + k; + + irq =3D irq_create_of_mapping(&parent_irq); + if (!irq) + continue; + + irq_set_chained_handler_and_data(irq, + aspeed_intc1_irq_handler, intc1); + } + } +} + +static int aspeed_intc1_probe(struct platform_device *pdev, + struct device_node *parent) +{ + struct device_node *node =3D pdev->dev.of_node; + struct aspeed_intc1 *intc1; + struct irq_domain *host; + int ret; + + if (!parent) { + dev_err(&pdev->dev, "missing parent interrupt node\n"); + return -ENODEV; + } + + if (!of_device_is_compatible(parent, "aspeed,ast2700-intc0")) + return -ENODEV; + + host =3D irq_find_host(parent); + if (!host) + return -ENODEV; + + intc1 =3D devm_kzalloc(&pdev->dev, sizeof(*intc1), GFP_KERNEL); + if (!intc1) + return -ENOMEM; + + intc1->dev =3D &pdev->dev; + intc1->upstream =3D host; + intc1->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(intc1->base)) + return PTR_ERR(intc1->base); + + aspeed_intc1_disable_int(intc1); + + raw_spin_lock_init(&intc1->intc_lock); + + intc1->local =3D irq_domain_create_linear(of_fwnode_handle(node), + INTC1_BANK_NUM * INTC1_IRQS_PER_BANK, + &aspeed_intc1_irq_domain_ops, intc1); + if (!intc1->local) + return -ENOMEM; + + ret =3D aspeed_intc_populate_ranges(&pdev->dev, &intc1->ranges); + if (ret < 0) { + irq_domain_remove(intc1->local); + return ret; + } + + aspeed_intc1_request_interrupts(intc1); + + return 0; +} + +IRQCHIP_PLATFORM_DRIVER_BEGIN(ast2700_intc1) +IRQCHIP_MATCH("aspeed,ast2700-intc1", aspeed_intc1_probe) +IRQCHIP_PLATFORM_DRIVER_END(ast2700_intc1) diff --git a/drivers/irqchip/irq-ast2700.c b/drivers/irqchip/irq-ast2700.c new file mode 100644 index 000000000000..280657480d5f --- /dev/null +++ b/drivers/irqchip/irq-ast2700.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Aspeed AST2700 Interrupt Controller. + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ +#include "irq-ast2700.h" + +#define ASPEED_INTC_RANGE_FIXED_CELLS 3U +#define ASPEED_INTC_RANGE_OFF_START 0U +#define ASPEED_INTC_RANGE_OFF_COUNT 1U +#define ASPEED_INTC_RANGE_OFF_PHANDLE 2U + +/** + * aspeed_intc_populate_ranges + * @dev: Device owning the interrupt controller node. + * @ranges: Destination for parsed range descriptors. + * + * Return: 0 on success, negative errno on error. + */ +int aspeed_intc_populate_ranges(struct device *dev, + struct aspeed_intc_interrupt_ranges *ranges) +{ + struct aspeed_intc_interrupt_range *arr; + const __be32 *pvs, *pve; + struct device_node *dn; + int len; + + if (!dev || !ranges) + return -EINVAL; + + dn =3D dev->of_node; + + pvs =3D of_get_property(dn, "aspeed,interrupt-ranges", &len); + if (!pvs) + return -EINVAL; + + if (len % sizeof(__be32)) + return -EINVAL; + + /* Over-estimate the range entry count for now */ + ranges->ranges =3D devm_kmalloc_array(dev, + len / (ASPEED_INTC_RANGE_FIXED_CELLS * sizeof(__be32)), + sizeof(*ranges->ranges), + GFP_KERNEL); + if (!ranges->ranges) + return -ENOMEM; + + pve =3D pvs + (len / sizeof(__be32)); + for (unsigned int i =3D 0; pve - pvs >=3D ASPEED_INTC_RANGE_FIXED_CELLS; = i++) { + struct aspeed_intc_interrupt_range *r; + struct device_node *target; + u32 target_cells; + + target =3D of_find_node_by_phandle(be32_to_cpu(pvs[ASPEED_INTC_RANGE_OFF= _PHANDLE])); + if (!target) + return -EINVAL; + + if (of_property_read_u32(target, "#interrupt-cells", + &target_cells)) { + of_node_put(target); + return -EINVAL; + } + + if (!target_cells || target_cells > IRQ_DOMAIN_IRQ_SPEC_PARAMS) { + of_node_put(target); + return -EINVAL; + } + + if (pve - pvs < ASPEED_INTC_RANGE_FIXED_CELLS + target_cells) { + of_node_put(target); + return -EINVAL; + } + + r =3D &ranges->ranges[i]; + r->start =3D be32_to_cpu(pvs[ASPEED_INTC_RANGE_OFF_START]); + r->count =3D be32_to_cpu(pvs[ASPEED_INTC_RANGE_OFF_COUNT]); + + { + struct of_phandle_args args =3D { + .np =3D target, + .args_count =3D target_cells, + }; + + for (u32 j =3D 0; j < target_cells; j++) + args.args[j] =3D be32_to_cpu(pvs[ASPEED_INTC_RANGE_FIXED_CELLS + j]); + + of_phandle_args_to_fwspec(target, args.args, + args.args_count, + &r->upstream); + } + + of_node_put(target); + pvs +=3D ASPEED_INTC_RANGE_FIXED_CELLS + target_cells; + ranges->nranges++; + } + + /* Re-fit the range array now we know the entry count */ + arr =3D devm_krealloc_array(dev, ranges->ranges, ranges->nranges, + sizeof(*ranges->ranges), GFP_KERNEL); + if (!arr) + return -ENOMEM; + ranges->ranges =3D arr; + + return 0; +} diff --git a/drivers/irqchip/irq-ast2700.h b/drivers/irqchip/irq-ast2700.h new file mode 100644 index 000000000000..544f1af4c8ab --- /dev/null +++ b/drivers/irqchip/irq-ast2700.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Aspeed AST2700 Interrupt Controller. + * + * Copyright (C) 2026 ASPEED Technology Inc. + */ +#ifndef DRIVERS_IRQCHIP_AST2700 +#define DRIVERS_IRQCHIP_AST2700 + +#include +#include + +#define AST2700_INTC_INVALID_ROUTE (~0U) +#define ASPEED_INTC_RANGES_BASE 0U +#define ASPEED_INTC_RANGES_COUNT 1U + +struct aspeed_intc_interrupt_range { + u32 start; + u32 count; + struct irq_fwspec upstream; +}; + +struct aspeed_intc_interrupt_ranges { + struct aspeed_intc_interrupt_range *ranges; + unsigned int nranges; +}; + +struct aspeed_intc0 { + struct device *dev; + void __iomem *base; + raw_spinlock_t intc_lock; + struct irq_domain *local; + struct device_node *parent; + struct aspeed_intc_interrupt_ranges ranges; +}; + +int aspeed_intc_populate_ranges(struct device *dev, + struct aspeed_intc_interrupt_ranges *ranges); + +int aspeed_intc0_resolve_route(const struct irq_domain *c0domain, + size_t nc1outs, + const u32 *c1outs, + size_t nc1ranges, + const struct aspeed_intc_interrupt_range *c1ranges, + struct aspeed_intc_interrupt_range *resolved); + +#endif --=20 2.34.1 From nobody Thu Apr 2 09:13:07 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BF5A391505; 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dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 30 Mar 2026 14:32:11 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Mon, 30 Mar 2026 14:32:11 +0800 From: Ryan Chen Date: Mon, 30 Mar 2026 14:32:12 +0800 Subject: [PATCH v4 3/4] irqchip/ast2700-intc: Add KUnit tests for route resolution Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260330-irqchip-v4-3-3c0f1620cc06@aspeedtech.com> References: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , "Alexandre Ghiti" , Thomas Gleixner , Thomas Gleixner CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774852330; l=14766; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=oB9RyZS3+772u0r2y3OmDdlibp4XBcBxID5nPLaEA68=; b=mZKfdNK4E99WvDkbbUua4z+WPC1acEvSxmCXc1+CGYyH5Rs5PuobYG9IEeBq40jRi4X/82loF nsCf1yvgyA2CT4kjFiHD0K5QtBcT9ZqWQsqZbyIPcgx79JEwAqTu1Y7 X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= Add a KUnit suite for aspeed_intc0_resolve_route(). Cover invalid arguments, invalid domain/range data, connected and disconnected mappings, and malformed upstream range cases. Signed-off-by: Ryan Chen --- Changes in v4: - fix warning: the frame size of 1296 bytes is larger than 1280 bytes. Changes in v2: - add line break before include "irq-ast2700.h" - remove pointless newline. - rename arm_gicv3_fwnode_read_string_array to gicv3_fwnode_read_string_array - add .kunitconfig file --- drivers/irqchip/.kunitconfig | 5 + drivers/irqchip/Kconfig | 11 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-ast2700-intc0-test.c | 473 +++++++++++++++++++++++++++= ++++ 4 files changed, 490 insertions(+) diff --git a/drivers/irqchip/.kunitconfig b/drivers/irqchip/.kunitconfig new file mode 100644 index 000000000000..00a12703f635 --- /dev/null +++ b/drivers/irqchip/.kunitconfig @@ -0,0 +1,5 @@ +CONFIG_KUNIT=3Dy +CONFIG_OF=3Dy +CONFIG_COMPILE_TEST=3Dy +CONFIG_ASPEED_AST2700_INTC=3Dy +CONFIG_ASPEED_AST2700_INTC_TEST=3Dy diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 0156fee89b2c..143af3f30a4b 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -122,6 +122,17 @@ config ASPEED_AST2700_INTC =20 If unsure, say N. =20 +config ASPEED_AST2700_INTC_TEST + bool "Tests for the ASPEED AST2700 Interrupt Controller" + depends on ASPEED_AST2700_INTC && KUNIT=3Dy + default KUNIT_ALL_TESTS + help + Enable KUnit tests for AST2700 INTC route resolution. + The tests exercise error handling and route selection paths. + This option is intended for test builds. + + If unsure, say N. + config ATMEL_AIC_IRQ bool select GENERIC_IRQ_CHIP diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 62790663f982..ac04a4b97797 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -90,6 +90,7 @@ obj-$(CONFIG_MVEBU_SEI) +=3D irq-mvebu-sei.o obj-$(CONFIG_LS_EXTIRQ) +=3D irq-ls-extirq.o obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ASPEED_AST2700_INTC) +=3D irq-ast2700.o irq-ast2700-intc0.o i= rq-ast2700-intc1.o +obj-$(CONFIG_ASPEED_AST2700_INTC_TEST) +=3D irq-ast2700-intc0-test.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o diff --git a/drivers/irqchip/irq-ast2700-intc0-test.c b/drivers/irqchip/irq= -ast2700-intc0-test.c new file mode 100644 index 000000000000..d49784509ac7 --- /dev/null +++ b/drivers/irqchip/irq-ast2700-intc0-test.c @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Code Construct + */ +#include + +#include "irq-ast2700.h" + +static void aspeed_intc0_resolve_route_bad_args(struct kunit *test) +{ + static const struct aspeed_intc_interrupt_range c1ranges[] =3D { 0 }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + const struct irq_domain c0domain =3D { 0 }; + int rc; + + rc =3D aspeed_intc0_resolve_route(NULL, 0, c1outs, 0, c1ranges, NULL); + KUNIT_EXPECT_EQ(test, rc, -EINVAL); + + rc =3D aspeed_intc0_resolve_route(&c0domain, 0, c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_EQ(test, rc, -ENOENT); + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + 0, c1ranges, &resolved); + KUNIT_EXPECT_EQ(test, rc, -ENOENT); +} + +static int gicv3_fwnode_read_string_array(const struct fwnode_handle *fwno= de, + const char *propname, const char **val, size_t nval) +{ + if (!propname) + return -EINVAL; + + if (!val) + return 1; + + if (WARN_ON(nval !=3D 1)) + return -EOVERFLOW; + + *val =3D "arm,gic-v3"; + return 1; +} + +static const struct fwnode_operations arm_gicv3_fwnode_ops =3D { + .property_read_string_array =3D gicv3_fwnode_read_string_array, +}; + +static void aspeed_intc_resolve_route_invalid_c0domain(struct kunit *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &arm_gicv3_fwnode_ops }, + }; + const struct irq_domain c0domain =3D { .fwnode =3D &intc0_node.fwnode }; + static const struct aspeed_intc_interrupt_range c1ranges[] =3D { 0 }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_NE(test, rc, 0); +} + +static int +aspeed_intc0_fwnode_read_string_array(const struct fwnode_handle *fwnode_h= andle, + const char *propname, const char **val, + size_t nval) +{ + if (!propname) + return -EINVAL; + + if (!val) + return 1; + + if (WARN_ON(nval !=3D 1)) + return -EOVERFLOW; + + *val =3D "aspeed,ast2700-intc0"; + return nval; +} + +static const struct fwnode_operations intc0_fwnode_ops =3D { + .property_read_string_array =3D aspeed_intc0_fwnode_read_string_array, +}; + +static void +aspeed_intc0_resolve_route_c1i1o1c0i1o1_connected(struct kunit *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 128 } + } + } + }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 128, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D { 0 }, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { .ranges =3D intc0_ranges, .nranges =3D ARRAY_SIZE(intc0_ra= nges), } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_EQ(test, rc, 0); + KUNIT_EXPECT_EQ(test, resolved.start, 0); + KUNIT_EXPECT_EQ(test, resolved.count, 1); + KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 128); +} + +static void +aspeed_intc0_resolve_route_c1i1o1c0i1o1_disconnected(struct kunit *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 128 } + } + } + }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 129, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D { 0 }, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { + .ranges =3D intc0_ranges, + .nranges =3D ARRAY_SIZE(intc0_ranges), + } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_NE(test, rc, 0); +} + +static void aspeed_intc0_resolve_route_c1i1o1mc0i1o1(struct kunit *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 480 } + } + } + }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 192, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D { 0 }, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { + .ranges =3D intc0_ranges, + .nranges =3D ARRAY_SIZE(intc0_ranges), + } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_EQ(test, rc, 0); + KUNIT_EXPECT_EQ(test, resolved.start, 0); + KUNIT_EXPECT_EQ(test, resolved.count, 1); + KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 480); +} + +static void aspeed_intc0_resolve_route_c1i2o2mc0i1o1(struct kunit *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 480 } + } + }, + { + .start =3D 1, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 510 } + } + } + }; + static const u32 c1outs[] =3D { 1 }; + struct aspeed_intc_interrupt_range resolved; + static struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 208, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D { 0 }, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { + .ranges =3D intc0_ranges, + .nranges =3D ARRAY_SIZE(intc0_ranges), + } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_EQ(test, rc, 0); + KUNIT_EXPECT_EQ(test, resolved.start, 1); + KUNIT_EXPECT_EQ(test, resolved.count, 1); + KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 510); +} + +static void aspeed_intc0_resolve_route_c1i1o1mc0i2o1(struct kunit *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 510 } + } + }, + }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + static struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 192, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D {0}, + } + }, + { + .start =3D 208, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D {0}, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { + .ranges =3D intc0_ranges, + .nranges =3D ARRAY_SIZE(intc0_ranges), + } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_EQ(test, rc, 0); + KUNIT_EXPECT_EQ(test, resolved.start, 0); + KUNIT_EXPECT_EQ(test, resolved.count, 1); + KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 510); +} + +static void aspeed_intc0_resolve_route_c1i1o2mc0i1o1_invalid(struct kunit = *test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 1, + .param =3D { 480 } + } + } + }; + static const u32 c1outs[] =3D { + AST2700_INTC_INVALID_ROUTE, 0 + }; + struct aspeed_intc_interrupt_range resolved; + struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 192, + .count =3D 1, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D { 0 }, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { + .ranges =3D intc0_ranges, + .nranges =3D ARRAY_SIZE(intc0_ranges), + } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_EQ(test, rc, 1); + KUNIT_EXPECT_EQ(test, resolved.start, 0); + KUNIT_EXPECT_EQ(test, resolved.count, 1); + KUNIT_EXPECT_EQ(test, resolved.upstream.param[0], 480); +} + +static void +aspeed_intc0_resolve_route_c1i1o1mc0i1o1_bad_range_upstream(struct kunit *= test) +{ + struct device_node intc0_node =3D { + .fwnode =3D { .ops =3D &intc0_fwnode_ops }, + }; + struct aspeed_intc_interrupt_range c1ranges[] =3D { + { + .start =3D 0, + .count =3D 1, + .upstream =3D { + .fwnode =3D &intc0_node.fwnode, + .param_count =3D 0, + .param =3D { 0 } + } + } + }; + static const u32 c1outs[] =3D { 0 }; + struct aspeed_intc_interrupt_range resolved; + struct aspeed_intc_interrupt_range intc0_ranges[] =3D { + { + .start =3D 0, + .count =3D 0, + .upstream =3D { + .fwnode =3D NULL, + .param_count =3D 0, + .param =3D { 0 }, + } + } + }; + struct aspeed_intc0 intc0 =3D { + .ranges =3D { + .ranges =3D intc0_ranges, + .nranges =3D ARRAY_SIZE(intc0_ranges), + } + }; + const struct irq_domain c0domain =3D { + .host_data =3D &intc0, + .fwnode =3D &intc0_node.fwnode + }; + int rc; + + rc =3D aspeed_intc0_resolve_route(&c0domain, ARRAY_SIZE(c1outs), c1outs, + ARRAY_SIZE(c1ranges), c1ranges, + &resolved); + KUNIT_EXPECT_NE(test, rc, 0); +} + +static struct kunit_case ast2700_intc0_test_cases[] =3D { + KUNIT_CASE(aspeed_intc0_resolve_route_bad_args), + KUNIT_CASE(aspeed_intc_resolve_route_invalid_c0domain), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1c0i1o1_connected), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1c0i1o1_disconnected), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1mc0i1o1), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i2o2mc0i1o1), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1mc0i2o1), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o2mc0i1o1_invalid), + KUNIT_CASE(aspeed_intc0_resolve_route_c1i1o1mc0i1o1_bad_range_upstream), + {}, +}; + +static struct kunit_suite ast2700_intc0_test_suite =3D { + .name =3D "ast2700-intc0", + .test_cases =3D ast2700_intc0_test_cases, +}; + +kunit_test_suite(ast2700_intc0_test_suite); + +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Thu Apr 2 09:13:07 2026 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC87D395257; Mon, 30 Mar 2026 06:33:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774852407; cv=none; b=bit7mIIxsesr11qGqxtA6HJ2R+hVQhV+TIm8v8urX2wd6IlVP3KytPBPWMBIdPgOcSSDqDbqoVozJjA0MfEIpyLsF07yR6iWqXkHBmxPNhI2A9Aw6fe+2ay+oV7q81yjpEh4F1MuafND0nwVMTfuZRWWHsp6kr958/GW9UMddm4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774852407; c=relaxed/simple; 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Mon, 30 Mar 2026 14:32:11 +0800 From: Ryan Chen Date: Mon, 30 Mar 2026 14:32:13 +0800 Subject: [PATCH v4 4/4] irqchip/aspeed-intc: Remove AST2700-A0 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260330-irqchip-v4-4-3c0f1620cc06@aspeedtech.com> References: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> In-Reply-To: <20260330-irqchip-v4-0-3c0f1620cc06@aspeedtech.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Paul Walmsley , "Palmer Dabbelt" , Albert Ou , "Alexandre Ghiti" , Thomas Gleixner , Thomas Gleixner CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774852330; l=5800; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=dDHK26Pv3om1nVVi9t4wNhYIZIKE7ffity4S2AcBKdE=; b=xcVlBcqWDoLrSv7zDQxLudTGqsYv9nGiPqMSGDAnUQk9iwdLNXt8pdbYnxcVyhlGGRtRLG9z2 izzl076YyejAR3X4wsT0KVZMGmDQYcuQlguDA5651cJq9HXtaED4K81 X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= The existing AST2700 interrupt controller driver ("aspeed,ast2700-intc-ic") was written against the A0 pre-production design. From A1 onwards (retained in the A2 production silicon), the interrupt fabric was re-architected: interrupt routing is programmable and interrupt outputs can be directed to multiple upstream controllers (PSP GIC, Secondary Service Processor (SSP) NVIC, Tertiary Service Processor (TSP) NVIC, and Boot MCU interrupt controller). This design requires route resolution and a controller hierarchy model which the A0 driver cannot represent. Remove driver support for A0 in favour of the driver for the A2 production design. Signed-off-by: Ryan Chen --- drivers/irqchip/Makefile | 1 - drivers/irqchip/irq-aspeed-intc.c | 139 ----------------------------------= ---- 2 files changed, 140 deletions(-) diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ac04a4b97797..3d02441b3ee6 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -92,7 +92,6 @@ obj-$(CONFIG_LS_SCFG_MSI) +=3D irq-ls-scfg-msi.o obj-$(CONFIG_ASPEED_AST2700_INTC) +=3D irq-ast2700.o irq-ast2700-intc0.o i= rq-ast2700-intc1.o obj-$(CONFIG_ASPEED_AST2700_INTC_TEST) +=3D irq-ast2700-intc0-test.o obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-a= speed-scu-ic.o -obj-$(CONFIG_ARCH_ASPEED) +=3D irq-aspeed-intc.o obj-$(CONFIG_STM32MP_EXTI) +=3D irq-stm32mp-exti.o obj-$(CONFIG_STM32_EXTI) +=3D irq-stm32-exti.o obj-$(CONFIG_QCOM_IRQ_COMBINER) +=3D qcom-irq-combiner.o diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed= -intc.c deleted file mode 100644 index 4fb0dd8349da..000000000000 --- a/drivers/irqchip/irq-aspeed-intc.c +++ /dev/null @@ -1,139 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Aspeed Interrupt Controller. - * - * Copyright (C) 2023 ASPEED Technology Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define INTC_INT_ENABLE_REG 0x00 -#define INTC_INT_STATUS_REG 0x04 -#define INTC_IRQS_PER_WORD 32 - -struct aspeed_intc_ic { - void __iomem *base; - raw_spinlock_t gic_lock; - raw_spinlock_t intc_lock; - struct irq_domain *irq_domain; -}; - -static void aspeed_intc_ic_irq_handler(struct irq_desc *desc) -{ - struct aspeed_intc_ic *intc_ic =3D irq_desc_get_handler_data(desc); - struct irq_chip *chip =3D irq_desc_get_chip(desc); - - chained_irq_enter(chip, desc); - - scoped_guard(raw_spinlock, &intc_ic->gic_lock) { - unsigned long bit, status; - - status =3D readl(intc_ic->base + INTC_INT_STATUS_REG); - for_each_set_bit(bit, &status, INTC_IRQS_PER_WORD) { - generic_handle_domain_irq(intc_ic->irq_domain, bit); - writel(BIT(bit), intc_ic->base + INTC_INT_STATUS_REG); - } - } - - chained_irq_exit(chip, desc); -} - -static void aspeed_intc_irq_mask(struct irq_data *data) -{ - struct aspeed_intc_ic *intc_ic =3D irq_data_get_irq_chip_data(data); - unsigned int mask =3D readl(intc_ic->base + INTC_INT_ENABLE_REG) & ~BIT(d= ata->hwirq); - - guard(raw_spinlock)(&intc_ic->intc_lock); - writel(mask, intc_ic->base + INTC_INT_ENABLE_REG); -} - -static void aspeed_intc_irq_unmask(struct irq_data *data) -{ - struct aspeed_intc_ic *intc_ic =3D irq_data_get_irq_chip_data(data); - unsigned int unmask =3D readl(intc_ic->base + INTC_INT_ENABLE_REG) | BIT(= data->hwirq); - - guard(raw_spinlock)(&intc_ic->intc_lock); - writel(unmask, intc_ic->base + INTC_INT_ENABLE_REG); -} - -static struct irq_chip aspeed_intc_chip =3D { - .name =3D "ASPEED INTC", - .irq_mask =3D aspeed_intc_irq_mask, - .irq_unmask =3D aspeed_intc_irq_unmask, -}; - -static int aspeed_intc_ic_map_irq_domain(struct irq_domain *domain, unsign= ed int irq, - irq_hw_number_t hwirq) -{ - irq_set_chip_and_handler(irq, &aspeed_intc_chip, handle_level_irq); - irq_set_chip_data(irq, domain->host_data); - - return 0; -} - -static const struct irq_domain_ops aspeed_intc_ic_irq_domain_ops =3D { - .map =3D aspeed_intc_ic_map_irq_domain, -}; - -static int __init aspeed_intc_ic_of_init(struct device_node *node, - struct device_node *parent) -{ - struct aspeed_intc_ic *intc_ic; - int irq, i, ret =3D 0; - - intc_ic =3D kzalloc_obj(*intc_ic); - if (!intc_ic) - return -ENOMEM; - - intc_ic->base =3D of_iomap(node, 0); - if (!intc_ic->base) { - pr_err("Failed to iomap intc_ic base\n"); - ret =3D -ENOMEM; - goto err_free_ic; - } - writel(0xffffffff, intc_ic->base + INTC_INT_STATUS_REG); - writel(0x0, intc_ic->base + INTC_INT_ENABLE_REG); - - intc_ic->irq_domain =3D irq_domain_create_linear(of_fwnode_handle(node), = INTC_IRQS_PER_WORD, - &aspeed_intc_ic_irq_domain_ops, intc_ic); - if (!intc_ic->irq_domain) { - ret =3D -ENOMEM; - goto err_iounmap; - } - - raw_spin_lock_init(&intc_ic->gic_lock); - raw_spin_lock_init(&intc_ic->intc_lock); - - /* Check all the irq numbers valid. If not, unmaps all the base and frees= the data. */ - for (i =3D 0; i < of_irq_count(node); i++) { - irq =3D irq_of_parse_and_map(node, i); - if (!irq) { - pr_err("Failed to get irq number\n"); - ret =3D -EINVAL; - goto err_iounmap; - } - } - - for (i =3D 0; i < of_irq_count(node); i++) { - irq =3D irq_of_parse_and_map(node, i); - irq_set_chained_handler_and_data(irq, aspeed_intc_ic_irq_handler, intc_i= c); - } - - return 0; - -err_iounmap: - iounmap(intc_ic->base); -err_free_ic: - kfree(intc_ic); - return ret; -} - -IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_= of_init); --=20 2.34.1