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Sun, 29 Mar 2026 08:24:47 -0700 (PDT) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Sun, 29 Mar 2026 08:24:46 -0700 Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Sun, 29 Mar 2026 08:24:45 -0700 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Sun, 29 Mar 2026 08:24:45 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 0839F3F70A3; Sun, 29 Mar 2026 08:24:42 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , Subject: [PATCH v2 1/2] dt-bindings: perf: marvell: Document CN20K DDR PMU Date: Sun, 29 Mar 2026 20:54:38 +0530 Message-ID: <20260329152439.10573-2-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260329152439.10573-1-gakula@marvell.com> References: <20260329152439.10573-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Authority-Analysis: v=2.4 cv=bfxmkePB c=1 sm=1 tr=0 ts=69c9443f cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=gEfo2CItAAAA:8 a=M5GUcnROAAAA:8 a=cxBr6QS3EhuSzrwsu80A:9 a=sptkURWiP4Gy88Gu7hUp:22 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: tb7vR8qxdi2mztV-MXqgls793zxXo8UH X-Proofpoint-GUID: tb7vR8qxdi2mztV-MXqgls793zxXo8UH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI5MDExOSBTYWx0ZWRfX5P44iiAmwQaz ivRyhs/Bliq93ik0LWMM6tdYf7p4FraZ3jFHBFDz9C8Y8HN7Wf2dG4QD1dt29Ek95v35Eh/I3xu j9CMu2ewE/WbcA+5DDCDe7ExQwtdUqSinV/4WcQiKSv+q8Zjx38pgi5nm3rY7meeW+9B22PvmK0 02KCsOv+q5soOJf4qtoo4Ogu0W7ZG3oerz9WPIkwMI2st+cc/F/0GSYiLvFZBF+nZcXEiWtaivB 4qHpa9UW+vUR6rs6OqLgYkDqqmurmiSnW9hSBqtjOsyjYQv+jh5HFXOT+fUrM82rb37HZ2t6H2b lLTPzq7WwokaGDTINl0duiXVYevcf/RLWTsoo7QPbHzT7jyx08yJ28oxT9rPiC8795vRAEmwR1X aT/Gsaw0fgXJrpNJB/dwpGr8WDYYj8U3p/TWHhBixNI/PX0Dse2spo80iHtWYxZUy+2vGONb1Ru PxmjNcmqmMzKyM4gF7w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-29_04,2026-03-28_01,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a devicetree binding for the Marvell CN20K DDR performance monitor block, including the marvell,cn20k-ddr-pmu compatible string and the required MMIO reg region. Signed-off-by: Geetha sowjanya --- Changes in v1: - Added a description field to the binding. - Simplified the compatible property using 'const' instead of 'items/enum'. - Updated the example node name to include a unit-address matching the reg = base. .../bindings/perf/marvell-cn20k-ddr.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/perf/marvell-cn20k-dd= r.yaml diff --git a/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml = b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml new file mode 100644 index 000000000000..470eac0a53c4 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/marvell-cn20k-ddr.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/marvell-cn20k-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell CN20K DDR performance monitor + +description: + Performance Monitoring Unit (PMU) for the DDR controller + in Marvell CN20K SoCs. + +maintainers: + - Geetha sowjanya + +properties: + compatible: + const: marvell,cn20k-ddr-pmu + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + ddr-pmu@c200000000 { + compatible =3D "marvell,cn20k-ddr-pmu"; + reg =3D <0xc200 0x00000000 0x0 0x100000>; + }; + }; --=20 2.25.1