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Sat, 28 Mar 2026 03:33:27 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 1/3] irqchip/renesas-rzg2l: Fix shared IRQ bit not cleared on free Date: Sat, 28 Mar 2026 10:33:18 +0000 Message-ID: <20260328103324.134131-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260328103324.134131-1-biju.das.jz@bp.renesas.com> References: <20260328103324.134131-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Calling irq_domain_free_irqs_common() internally calls irq_domain_reset_irq_data(), which explicitly sets irq_data->hwirq to 0. Consequently, irqd_to_hwirq(d) returns 0 when called after it. Since 0 falls outside the valid shared IRQ ranges, rzg2l_irqc_is_shared_and_get_irq_num() evaluates to false, completely bypassing the test_and_clear_bit() operation. This leaves the bit set in priv->used_irqs, causing future allocations to fail with -EBUSY. Fix this by retrieving irq_data and caching hwirq before calling irq_domain_free_irqs_common(). Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index f5c4d7e0aec3..3cc1efd8d914 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -699,15 +699,14 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain= , unsigned int virq, =20 static void rzg2l_irqc_free(struct irq_domain *domain, unsigned int virq, = unsigned int nr_irqs) { + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); struct rzg2l_irqc_priv *priv =3D domain->host_data; + irq_hw_number_t hwirq =3D irqd_to_hwirq(d); =20 irq_domain_free_irqs_common(domain, virq, nr_irqs); =20 - if (priv->info.shared_irq_cnt) { - struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); - - rzg2l_irqc_shared_irq_free(priv, irqd_to_hwirq(d)); - } + if (priv->info.shared_irq_cnt) + rzg2l_irqc_shared_irq_free(priv, hwirq); } =20 static const struct irq_domain_ops rzg2l_irqc_domain_ops =3D { --=20 2.43.0 From nobody Thu Apr 2 14:13:09 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D89A935CB62 for ; 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charset="utf-8" From: Biju Das Simplify the locking logic in rzg2l_irq_set_type() by using guard(), eliminating the need for an explicit unlock call. While at it, add the missing cleanup.h header file. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 3cc1efd8d914..0f1157d5ce55 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include #include @@ -373,14 +374,13 @@ static int rzg2l_irq_set_type(struct irq_data *d, uns= igned int type) return -EINVAL; } =20 - raw_spin_lock(&priv->lock); + guard(raw_spinlock)(&priv->lock); tmp =3D readl_relaxed(priv->base + IITSR); tmp &=3D ~IITSR_IITSEL_MASK(iitseln); tmp |=3D IITSR_IITSEL(iitseln, sense); if (clear_irq_int) rzg2l_clear_irq_int(priv, hwirq); writel_relaxed(tmp, priv->base + IITSR); - raw_spin_unlock(&priv->lock); =20 return 0; } --=20 2.43.0 From nobody Thu Apr 2 14:13:09 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B4D033C18B for ; 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Sat, 28 Mar 2026 03:33:29 -0700 (PDT) Received: from localhost.localdomain ([2a00:23c4:a758:8a01:8a55:5310:98fe:930d]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-487270fd880sm42270035e9.8.2026.03.28.03.33.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Mar 2026 03:33:29 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Thomas Gleixner Cc: Biju Das , linux-kernel@vger.kernel.org, Geert Uytterhoeven , Prabhakar Mahadev Lad , Biju Das , linux-renesas-soc@vger.kernel.org Subject: [PATCH 3/3] irqchip/renesas-rzg2l: Add NMI support Date: Sat, 28 Mar 2026 10:33:20 +0000 Message-ID: <20260328103324.134131-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260328103324.134131-1-biju.das.jz@bp.renesas.com> References: <20260328103324.134131-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3L SoC has an NMI interrupt. Add support for the NMI interrupt. Signed-off-by: Biju Das --- drivers/irqchip/irq-renesas-rzg2l.c | 92 ++++++++++++++++++++++++++++- 1 file changed, 91 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-rene= sas-rzg2l.c index 0f1157d5ce55..622a9045b606 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -21,11 +21,14 @@ #include #include =20 +#define IRQC_NMI 0 #define IRQC_IRQ_START 1 #define IRQC_TINT_COUNT 32 #define IRQC_SHARED_IRQ_COUNT 8 #define IRQC_IRQ_SHARED_START (IRQC_IRQ_START + IRQC_SHARED_IRQ_COUNT) =20 +#define NSCR 0x0 +#define NITSR 0x4 #define ISCR 0x10 #define IITSR 0x14 #define TSCR 0x20 @@ -44,6 +47,9 @@ #define TSSR_OFFSET(n) ((n) % 4) #define TSSR_INDEX(n) ((n) / 4) =20 +#define NITSR_NTSEL_EDGE_FALLING 0 +#define NITSR_NTSEL_EDGE_RISING 1 + #define TITSR_TITSEL_EDGE_RISING 0 #define TITSR_TITSEL_EDGE_FALLING 1 #define TITSR_TITSEL_LEVEL_HIGH 2 @@ -64,11 +70,13 @@ =20 /** * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/re= sume) + * @nitsr: NITSR register * @iitsr: IITSR register * @inttsel: INTTSEL register * @titsr: TITSR registers */ struct rzg2l_irqc_reg_cache { + u32 nitsr; u32 iitsr; u32 inttsel; u32 titsr[2]; @@ -117,6 +125,22 @@ static struct rzg2l_irqc_priv *irq_data_to_priv(struct= irq_data *data) return data->domain->host_data; } =20 +static void rzg2l_clear_nmi_int(struct rzg2l_irqc_priv *priv, unsigned int= hwirq) +{ + u32 bit =3D BIT(hwirq); + u32 reg; + + reg =3D readl_relaxed(priv->base + NSCR); + if (reg & bit) { + writel_relaxed(reg & ~bit, priv->base + NSCR); + /* + * Enforce that the posted write is flushed to prevent that the + * just handled interrupt is raised again. + */ + readl_relaxed(priv->base + NSCR); + } +} + static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int= hwirq) { unsigned int hw_irq =3D hwirq - IRQC_IRQ_START; @@ -156,6 +180,17 @@ static void rzg2l_clear_tint_int(struct rzg2l_irqc_pri= v *priv, unsigned int hwir } } =20 +static void rzg2l_irqc_nmi_eoi(struct irq_data *d) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + unsigned int hw_irq =3D irqd_to_hwirq(d); + + scoped_guard(raw_spinlock, &priv->lock) + rzg2l_clear_nmi_int(priv, hw_irq); + + irq_chip_eoi_parent(d); +} + static void rzg2l_irqc_irq_eoi(struct irq_data *d) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -342,6 +377,29 @@ static void rzg2l_irqc_tint_enable(struct irq_data *d) irq_chip_enable_parent(d); } =20 +static int rzg2l_nmi_set_type(struct irq_data *d, unsigned int type) +{ + struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); + u32 sense; + + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + sense =3D NITSR_NTSEL_EDGE_FALLING; + break; + + case IRQ_TYPE_EDGE_RISING: + sense =3D NITSR_NTSEL_EDGE_RISING; + break; + + default: + return -EINVAL; + } + + writel_relaxed(sense, priv->base + NITSR); + + return 0; +} + static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) { struct rzg2l_irqc_priv *priv =3D irq_data_to_priv(d); @@ -468,11 +526,23 @@ static int rzg2l_irqc_tint_set_type(struct irq_data *= d, unsigned int type) return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); } =20 +static int rzg2l_irqc_nmi_set_type(struct irq_data *d, unsigned int type) +{ + int ret; + + ret =3D rzg2l_nmi_set_type(d, type); + if (ret) + return ret; + + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); +} + static int rzg2l_irqc_irq_suspend(void *data) { struct rzg2l_irqc_reg_cache *cache =3D &rzg2l_irqc_data->cache; void __iomem *base =3D rzg2l_irqc_data->base; =20 + cache->nitsr =3D readl_relaxed(base + NITSR); cache->iitsr =3D readl_relaxed(base + IITSR); if (rzg2l_irqc_data->info.shared_irq_cnt) cache->inttsel =3D readl_relaxed(base + INTTSEL); @@ -497,6 +567,7 @@ static void rzg2l_irqc_irq_resume(void *data) if (rzg2l_irqc_data->info.shared_irq_cnt) writel_relaxed(cache->inttsel, base + INTTSEL); writel_relaxed(cache->iitsr, base + IITSR); + writel_relaxed(cache->nitsr, base + NITSR); } =20 static const struct syscore_ops rzg2l_irqc_syscore_ops =3D { @@ -508,6 +579,23 @@ static struct syscore rzg2l_irqc_syscore =3D { .ops =3D &rzg2l_irqc_syscore_ops, }; =20 +static const struct irq_chip rzg2l_irqc_nmi_chip =3D { + .name =3D "rzg2l-irqc", + .irq_eoi =3D rzg2l_irqc_nmi_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D irq_chip_disable_parent, + .irq_enable =3D irq_chip_enable_parent, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D rzg2l_irqc_nmi_set_type, + .irq_set_affinity =3D irq_chip_set_affinity_parent, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE, +}; + static const struct irq_chip rzg2l_irqc_irq_chip =3D { .name =3D "rzg2l-irqc", .irq_eoi =3D rzg2l_irqc_irq_eoi, @@ -663,7 +751,9 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, = unsigned int virq, * from 16-31 bits. TINT from the pinctrl driver needs to be programmed * in IRQC registers to enable a given gpio pin as interrupt. */ - if (hwirq > priv->info.irq_count) { + if (hwirq =3D=3D IRQC_NMI) { + chip =3D &rzg2l_irqc_nmi_chip; + } else if (hwirq > priv->info.irq_count) { tint =3D TINT_EXTRACT_GPIOINT(hwirq); hwirq =3D TINT_EXTRACT_HWIRQ(hwirq); chip =3D priv->tint_chip; --=20 2.43.0