From nobody Thu Apr 2 14:14:44 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8891334D911 for ; Sat, 28 Mar 2026 08:06:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774685203; cv=none; b=ay9409rw/AbMBy+UZyAQX6zLEbzw0Uo3xhRzQ0yl7Ap5Ua+hM41gWLWkiRNo6W8IZ0U7yBhV6hMQK7tysQGQzbSJsJ4Sfn/Fbu4C1GeBsIvUW+wIV4X3v3m2OYEitq5O44oFw2yMCzs3DVlSeXm/J/5/UuG1lPbdu10Kr0ynCsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774685203; c=relaxed/simple; bh=JVFm5Jhd1CBr5geTZDgH/05roYKWC/LQdWuzguZcszY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m7M2vAK0YQpYMlFLCBRgDbrmvp4XAxn/F2O+3Gu0D0YBj6Kh1Cf02ZBN0bGbYZzrbFcUqyYCB/Ac5F0WqqYaEgpGQY3H3hVIevPST4+j8YsqzvqWLbZYP85oA0eylZQrmuywi21cZaexv8wIcpR2LAkXY6GH4MKWRPCivh+mlcw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=eub+fkd5; arc=none smtp.client-ip=170.10.129.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="eub+fkd5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1774685200; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=88u8u+mfyZVdVTX7DETeyz8YIHQFshsiQRYJ3CgX5YA=; b=eub+fkd5xIHLiiZOPg/esGRc4JIZ7zpEsDcwMg1NaX+NTEdg/hgqrY2G1eKFzBkzObWncE GKgtdwHVfdmMZc30W8ehyd4QTiRrXR4Aq1HU/6PXsZSiPB3nhlSZ0ELeFylWPlMW0Vgn+P ARf27xQU0tOE1p6wkeH1VySWxKiXkpo= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-417-YdgHh7shPyKY0DoetZW19A-1; Sat, 28 Mar 2026 04:06:37 -0400 X-MC-Unique: YdgHh7shPyKY0DoetZW19A-1 X-Mimecast-MFC-AGG-ID: YdgHh7shPyKY0DoetZW19A_1774685195 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id CA89918005B3; Sat, 28 Mar 2026 08:06:34 +0000 (UTC) Received: from p16v.redhat.com (unknown [10.44.32.48]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id C95CE1800351; Sat, 28 Mar 2026 08:06:30 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Petr Oros , Prathosh Satish , Arkadiusz Kubalewski , Jiri Pirko , Michal Schmidt , Simon Horman , Vadim Fedorenko , linux-kernel@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, Pasi Vaananen Subject: [PATCH net-next v2 1/5] dpll: zl3073x: clean up esync get/set and use zl3073x_out_is_ndiv() Date: Sat, 28 Mar 2026 09:06:20 +0100 Message-ID: <20260328080624.593916-2-ivecera@redhat.com> In-Reply-To: <20260328080624.593916-1-ivecera@redhat.com> References: <20260328080624.593916-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Return -EOPNOTSUPP early in esync_get callbacks when esync is not supported instead of conditionally populating the range at the end. This simplifies the control flow by removing the finish label/goto in the output variant and the conditional range assignment in both input and output variants. Replace open-coded N-div signal format switch statements with zl3073x_out_is_ndiv() helper in esync_get, esync_set and frequency_set callbacks. Reviewed-by: Petr Oros Reviewed-by: Prathosh Satish Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/dpll.c | 64 ++++++++++++------------------------- 1 file changed, 20 insertions(+), 44 deletions(-) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index a29f606318f6d..2476c14028210 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -131,6 +131,12 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin= *dpll_pin, ref_id =3D zl3073x_input_pin_ref_get(pin->id); ref =3D zl3073x_ref_state_get(zldev, ref_id); =20 + if (!pin->esync_control || zl3073x_ref_freq_get(ref) <=3D 1) + return -EOPNOTSUPP; + + esync->range =3D esync_freq_ranges; + esync->range_num =3D ARRAY_SIZE(esync_freq_ranges); + switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: esync->freq =3D ref->esync_n_div =3D=3D ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; @@ -142,17 +148,6 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin= *dpll_pin, break; } =20 - /* If the pin supports esync control expose its range but only - * if the current reference frequency is > 1 Hz. - */ - if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) { - esync->range =3D esync_freq_ranges; - esync->range_num =3D ARRAY_SIZE(esync_freq_ranges); - } else { - esync->range =3D NULL; - esync->range_num =3D 0; - } - return 0; } =20 @@ -582,8 +577,8 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin= *dpll_pin, struct zl3073x_dpll_pin *pin =3D pin_priv; const struct zl3073x_synth *synth; const struct zl3073x_out *out; + u32 synth_freq, out_freq; u8 clock_type, out_id; - u32 synth_freq; =20 out_id =3D zl3073x_output_pin_out_get(pin->id); out =3D zl3073x_out_state_get(zldev, out_id); @@ -592,17 +587,19 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_p= in *dpll_pin, * for N-division is also used for the esync divider so both cannot * be used. */ - switch (zl3073x_out_signal_format_get(out)) { - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: + if (zl3073x_out_is_ndiv(out)) return -EOPNOTSUPP; - default: - break; - } =20 /* Get attached synth frequency */ synth =3D zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); synth_freq =3D zl3073x_synth_freq_get(synth); + out_freq =3D synth_freq / out->div; + + if (!pin->esync_control || out_freq <=3D 1) + return -EOPNOTSUPP; + + esync->range =3D esync_freq_ranges; + esync->range_num =3D ARRAY_SIZE(esync_freq_ranges); =20 clock_type =3D FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); if (clock_type !=3D ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { @@ -610,11 +607,11 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_p= in *dpll_pin, esync->freq =3D 0; esync->pulse =3D 0; =20 - goto finish; + return 0; } =20 /* Compute esync frequency */ - esync->freq =3D synth_freq / out->div / out->esync_n_period; + esync->freq =3D out_freq / out->esync_n_period; =20 /* By comparing the esync_pulse_width to the half of the pulse width * the esync pulse percentage can be determined. @@ -623,18 +620,6 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pi= n *dpll_pin, */ esync->pulse =3D (50 * out->esync_n_width) / out->div; =20 -finish: - /* Set supported esync ranges if the pin supports esync control and - * if the output frequency is > 1 Hz. - */ - if (pin->esync_control && (synth_freq / out->div) > 1) { - esync->range =3D esync_freq_ranges; - esync->range_num =3D ARRAY_SIZE(esync_freq_ranges); - } else { - esync->range =3D NULL; - esync->range_num =3D 0; - } - return 0; } =20 @@ -660,13 +645,8 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_pi= n *dpll_pin, * for N-division is also used for the esync divider so both cannot * be used. */ - switch (zl3073x_out_signal_format_get(&out)) { - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: - case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: + if (zl3073x_out_is_ndiv(&out)) return -EOPNOTSUPP; - default: - break; - } =20 /* Select clock type */ if (freq) @@ -728,9 +708,9 @@ zl3073x_dpll_output_pin_frequency_set(const struct dpll= _pin *dpll_pin, struct zl3073x_dev *zldev =3D zldpll->dev; struct zl3073x_dpll_pin *pin =3D pin_priv; const struct zl3073x_synth *synth; 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charset="utf-8" Replace open-coded clear-and-set bitfield operations with FIELD_MODIFY(). Reviewed-by: Petr Oros Reviewed-by: Prathosh Satish Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/chan.h | 17 ++++++----------- drivers/dpll/zl3073x/core.c | 3 +-- drivers/dpll/zl3073x/flash.c | 3 +-- 3 files changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/dpll/zl3073x/chan.h b/drivers/dpll/zl3073x/chan.h index e0f02d3432086..481da2133202b 100644 --- a/drivers/dpll/zl3073x/chan.h +++ b/drivers/dpll/zl3073x/chan.h @@ -66,8 +66,7 @@ static inline u8 zl3073x_chan_ref_get(const struct zl3073= x_chan *chan) */ static inline void zl3073x_chan_mode_set(struct zl3073x_chan *chan, u8 mod= e) { - chan->mode_refsel &=3D ~ZL_DPLL_MODE_REFSEL_MODE; - chan->mode_refsel |=3D FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode); + FIELD_MODIFY(ZL_DPLL_MODE_REFSEL_MODE, &chan->mode_refsel, mode); } =20 /** @@ -77,8 +76,7 @@ static inline void zl3073x_chan_mode_set(struct zl3073x_c= han *chan, u8 mode) */ static inline void zl3073x_chan_ref_set(struct zl3073x_chan *chan, u8 ref) { - chan->mode_refsel &=3D ~ZL_DPLL_MODE_REFSEL_REF; - chan->mode_refsel |=3D FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); + FIELD_MODIFY(ZL_DPLL_MODE_REFSEL_REF, &chan->mode_refsel, ref); } =20 /** @@ -110,13 +108,10 @@ zl3073x_chan_ref_prio_set(struct zl3073x_chan *chan, = u8 ref, u8 prio) { u8 *val =3D &chan->ref_prio[ref / 2]; =20 - if (!(ref & 1)) { - *val &=3D ~ZL_DPLL_REF_PRIO_REF_P; - *val |=3D FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); - } else { - *val &=3D ~ZL_DPLL_REF_PRIO_REF_N; - *val |=3D FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); - } + if (!(ref & 1)) + FIELD_MODIFY(ZL_DPLL_REF_PRIO_REF_P, val, prio); + else + FIELD_MODIFY(ZL_DPLL_REF_PRIO_REF_N, val, prio); } =20 /** diff --git a/drivers/dpll/zl3073x/core.c b/drivers/dpll/zl3073x/core.c index 6363002d48d46..7eebfc1ad1019 100644 --- a/drivers/dpll/zl3073x/core.c +++ b/drivers/dpll/zl3073x/core.c @@ -743,8 +743,7 @@ int zl3073x_dev_phase_avg_factor_set(struct zl3073x_dev= *zldev, u8 factor) value =3D (factor + 1) & 0x0f; =20 /* Update phase measurement control register */ - dpll_meas_ctrl &=3D ~ZL_DPLL_MEAS_CTRL_AVG_FACTOR; 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charset="utf-8" Add ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR and ZL_REF_SYNC_CTRL_PAIR register definitions. Add inline helpers to get and set the sync control mode and sync pair fields of the reference sync control register: zl3073x_ref_sync_mode_get/set() - ZL_REF_SYNC_CTRL_MODE field zl3073x_ref_sync_pair_get/set() - ZL_REF_SYNC_CTRL_PAIR field Add inline helpers to get and set the clock type field of the output mode register: zl3073x_out_clock_type_get/set() - ZL_OUTPUT_MODE_CLOCK_TYPE field Convert existing esync callbacks to use the new helpers. Reviewed-by: Petr Oros Reviewed-by: Prathosh Satish Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/dpll.c | 24 ++++++++----------- drivers/dpll/zl3073x/out.h | 22 ++++++++++++++++++ drivers/dpll/zl3073x/ref.h | 46 +++++++++++++++++++++++++++++++++++++ drivers/dpll/zl3073x/regs.h | 2 ++ 4 files changed, 80 insertions(+), 14 deletions(-) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index 2476c14028210..b5b411425f6b3 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -137,7 +137,7 @@ zl3073x_dpll_input_pin_esync_get(const struct dpll_pin = *dpll_pin, esync->range =3D esync_freq_ranges; esync->range_num =3D ARRAY_SIZE(esync_freq_ranges); =20 - switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { + switch (zl3073x_ref_sync_mode_get(ref)) { case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: esync->freq =3D ref->esync_n_div =3D=3D ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; esync->pulse =3D 25; @@ -173,8 +173,7 @@ zl3073x_dpll_input_pin_esync_set(const struct dpll_pin = *dpll_pin, else sync_mode =3D ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; =20 - ref.sync_ctrl &=3D ~ZL_REF_SYNC_CTRL_MODE; - ref.sync_ctrl |=3D FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); + zl3073x_ref_sync_mode_set(&ref, sync_mode); =20 if (freq) { /* 1 Hz is only supported frequency now */ @@ -578,7 +577,7 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin= *dpll_pin, const struct zl3073x_synth *synth; const struct zl3073x_out *out; u32 synth_freq, out_freq; - u8 clock_type, out_id; + u8 out_id; =20 out_id =3D zl3073x_output_pin_out_get(pin->id); out =3D zl3073x_out_state_get(zldev, out_id); @@ -601,8 +600,7 @@ zl3073x_dpll_output_pin_esync_get(const struct dpll_pin= *dpll_pin, esync->range =3D esync_freq_ranges; esync->range_num =3D ARRAY_SIZE(esync_freq_ranges); =20 - clock_type =3D FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); - if (clock_type !=3D ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { + if (zl3073x_out_clock_type_get(out) !=3D ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC)= { /* No need to read esync data if it is not enabled */ esync->freq =3D 0; esync->pulse =3D 0; @@ -635,8 +633,8 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_pin= *dpll_pin, struct zl3073x_dpll_pin *pin =3D pin_priv; const struct zl3073x_synth *synth; struct zl3073x_out out; - u8 clock_type, out_id; u32 synth_freq; + u8 out_id; =20 out_id =3D zl3073x_output_pin_out_get(pin->id); out =3D *zl3073x_out_state_get(zldev, out_id); @@ -648,15 +646,13 @@ zl3073x_dpll_output_pin_esync_set(const struct dpll_p= in *dpll_pin, if (zl3073x_out_is_ndiv(&out)) return -EOPNOTSUPP; =20 - /* Select clock type */ + /* Update clock type in output mode */ if (freq) - clock_type =3D ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; + zl3073x_out_clock_type_set(&out, + ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC); else - clock_type =3D ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; - - /* Update clock type in output mode */ - out.mode &=3D ~ZL_OUTPUT_MODE_CLOCK_TYPE; - out.mode |=3D FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); + zl3073x_out_clock_type_set(&out, + ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL); =20 /* If esync is being disabled just write mailbox and finish */ if (!freq) diff --git a/drivers/dpll/zl3073x/out.h b/drivers/dpll/zl3073x/out.h index edf40432bba5f..660889c57bffa 100644 --- a/drivers/dpll/zl3073x/out.h +++ b/drivers/dpll/zl3073x/out.h @@ -42,6 +42,28 @@ const struct zl3073x_out *zl3073x_out_state_get(struct z= l3073x_dev *zldev, int zl3073x_out_state_set(struct zl3073x_dev *zldev, u8 index, const struct zl3073x_out *out); =20 +/** + * zl3073x_out_clock_type_get - get output clock type + * @out: pointer to out state + * + * Return: clock type of given output (ZL_OUTPUT_MODE_CLOCK_TYPE_*) + */ +static inline u8 zl3073x_out_clock_type_get(const struct zl3073x_out *out) +{ + return FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); +} + +/** + * zl3073x_out_clock_type_set - set output clock type + * @out: pointer to out state + * @type: clock type (ZL_OUTPUT_MODE_CLOCK_TYPE_*) + */ +static inline void +zl3073x_out_clock_type_set(struct zl3073x_out *out, u8 type) +{ + FIELD_MODIFY(ZL_OUTPUT_MODE_CLOCK_TYPE, &out->mode, type); +} + /** * zl3073x_out_signal_format_get - get output signal format * @out: pointer to out state diff --git a/drivers/dpll/zl3073x/ref.h b/drivers/dpll/zl3073x/ref.h index 06d8d4d97ea26..09fab97a71d7e 100644 --- a/drivers/dpll/zl3073x/ref.h +++ b/drivers/dpll/zl3073x/ref.h @@ -106,6 +106,52 @@ zl3073x_ref_freq_set(struct zl3073x_ref *ref, u32 freq) return 0; } =20 +/** + * zl3073x_ref_sync_mode_get - get sync control mode + * @ref: pointer to ref state + * + * Return: sync control mode (ZL_REF_SYNC_CTRL_MODE_*) + */ +static inline u8 +zl3073x_ref_sync_mode_get(const struct zl3073x_ref *ref) +{ + return FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl); +} + +/** + * zl3073x_ref_sync_mode_set - set sync control mode + * @ref: pointer to ref state + * @mode: sync control mode (ZL_REF_SYNC_CTRL_MODE_*) + */ +static inline void +zl3073x_ref_sync_mode_set(struct zl3073x_ref *ref, u8 mode) +{ + FIELD_MODIFY(ZL_REF_SYNC_CTRL_MODE, &ref->sync_ctrl, mode); +} + +/** + * zl3073x_ref_sync_pair_get - get sync pair reference index + * @ref: pointer to ref state + * + * Return: paired reference index + */ +static inline u8 +zl3073x_ref_sync_pair_get(const struct zl3073x_ref *ref) +{ + return FIELD_GET(ZL_REF_SYNC_CTRL_PAIR, ref->sync_ctrl); +} + +/** + * zl3073x_ref_sync_pair_set - set sync pair reference index + * @ref: pointer to ref state + * @pair: paired reference index + */ +static inline void +zl3073x_ref_sync_pair_set(struct zl3073x_ref *ref, u8 pair) +{ + FIELD_MODIFY(ZL_REF_SYNC_CTRL_PAIR, &ref->sync_ctrl, pair); +} + /** * zl3073x_ref_is_diff - check if the given input reference is differential * @ref: pointer to ref state diff --git a/drivers/dpll/zl3073x/regs.h b/drivers/dpll/zl3073x/regs.h index 5ae50cb761a97..d425dc67250fe 100644 --- a/drivers/dpll/zl3073x/regs.h +++ b/drivers/dpll/zl3073x/regs.h @@ -213,7 +213,9 @@ #define ZL_REG_REF_SYNC_CTRL ZL_REG(10, 0x2e, 1) #define ZL_REF_SYNC_CTRL_MODE GENMASK(2, 0) #define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF 0 +#define ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR 1 #define ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75 2 +#define ZL_REF_SYNC_CTRL_PAIR GENMASK(7, 4) =20 #define ZL_REG_REF_ESYNC_DIV ZL_REG(10, 0x30, 4) #define ZL_REF_ESYNC_DIV_1HZ 0 --=20 2.52.0 From nobody Thu Apr 2 14:14:44 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31A623644DA for ; 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charset="utf-8" Add ref-sync-sources phandle-array property to the dpll-pin schema allowing board designers to declare which input pins can serve as sync sources in a Reference-Sync pair. A Ref-Sync pair consists of a clock reference and a low-frequency sync signal where the DPLL locks to the clock but phase-aligns to the sync reference. Update both examples in the Microchip ZL3073x binding to demonstrate the new property with a 1 PPS sync source paired to a clock source. Reviewed-by: Petr Oros Reviewed-by: Prathosh Satish Signed-off-by: Ivan Vecera --- .../devicetree/bindings/dpll/dpll-pin.yaml | 11 +++++++ .../bindings/dpll/microchip,zl30731.yaml | 30 ++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml b/Documen= tation/devicetree/bindings/dpll/dpll-pin.yaml index 51db93b77306f..7084f102e274c 100644 --- a/Documentation/devicetree/bindings/dpll/dpll-pin.yaml +++ b/Documentation/devicetree/bindings/dpll/dpll-pin.yaml @@ -36,6 +36,17 @@ properties: description: String exposed as the pin board label $ref: /schemas/types.yaml#/definitions/string =20 + ref-sync-sources: + description: | + List of phandles to input pins that can serve as the sync source + in a Reference-Sync pair with this pin acting as the clock source. + A Ref-Sync pair consists of a clock reference and a low-frequency + sync signal. The DPLL locks to the clock reference but + phase-aligns to the sync reference. + Only valid for input pins. Each referenced pin must be a + different input pin on the same device. + $ref: /schemas/types.yaml#/definitions/phandle-array + supported-frequencies-hz: description: List of supported frequencies for this pin, expressed in = Hz. =20 diff --git a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml = b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml index 17747f754b845..fa5a8f8e390cd 100644 --- a/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml +++ b/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml @@ -52,11 +52,19 @@ examples: #address-cells =3D <1>; #size-cells =3D <0>; =20 - pin@0 { /* REF0P */ + sync0: pin@0 { /* REF0P - 1 PPS sync source */ reg =3D <0>; connection-type =3D "ext"; - label =3D "Input 0"; - supported-frequencies-hz =3D /bits/ 64 <1 1000>; + label =3D "SMA1"; + supported-frequencies-hz =3D /bits/ 64 <1>; + }; + + pin@1 { /* REF0N - clock source, can pair with sync0 */ + reg =3D <1>; + connection-type =3D "ext"; + label =3D "SMA2"; + supported-frequencies-hz =3D /bits/ 64 <10000 10000000>; + ref-sync-sources =3D <&sync0>; }; }; =20 @@ -90,11 +98,19 @@ examples: #address-cells =3D <1>; #size-cells =3D <0>; =20 - pin@0 { /* REF0P */ + sync1: pin@0 { /* REF0P - 1 PPS sync source */ reg =3D <0>; - connection-type =3D "ext"; - label =3D "Input 0"; - supported-frequencies-hz =3D /bits/ 64 <1 1000>; + connection-type =3D "gnss"; + label =3D "GNSS_1PPS_IN"; + supported-frequencies-hz =3D /bits/ 64 <1>; + }; + + pin@1 { /* REF0N - clock source */ + reg =3D <1>; + connection-type =3D "gnss"; + label =3D "GNSS_10M_IN"; + supported-frequencies-hz =3D /bits/ 64 <10000000>; + ref-sync-sources =3D <&sync1>; }; }; =20 --=20 2.52.0 From nobody Thu Apr 2 14:14:44 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A2B836308A for ; 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Sat, 28 Mar 2026 04:06:54 -0400 X-MC-Unique: Pjo3sygoMOiWWMD2idCeAA-1 X-Mimecast-MFC-AGG-ID: Pjo3sygoMOiWWMD2idCeAA_1774685212 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 313081800345; Sat, 28 Mar 2026 08:06:52 +0000 (UTC) Received: from p16v.redhat.com (unknown [10.44.32.48]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 6199C1800351; Sat, 28 Mar 2026 08:06:48 +0000 (UTC) From: Ivan Vecera To: netdev@vger.kernel.org Cc: Petr Oros , Prathosh Satish , Arkadiusz Kubalewski , Jiri Pirko , Michal Schmidt , Simon Horman , Vadim Fedorenko , linux-kernel@vger.kernel.org, Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, Pasi Vaananen Subject: [PATCH net-next v2 5/5] dpll: zl3073x: add ref-sync pair support Date: Sat, 28 Mar 2026 09:06:24 +0100 Message-ID: <20260328080624.593916-6-ivecera@redhat.com> In-Reply-To: <20260328080624.593916-1-ivecera@redhat.com> References: <20260328080624.593916-1-ivecera@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Add support for ref-sync pair registration using the 'ref-sync-sources' phandle property from device tree. A ref-sync pair consists of a clock reference and a low-frequency sync signal where the DPLL locks to the clock reference but phase-aligns to the sync reference. The implementation: - Stores fwnode handle in zl3073x_dpll_pin during pin registration - Adds ref_sync_get/set callbacks to read and write the sync control mode and pair registers - Validates ref-sync frequency constraints: sync signal must be 8 kHz or less, clock reference must be 1 kHz or more and higher than sync - Excludes sync source from automatic reference selection by setting its priority to NONE on connect; on disconnect the priority is left as NONE and the user must explicitly make the pin selectable again - Iterates ref-sync-sources phandles to register declared pairings via dpll_pin_ref_sync_pair_add() Reviewed-by: Petr Oros Reviewed-by: Prathosh Satish Signed-off-by: Ivan Vecera --- drivers/dpll/zl3073x/dpll.c | 207 +++++++++++++++++++++++++++++++++++- 1 file changed, 206 insertions(+), 1 deletion(-) diff --git a/drivers/dpll/zl3073x/dpll.c b/drivers/dpll/zl3073x/dpll.c index b5b411425f6b3..79589400f0cc2 100644 --- a/drivers/dpll/zl3073x/dpll.c +++ b/drivers/dpll/zl3073x/dpll.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -30,6 +31,7 @@ * @dpll: DPLL the pin is registered to * @dpll_pin: pointer to registered dpll_pin * @tracker: tracking object for the acquired reference + * @fwnode: firmware node handle * @label: package label * @dir: pin direction * @id: pin id @@ -45,6 +47,7 @@ struct zl3073x_dpll_pin { struct zl3073x_dpll *dpll; struct dpll_pin *dpll_pin; dpll_tracker tracker; + struct fwnode_handle *fwnode; char label[8]; enum dpll_pin_direction dir; u8 id; @@ -184,6 +187,109 @@ zl3073x_dpll_input_pin_esync_set(const struct dpll_pi= n *dpll_pin, return zl3073x_ref_state_set(zldev, ref_id, &ref); } =20 +static int +zl3073x_dpll_input_pin_ref_sync_get(const struct dpll_pin *dpll_pin, + void *pin_priv, + const struct dpll_pin *ref_sync_pin, + void *ref_sync_pin_priv, + enum dpll_pin_state *state, + struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll_pin *sync_pin =3D ref_sync_pin_priv; + struct zl3073x_dpll_pin *pin =3D pin_priv; + struct zl3073x_dpll *zldpll =3D pin->dpll; + struct zl3073x_dev *zldev =3D zldpll->dev; + const struct zl3073x_ref *ref; + u8 ref_id, mode, pair; + + ref_id =3D zl3073x_input_pin_ref_get(pin->id); + ref =3D zl3073x_ref_state_get(zldev, ref_id); + mode =3D zl3073x_ref_sync_mode_get(ref); + pair =3D zl3073x_ref_sync_pair_get(ref); + + if (mode =3D=3D ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR && + pair =3D=3D zl3073x_input_pin_ref_get(sync_pin->id)) + *state =3D DPLL_PIN_STATE_CONNECTED; + else + *state =3D DPLL_PIN_STATE_DISCONNECTED; + + return 0; +} + +static int +zl3073x_dpll_input_pin_ref_sync_set(const struct dpll_pin *dpll_pin, + void *pin_priv, + const struct dpll_pin *ref_sync_pin, + void *ref_sync_pin_priv, + const enum dpll_pin_state state, + struct netlink_ext_ack *extack) +{ + struct zl3073x_dpll_pin *sync_pin =3D ref_sync_pin_priv; + struct zl3073x_dpll_pin *pin =3D pin_priv; + struct zl3073x_dpll *zldpll =3D pin->dpll; + struct zl3073x_dev *zldev =3D zldpll->dev; + u8 mode, ref_id, sync_ref_id; + struct zl3073x_chan chan; + struct zl3073x_ref ref; + int rc; + + ref_id =3D zl3073x_input_pin_ref_get(pin->id); + sync_ref_id =3D zl3073x_input_pin_ref_get(sync_pin->id); + ref =3D *zl3073x_ref_state_get(zldev, ref_id); + + if (state =3D=3D DPLL_PIN_STATE_CONNECTED) { + const struct zl3073x_ref *sync_ref; + u32 ref_freq, sync_freq; + + sync_ref =3D zl3073x_ref_state_get(zldev, sync_ref_id); + ref_freq =3D zl3073x_ref_freq_get(&ref); + sync_freq =3D zl3073x_ref_freq_get(sync_ref); + + /* Sync signal must be 8 kHz or less and clock reference + * must be 1 kHz or more and higher than the sync signal. + */ + if (sync_freq > 8000) { + NL_SET_ERR_MSG(extack, + "sync frequency must be 8 kHz or less"); + return -EINVAL; + } + if (ref_freq < 1000) { + NL_SET_ERR_MSG(extack, + "clock frequency must be 1 kHz or more"); + return -EINVAL; + } + if (ref_freq <=3D sync_freq) { + NL_SET_ERR_MSG(extack, + "clock frequency must be higher than sync frequency"); + return -EINVAL; + } + + zl3073x_ref_sync_pair_set(&ref, sync_ref_id); + mode =3D ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR; + } else { + mode =3D ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; + } + + zl3073x_ref_sync_mode_set(&ref, mode); + + rc =3D zl3073x_ref_state_set(zldev, ref_id, &ref); + if (rc) + return rc; + + /* Exclude sync source from automatic reference selection by setting + * its priority to NONE. On disconnect the priority is left as NONE + * and the user must explicitly make the pin selectable again. + */ + if (state =3D=3D DPLL_PIN_STATE_CONNECTED) { + chan =3D *zl3073x_chan_state_get(zldev, zldpll->id); + zl3073x_chan_ref_prio_set(&chan, sync_ref_id, + ZL_DPLL_REF_PRIO_NONE); + return zl3073x_chan_state_set(zldev, zldpll->id, &chan); + } + + return 0; +} + static int zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_= priv, const struct dpll_device *dpll, void *dpll_priv, @@ -1100,6 +1206,8 @@ static const struct dpll_pin_ops zl3073x_dpll_input_p= in_ops =3D { .phase_adjust_set =3D zl3073x_dpll_input_pin_phase_adjust_set, .prio_get =3D zl3073x_dpll_input_pin_prio_get, .prio_set =3D zl3073x_dpll_input_pin_prio_set, + .ref_sync_get =3D zl3073x_dpll_input_pin_ref_sync_get, + .ref_sync_set =3D zl3073x_dpll_input_pin_ref_sync_set, .state_on_dpll_get =3D zl3073x_dpll_input_pin_state_on_dpll_get, .state_on_dpll_set =3D zl3073x_dpll_input_pin_state_on_dpll_set, }; @@ -1190,8 +1298,11 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *p= in, u32 index) if (IS_ERR(props)) return PTR_ERR(props); =20 - /* Save package label, esync capability and phase adjust granularity */ + /* Save package label, fwnode, esync capability and phase adjust + * granularity. + */ strscpy(pin->label, props->package_label); + pin->fwnode =3D fwnode_handle_get(props->fwnode); pin->esync_control =3D props->esync_control; pin->phase_gran =3D props->dpll_props.phase_gran; =20 @@ -1236,6 +1347,8 @@ zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pi= n, u32 index) dpll_pin_put(pin->dpll_pin, &pin->tracker); pin->dpll_pin =3D NULL; err_pin_get: + fwnode_handle_put(pin->fwnode); + pin->fwnode =3D NULL; zl3073x_pin_props_put(props); =20 return rc; @@ -1265,6 +1378,9 @@ zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *= pin) =20 dpll_pin_put(pin->dpll_pin, &pin->tracker); pin->dpll_pin =3D NULL; + + fwnode_handle_put(pin->fwnode); + pin->fwnode =3D NULL; } =20 /** @@ -1735,6 +1851,88 @@ zl3073x_dpll_free(struct zl3073x_dpll *zldpll) kfree(zldpll); } =20 +/** + * zl3073x_dpll_ref_sync_pair_register - register ref_sync pairs for a pin + * @pin: pointer to zl3073x_dpll_pin structure + * + * Iterates 'ref-sync-sources' phandles in the pin's firmware node and + * registers each declared pairing. + * + * Return: 0 on success, <0 on error + */ +static int +zl3073x_dpll_ref_sync_pair_register(struct zl3073x_dpll_pin *pin) +{ + struct zl3073x_dev *zldev =3D pin->dpll->dev; + struct fwnode_handle *fwnode; + struct dpll_pin *sync_pin; + dpll_tracker tracker; + int n, rc; + + for (n =3D 0; ; n++) { + /* Get n'th ref-sync source */ + fwnode =3D fwnode_find_reference(pin->fwnode, "ref-sync-sources", + n); + if (IS_ERR(fwnode)) { + rc =3D PTR_ERR(fwnode); + break; + } + + /* Find associated dpll pin */ + sync_pin =3D fwnode_dpll_pin_find(fwnode, &tracker); + fwnode_handle_put(fwnode); + if (!sync_pin) { + dev_warn(zldev->dev, "%s: ref-sync source %d not found", + pin->label, n); + continue; + } + + /* Register new ref-sync pair */ + rc =3D dpll_pin_ref_sync_pair_add(pin->dpll_pin, sync_pin); + dpll_pin_put(sync_pin, &tracker); + + /* -EBUSY means pairing already exists from another DPLL's + * registration. + */ + if (rc && rc !=3D -EBUSY) { + dev_err(zldev->dev, + "%s: failed to add ref-sync source %d: %pe", + pin->label, n, ERR_PTR(rc)); + break; + } + } + + return rc !=3D -ENOENT ? rc : 0; +} + +/** + * zl3073x_dpll_ref_sync_pairs_register - register ref_sync pairs for a DP= LL + * @zldpll: pointer to zl3073x_dpll structure + * + * Iterates all registered input pins of the given DPLL and establishes + * ref_sync pairings declared by 'ref-sync-sources' phandles in the + * device tree. + * + * Return: 0 on success, <0 on error + */ +static int +zl3073x_dpll_ref_sync_pairs_register(struct zl3073x_dpll *zldpll) +{ + struct zl3073x_dpll_pin *pin; + int rc; + + list_for_each_entry(pin, &zldpll->pins, list) { + if (!zl3073x_dpll_is_input_pin(pin) || !pin->fwnode) + continue; + + rc =3D zl3073x_dpll_ref_sync_pair_register(pin); + if (rc) + return rc; + } + + return 0; +} + /** * zl3073x_dpll_register - register DPLL device and all its pins * @zldpll: pointer to zl3073x_dpll structure @@ -1758,6 +1956,13 @@ zl3073x_dpll_register(struct zl3073x_dpll *zldpll) return rc; } =20 + rc =3D zl3073x_dpll_ref_sync_pairs_register(zldpll); + if (rc) { + zl3073x_dpll_pins_unregister(zldpll); + zl3073x_dpll_device_unregister(zldpll); + return rc; + } + return 0; } =20 --=20 2.52.0