From nobody Thu Apr 2 14:14:19 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9C2F37104E; Sat, 28 Mar 2026 22:58:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774738724; cv=none; b=NrmDztg10oCQdWjXyvxgHf+X0X55dyknonhIQs4ym/HBEn/tboKGQ7sulxyyAKwaoV585PH2X944Z2Zs3Ad6gB1SIntXshHroU4sRIi9j3AC3rsBABsaJc07oMQKxdbdYsmJZZqP1bnG2YFLa+xG8XRmPqN7PZh7uS++p7EzBCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774738724; c=relaxed/simple; bh=c7q27+5pV6seCz6fw/OaZXueVh85YipuI8NB3yehnEg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tUVGPzl9b9teYTQSMdqAwilfzRHBxIj0MSo9PIRIg7OY7v1IJGNAWOmokq5gjfD6Rgq9N7kAbRGCj4gLXvg7WdalF7WhkQgK8TCtpG6zKt3X0VVTBF8CyfBEzltktXKiWrK+a3cgb3pBNcGuE3kt17yVzEYwjmupFgkcgNYYDl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VFOoA2UY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VFOoA2UY" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5329CC2BC9E; Sat, 28 Mar 2026 22:58:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774738724; bh=c7q27+5pV6seCz6fw/OaZXueVh85YipuI8NB3yehnEg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=VFOoA2UYm4gECQ78kENXLvz9oOlmM7pZufizmQYvNza2qDoedQ3HMEUdnwsFxqo1D M7yGZNWx381cYZ57fOUKkltGo+Bz4FOS4w3z5PAlKbQpbJw+ZU3W6qgYOjjf8upbNL Z17a4k1uwwZrGvqY57JlAaWKBNDAdX50X8cC9D/VyuB8P6Iu5f3kB9ARkpn78zlM2Z z5s9HHm9fyxIW44JKYVRTrvAjJOsrPCWCGm9AZVxXgJVVPhIoU+mxIxgsznKRlwfhL VAEyoUfuSnHe4Lk1w0KCcaxK4eJVCp3h8otHK/TCbNNYup6erthWFWwyTFuxJOttf/ EjOj9G132DWUQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41AAE10D148A; Sat, 28 Mar 2026 22:58:44 +0000 (UTC) From: =?utf-8?q?Pablo_Correa_G=C3=B3mez_via_B4_Relay?= Date: Sat, 28 Mar 2026 23:58:40 +0100 Subject: [PATCH v2 1/3] arm64: dts: qcom: sdm670: add default uart pinctrl nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260328-pabloyoyoista-debug-uart-on-rdacayan-next-v2-1-53abd9db8f0a@postmarketos.org> References: <20260328-pabloyoyoista-debug-uart-on-rdacayan-next-v2-0-53abd9db8f0a@postmarketos.org> In-Reply-To: <20260328-pabloyoyoista-debug-uart-on-rdacayan-next-v2-0-53abd9db8f0a@postmarketos.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Richard Acayan , ~postmarketos/upstreaming@lists.sr.ht, =?utf-8?q?Pablo_Correa_G=C3=B3mez?= X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=4680; i=pabloyoyoista@postmarketos.org; h=from:subject:message-id; bh=BuzAL9B0hzH8sHOEbYMQsrlBM+zPhBYp09xz2YwAGlk=; b=owEBbQKS/ZANAwAKAXo0JWX/Y195AcsmYgBpyF0i3yr0N6jl6v9p1QPksvTA/RkAzSaABc3un ClG0jVJfUiJAjMEAAEKAB0WIQS9CheUSi6o/ykTCaJ6NCVl/2NfeQUCachdIgAKCRB6NCVl/2Nf eaNPEACVn4qDfezmZfOt2Qpaa8fgkxBV0/vvAJZVfkt1LQOQQP8fTJqOgwv6Do7LjJl5gV3kJcT /8XbUofOrYtlp/YgHwJEv2pSdxokaYK6lDeyuDauXhaqxo+z37d16Pk6trdnzwX8QsQWi/h6pRD cxIUTO5zTe1036o736kb8w+7D7bNo2Wp94ZNaUrSRBD61j/38phgDzA38NXhXxfACuE+t6YdD1H Ya6hh6As9jv3mELpxBD+LxAi7LaMl6q14aVERbVs3o7NT7fbtkZ4t4+QGFR86btG8QGUl9YwBDL dkle8b662I/NUNHNMr1biD8gPWNYu7LsBcZvr1iVfXZQk5HugAGjPYrtSNkWJoyGA/Phx5yZscQ EuEPQ2BL1qbID11VnjyXf5Fer4QIsexbSqBz6J8uc/a4hqcr/nPzQnp9GQilA9iTkHEhoAnecmv ogeRz3vlorbuT2ahNkhIXqHBfTHI+0BuJAxfESyhJtdEbYYvP6oBmlwuY4L5z5HrtZbz1j6Ke9D LzW+rPhBg7XhQN/X7EzbZq0YtFfkYwg0qCGOpmRg7ymkFdvLEaAHwxSbV/JfHKv8hIhytEzDymq cvL02qGm8XoBGIe89AveYQD6AvSphRLGeH8LUAocLwY3XpfvzrWN9jJb6R5MYCj/Bgnv3qn99DA q6/VVvv+wxw+Z5w== X-Developer-Key: i=pabloyoyoista@postmarketos.org; a=openpgp; fpr=BD0A17944A2EA8FF291309A27A342565FF635F79 X-Endpoint-Received: by B4 Relay for pabloyoyoista@postmarketos.org/default with auth_id=698 X-Original-From: =?utf-8?q?Pablo_Correa_G=C3=B3mez?= Reply-To: pabloyoyoista@postmarketos.org From: Pablo Correa G=C3=B3mez This is a pre-requisite to enable UART in sargo and bonito. Values for the pins have been taken from sdm845, and cross-checking dowstream, where available. Signed-off-by: Pablo Correa G=C3=B3mez --- arch/arm64/boot/dts/qcom/sdm670.dtsi | 192 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 192 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qco= m/sdm670.dtsi index 6b296ceaebc2..3e60ab527a42 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -1352,6 +1352,198 @@ qup_i2c15_default: qup-i2c15-default-state { function =3D "qup15"; }; =20 + qup_uart0_default: qup-uart0-default-state { + qup_uart0_tx: tx-pins { + pins =3D "gpio2"; + function =3D "qup0"; + }; + + qup_uart0_rx: rx-pins { + pins =3D "gpio3"; + function =3D "qup0"; + }; + }; + + qup_uart1_default: qup-uart1-default-state { + qup_uart1_tx: tx-pins { + pins =3D "gpio19"; + function =3D "qup1"; + }; + + qup_uart1_rx: rx-pins { + pins =3D "gpio20"; + function =3D "qup1"; + }; + }; + + qup_uart2_default: qup-uart2-default-state { + qup_uart2_tx: tx-pins { + pins =3D "gpio29"; + function =3D "qup2"; + }; + + qup_uart2_rx: rx-pins { + pins =3D "gpio30"; + function =3D "qup2"; + }; + }; + + qup_uart3_default: qup-uart3-default-state { + qup_uart3_tx: tx-pins { + pins =3D "gpio43"; + function =3D "qup3"; + }; + + qup_uart3_rx: rx-pins { + pins =3D "gpio44"; + function =3D "qup3"; + }; + }; + + qup_uart4_default: qup-uart4-default-state { + qup_uart4_tx: tx-pins { + pins =3D "gpio91"; + function =3D "qup4"; + }; + + qup_uart4_rx: rx-pins { + pins =3D "gpio92"; + function =3D "qup4"; + }; + }; + + qup_uart5_default: qup-uart5-default-state { + qup_uart5_tx: tx-pins { + pins =3D "gpio87"; + function =3D "qup5"; + }; + + qup_uart5_rx: rx-pins { + pins =3D "gpio88"; + function =3D "qup5"; + }; + }; + + qup_uart6_default: qup-uart6-default-state { + qup_uart6_tx: tx-pins { + pins =3D "gpio47"; + function =3D "qup6"; + }; + + qup_uart6_rx: rx-pins { + pins =3D "gpio48"; + function =3D "qup6"; + }; + }; + + qup_uart7_default: qup-uart7-default-state { + qup_uart7_tx: tx-pins { + pins =3D "gpio95"; + function =3D "qup7"; + }; + + qup_uart7_rx: rx-pins { + pins =3D "gpio96"; + function =3D "qup7"; + }; + }; + + qup_uart8_default: qup-uart8-default-state { + qup_uart8_tx: tx-pins { + pins =3D "gpio67"; + function =3D "qup8"; + }; + + qup_uart8_rx: rx-pins { + pins =3D "gpio68"; + function =3D "qup8"; + }; + }; + + qup_uart9_default: qup-uart9-default-state { + qup_uart9_tx: tx-pins { + pins =3D "gpio4"; + function =3D "qup9"; + }; + + qup_uart9_rx: rx-pins { + pins =3D "gpio5"; + function =3D "qup9"; + }; + }; + + qup_uart10_default: qup-uart10-default-state { + qup_uart10_tx: tx-pins { + pins =3D "gpio53"; + function =3D "qup10"; + }; + + qup_uart10_rx: rx-pins { + pins =3D "gpio54"; + function =3D "qup10"; + }; + }; + + qup_uart11_default: qup-uart11-default-state { + qup_uart11_tx: tx-pins { + pins =3D "gpio33"; + function =3D "qup11"; + }; + + qup_uart11_rx: rx-pins { + pins =3D "gpio34"; + function =3D "qup11"; + }; + }; + + qup_uart12_default: qup-uart12-default-state { + qup_uart12_tx: tx-pins { + pins =3D "gpio51"; + function =3D "qup12"; + }; + + qup_uart12_rx: rx-pins { + pins =3D "gpio52"; + function =3D "qup12"; + }; + }; + + qup_uart13_default: qup-uart13-default-state { + qup_uart13_tx: tx-pins { + pins =3D "gpio107"; + function =3D "qup13"; + }; + + qup_uart13_rx: rx-pins { + pins =3D "gpio108"; + function =3D "qup13"; + }; + }; + + qup_uart14_default: qup-uart14-default-state { + qup_uart14_tx: tx-pins { + pins =3D "gpio31"; + function =3D "qup14"; + }; + + qup_uart14_rx: rx-pins { + pins =3D "gpio32"; + function =3D "qup14"; + }; + }; + + qup_uart15_default: qup-uart15-default-state { + qup_uart15_tx: tx-pins { + pins =3D "gpio83"; + function =3D "qup15"; + }; + + qup_uart15_rx: rx-pins { + pins =3D "gpio84"; + function =3D "qup15"; + }; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins =3D "sdc1_clk"; --=20 2.53.0