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Signed-off-by: Umang Chheda --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index ca880c105f3b..07053cc2ac1c 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -918,6 +918,7 @@ properties: - enum: - arduino,monza - qcom,monaco-evk + - qcom,monaco-evk-ac-sku - qcom,qcs8300-ride - const: qcom,qcs8300 =20 --=20 2.34.1 From nobody Thu Apr 2 14:09:56 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 159C8337BB0 for ; Sat, 28 Mar 2026 11:41:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Sat, 28 Mar 2026 04:41:47 -0700 (PDT) X-Received: by 2002:a05:6a21:4d8f:b0:38b:d93f:bbf5 with SMTP id adf61e73a8af0-39c8715bdd2mr3438645637.0.1774698106751; Sat, 28 Mar 2026 04:41:46 -0700 (PDT) Received: from hu-uchheda-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c76917db535sm1681238a12.30.2026.03.28.04.41.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Mar 2026 04:41:46 -0700 (PDT) From: Umang Chheda Date: Sat, 28 Mar 2026 17:11:18 +0530 Subject: [PATCH 2/2] arm64: dts: qcom: qcs8300: Add monaco-ac-sku EVK board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260328-monaco-evk-ac-sku-v1-2-79d166fa5571@oss.qualcomm.com> References: <20260328-monaco-evk-ac-sku-v1-0-79d166fa5571@oss.qualcomm.com> In-Reply-To: <20260328-monaco-evk-ac-sku-v1-0-79d166fa5571@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Umang Chheda , Faruque Ansari X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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Compared to "monaco-evk" variant, which utilizes higher tier QCS8300-AA SKU (supporting 40 TOPS of NPU) and a 4-PMIC (2x PM8650AU + Maxim MAX20018 + TI TPS6594) power delivery network (PDN) to support higher power requirement. This board utilizes lower tier QCS8300-AC SKU (Supporting 20 TOPS of NPU) and a simplified 2 PMIC(2x PM8650AU) PDN. Add support for the following components : - GPI (Generic Peripheral Interface) and QUPv3-0/1 controllers to facilitate DMA and peripheral communication. - TCA9534 I/O expander via I2C to provide 8 additional GPIO lines for extended I/O functionality. - USB1 controller routed to a TypeC connector in device mode to support USB peripheral operations. - Remoteproc subsystems for supported DSPs such as Audio DSP, Compute DSP and Generic DSP, along with their corresponding firmware. - Configure nvmem-layout on the I2C EEPROM to store data for Ethernet and other consumers. - QCA8081 2.5G Ethernet PHY on port-0 and expose the Ethernet MAC address via nvmem for network configuration. It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY. - Support for the Iris video decoder, including the required firmware, to enable video decoding capabilities. - PCIe0 and PCIe1 controller and phy-nodes. - Sound card and max98357a based I2S speaker amplifier. Written with inputs from: Nirmesh Kumar Singh - GPIO Expander. Viken Dadhaniya - GPI/QUP. Mohd Ayaan Anwar - Ethernet. Monish Chunara - EEPROM. Swati Agarwal - USB. Sushrut Shree Trivedi - PCIe. Mohammad Rafi Shaik - Audio. Co-developed-by: Faruque Ansari Signed-off-by: Faruque Ansari Signed-off-by: Umang Chheda --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/monaco-evk-ac-sku.dts | 730 +++++++++++++++++++++= ++++ 2 files changed, 731 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index c46d94bb6dd5..1d8c2a3db6c0 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -57,6 +57,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-arduino-monza.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-ac-sku.dtb =20 monaco-evk-camera-imx577-dtbs :=3D monaco-evk.dtb monaco-evk-camera-imx577= .dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D monaco-evk-camera-imx577.dtb diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-ac-sku.dts b/arch/arm64/bo= ot/dts/qcom/monaco-evk-ac-sku.dts new file mode 100644 index 000000000000..c100ed9f7981 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/monaco-evk-ac-sku.dts @@ -0,0 +1,730 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "monaco.dtsi" +#include "monaco-pmics.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Monaco-ac-sku EVK"; + compatible =3D "qcom,monaco-evk-ac-sku", "qcom,qcs8300"; + + aliases { + ethernet0 =3D ðernet0; + i2c1 =3D &i2c1; + serial0 =3D &uart7; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + dmic: audio-codec-0 { + compatible =3D "dmic-codec"; + #sound-dai-cells =3D <0>; + num-channels =3D <1>; + }; + + max98357a: audio-codec-1 { + compatible =3D "maxim,max98357a"; + #sound-dai-cells =3D <0>; + }; + + sound { + compatible =3D "qcom,qcs8275-sndcard"; + model =3D "MONACO-EVK"; + + pinctrl-0 =3D <&hs0_mi2s_active>, <&mi2s1_active>; + pinctrl-names =3D "default"; + + hs0-mi2s-playback-dai-link { + link-name =3D "HS0 MI2S Playback"; + + codec { + sound-dai =3D <&max98357a>; + }; + + cpu { + sound-dai =3D <&q6apmbedai PRIMARY_MI2S_RX>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name =3D "Secondary MI2S Capture"; + + codec { + sound-dai =3D <&dmic>; + }; + + cpu { + sound-dai =3D <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "a"; + + vreg_l3a: ldo3 { + regulator-name =3D "vreg_l3a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4a: ldo4 { + regulator-name =3D "vreg_l4a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l5a: ldo5 { + regulator-name =3D "vreg_l5a"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6a: ldo6 { + regulator-name =3D "vreg_l6a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7a: ldo7 { + regulator-name =3D "vreg_l7a"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8a: ldo8 { + regulator-name =3D "vreg_l8a"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9a: ldo9 { + regulator-name =3D "vreg_l9a"; + regulator-min-microvolt =3D <2970000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s4a: smps4 { + regulator-name =3D "vreg_s4a"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_s9a: smps9 { + regulator-name =3D "vreg_s9a"; + regulator-min-microvolt =3D <1352000>; + regulator-max-microvolt =3D <1352000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pmm8654au-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vreg_l1c: ldo1 { + regulator-name =3D "vreg_l1c"; + regulator-min-microvolt =3D <300000>; + regulator-max-microvolt =3D <500000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <904000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l4c: ldo4 { + regulator-name =3D "vreg_l4c"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l6c: ldo6 { + regulator-name =3D "vreg_l6c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l7c: ldo7 { + regulator-name =3D "vreg_l7c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l8c: ldo8 { + regulator-name =3D "vreg_l8c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_l9c: ldo9 { + regulator-name =3D "vreg_l9c"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + regulator-allow-set-load; + regulator-allowed-modes =3D ; + }; + + vreg_s5c: smps5 { + regulator-name =3D "vreg_s5c"; + regulator-min-microvolt =3D <1104000>; + regulator-max-microvolt =3D <1104000>; + regulator-initial-mode =3D ; + }; + }; +}; + +ðernet0 { + phy-mode =3D "2500base-x"; + phy-handle =3D <&hsgmii_phy0>; + + pinctrl-0 =3D <ðernet0_default>; + pinctrl-names =3D "default"; + + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + nvmem-cells =3D <&mac_addr0>; + nvmem-cell-names =3D "mac-address"; + + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hsgmii_phy0: ethernet-phy@1c { + compatible =3D "ethernet-phy-id004d.d101"; + reg =3D <0x1c>; + reset-gpios =3D <&tlmm 31 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <11000>; + reset-deassert-us =3D <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + snps,route-up; + snps,priority =3D <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel =3D <0x3>; + snps,priority =3D <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope =3D <0x1000>; + snps,idle_slope =3D <0x1000>; + snps,high_credit =3D <0x3e800>; + snps,low_credit =3D <0xffc18000>; + }; + }; +}; + +&gpi_dma0 { + status =3D "okay"; +}; + +&gpi_dma1 { + status =3D "okay"; +}; + +&i2c1 { + pinctrl-0 =3D <&qup_i2c1_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + fan_controller: fan@18 { + compatible =3D "ti,amc6821"; + reg =3D <0x18>; + #pwm-cells =3D <2>; + + fan { + pwms =3D <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + eeprom0: eeprom@50 { + compatible =3D "atmel,24c256"; + reg =3D <0x50>; + pagesize =3D <64>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mac_addr0: mac-addr@0 { + reg =3D <0x0 0x6>; + }; + }; + }; +}; + +&i2c15 { + pinctrl-0 =3D <&qup_i2c15_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; + + expander0: gpio@38 { + compatible =3D "ti,tca9538"; + reg =3D <0x38>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 56 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander0_int>; + pinctrl-names =3D "default"; + }; + + expander1: gpio@39 { + compatible =3D "ti,tca9538"; + reg =3D <0x39>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 16 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander1_int>; + pinctrl-names =3D "default"; + }; + + expander2: gpio@3a { + compatible =3D "ti,tca9538"; + reg =3D <0x3a>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 95 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander2_int>; + pinctrl-names =3D "default"; + }; + + expander3: gpio@3b { + compatible =3D "ti,tca9538"; + reg =3D <0x3b>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 24 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander3_int>; + pinctrl-names =3D "default"; + }; + + expander4: gpio@3c { + compatible =3D "ti,tca9538"; + reg =3D <0x3c>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 96 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander4_int>; + pinctrl-names =3D "default"; + }; + + expander5: gpio@3d { + compatible =3D "ti,tca9538"; + reg =3D <0x3d>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander5_int>; + pinctrl-names =3D "default"; + }; + + expander6: gpio@3e { + compatible =3D "ti,tca9538"; + reg =3D <0x3e>; + #gpio-cells =3D <2>; + gpio-controller; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&tlmm 52 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 =3D <&expander6_int>; + pinctrl-names =3D "default"; + }; +}; + +&iris { + status =3D "okay"; +}; + +&pcie0 { + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie0_phy { + vdda-phy-supply =3D <&vreg_l6a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&pcie1 { + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + vdda-phy-supply =3D <&vreg_l6a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&pcieport0 { + reset-gpios =3D <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcieport1 { + reset-gpios =3D <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 21 GPIO_ACTIVE_HIGH>; +}; + +&qupv3_id_0 { + firmware-name =3D "qcom/qcs8300/qupv3fw.elf"; + + status =3D "okay"; +}; + +&qupv3_id_1 { + firmware-name =3D "qcom/qcs8300/qupv3fw.elf"; + + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/qcs8300/adsp.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/qcs8300/cdsp0.mbn"; + + status =3D "okay"; +}; + +&remoteproc_gpdsp { + firmware-name =3D "qcom/qcs8300/gpdsp0.mbn"; + + status =3D "okay"; +}; + +&serdes0 { + phy-supply =3D <&vreg_l4a>; + + status =3D "okay"; +}; + +&spi10 { + status =3D "okay"; + + tpm@0 { + compatible =3D "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg =3D <0>; + spi-max-frequency =3D <20000000>; + }; +}; + +&tlmm { + + pcie0_default_state: pcie0-default-state { + wake-pins { + pins =3D "gpio0"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio1"; + function =3D "pcie0_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio2"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + expander5_int: expander5-int-state { + pins =3D "gpio3"; + function =3D "gpio"; + bias-pull-up; + }; + + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins =3D "gpio5"; + function =3D "emac0_mdc"; + drive-strength =3D <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins =3D "gpio6"; + function =3D "emac0_mdio"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + + expander1_int: expander1-int-state { + pins =3D "gpio16"; + function =3D "gpio"; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-state { + pins =3D "gpio19", "gpio20"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-state { + pins =3D "gpio19", "gpio20"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pcie1_default_state: pcie1-default-state { + wake-pins { + pins =3D "gpio21"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + clkreq-pins { + pins =3D "gpio22"; + function =3D "pcie1_clkreq"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-pins { + pins =3D "gpio23"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + expander3_int: expander3-int-state { + pins =3D "gpio24"; + function =3D "gpio"; + bias-pull-up; + }; + + expander6_int: expander6-int-state { + pins =3D "gpio52"; + function =3D "gpio"; + bias-pull-up; + }; + + expander0_int: expander0-int-state { + pins =3D "gpio56"; + function =3D "gpio"; + bias-pull-up; + }; + + qup_i2c15_default: qup-i2c15-state { + pins =3D "gpio91", "gpio92"; + function =3D "qup1_se7"; + drive-strength =3D <2>; + bias-pull-up; + }; + + expander2_int: expander2-int-state { + pins =3D "gpio95"; + function =3D "gpio"; + bias-pull-up; + }; + + expander4_int: expander4-int-state { + pins =3D "gpio96"; + function =3D "gpio"; + bias-pull-up; + }; +}; + +&uart7 { + status =3D "okay"; +}; + +&ufs_mem_hc { + reset-gpios =3D <&tlmm 133 GPIO_ACTIVE_LOW>; + vcc-supply =3D <&vreg_l8a>; + vcc-max-microamp =3D <1100000>; + vccq-supply =3D <&vreg_l4c>; + vccq-max-microamp =3D <1200000>; + + status =3D "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply =3D <&vreg_l4a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; + +&usb_1 { + dr_mode =3D "peripheral"; + + status =3D "okay"; +}; + +&usb_1_hsphy { + vdda-pll-supply =3D <&vreg_l7a>; + vdda18-supply =3D <&vreg_l7c>; + vdda33-supply =3D <&vreg_l9a>; + + status =3D "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply =3D <&vreg_l7a>; + vdda-pll-supply =3D <&vreg_l5a>; + + status =3D "okay"; +}; --=20 2.34.1