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For example, SM8450 uses Gen2 firmware, so currently its platform data should be placed next to the other gen2 platforms, although it has the VPU2.0 core, similar to the one found on SM8250 and SC7280 and so the hardware-specific platform data is also close to those devices. Split firmware data to a separate struct, separating hardware-related data from the firmware interfaces. Reviewed-by: Dikshita Agarwal Signed-off-by: Dmitry Baryshkov --- drivers/media/platform/qcom/iris/iris_buffer.c | 82 +++---- drivers/media/platform/qcom/iris/iris_core.h | 2 + drivers/media/platform/qcom/iris/iris_ctrls.c | 8 +- .../platform/qcom/iris/iris_hfi_gen1_command.c | 8 +- .../platform/qcom/iris/iris_hfi_gen2_command.c | 66 +++--- .../platform/qcom/iris/iris_platform_common.h | 81 ++++--- .../media/platform/qcom/iris/iris_platform_gen1.c | 67 +++--- .../media/platform/qcom/iris/iris_platform_gen2.c | 248 ++++-------------= ---- drivers/media/platform/qcom/iris/iris_probe.c | 3 +- drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- drivers/media/platform/qcom/iris/iris_vpu_common.c | 2 +- 11 files changed, 206 insertions(+), 371 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index f55b7c608116..fbe136360aa1 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -301,31 +301,31 @@ static void iris_fill_internal_buf_info(struct iris_i= nst *inst, =20 void iris_get_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; for (i =3D 0; i < internal_buffer_count; i++) iris_fill_internal_buf_info(inst, internal_buf_type[i]); } @@ -366,7 +366,7 @@ static int iris_create_internal_buffer(struct iris_inst= *inst, =20 int iris_create_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; u32 internal_buffer_count, i, j; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -374,19 +374,19 @@ int iris_create_internal_buffers(struct iris_inst *in= st, u32 plane) =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -442,7 +442,7 @@ int iris_queue_internal_deferred_buffers(struct iris_in= st *inst, enum iris_buffe =20 int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buffer, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -451,19 +451,19 @@ int iris_queue_internal_buffers(struct iris_inst *ins= t, u32 plane) =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -501,7 +501,7 @@ int iris_destroy_internal_buffer(struct iris_inst *inst= , struct iris_buffer *buf =20 static int iris_destroy_internal_buffers(struct iris_inst *inst, u32 plane= , bool force) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -510,19 +510,19 @@ static int iris_destroy_internal_buffers(struct iris_= inst *inst, u32 plane, bool =20 if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - len =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + len =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - len =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + len =3D firmware_data->dec_op_int_buf_tbl_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - len =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + len =3D firmware_data->enc_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_op_int_buf_tbl; - len =3D platform_data->enc_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_op_int_buf_tbl; + len =3D firmware_data->enc_op_int_buf_tbl_size; } } =20 @@ -593,17 +593,17 @@ static int iris_release_internal_buffers(struct iris_= inst *inst, =20 static int iris_release_input_internal_buffers(struct iris_inst *inst) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; const u32 *internal_buf_type; u32 internal_buffer_count, i; int ret; =20 if (inst->domain =3D=3D DECODER) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->enc_ip_int_buf_tbl_size; } =20 for (i =3D 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 1592681640ab..e0ca245c8c63 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -54,6 +54,7 @@ struct qcom_ubwc_cfg_data; * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data + * @iris_firmware_data: a pointer to the firmware (or HFI) specific data * @ubwc_cfg: UBWC configuration for the platform * @state: current state of core * @iface_q_table_daddr: device address for interface queue table memory @@ -97,6 +98,7 @@ struct iris_core { struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; + const struct iris_firmware_data *iris_firmware_data; const struct qcom_ubwc_cfg_data *ubwc_cfg; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 5a24aa869b2d..ef7adac3764d 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -332,8 +332,8 @@ void iris_session_init_caps(struct iris_core *core) const struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; =20 - caps =3D core->iris_platform_data->inst_fw_caps_dec; - num_cap =3D core->iris_platform_data->inst_fw_caps_dec_size; + caps =3D core->iris_firmware_data->inst_fw_caps_dec; + num_cap =3D core->iris_firmware_data->inst_fw_caps_dec_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; @@ -360,8 +360,8 @@ void iris_session_init_caps(struct iris_core *core) } } =20 - caps =3D core->iris_platform_data->inst_fw_caps_enc; - num_cap =3D core->iris_platform_data->inst_fw_caps_enc_size; + caps =3D core->iris_firmware_data->inst_fw_caps_enc; + num_cap =3D core->iris_firmware_data->inst_fw_caps_enc_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 0017ade4adbd..3fb90a466a64 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -1033,8 +1033,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p }; =20 if (inst->domain =3D=3D DECODER) { - config_params =3D core->iris_platform_data->dec_input_config_params_defa= ult; - config_params_size =3D core->iris_platform_data->dec_input_config_params= _default_size; + config_params =3D core->iris_firmware_data->dec_input_config_params_defa= ult; + config_params_size =3D core->iris_firmware_data->dec_input_config_params= _default_size; if (V4L2_TYPE_IS_OUTPUT(plane)) { handler =3D vdec_prop_type_handle_inp_arr; handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_inp_arr); @@ -1043,8 +1043,8 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_out_arr); } } else { - config_params =3D core->iris_platform_data->enc_input_config_params; - config_params_size =3D core->iris_platform_data->enc_input_config_params= _size; + config_params =3D core->iris_firmware_data->enc_input_config_params; + config_params_size =3D core->iris_firmware_data->enc_input_config_params= _size; handler =3D venc_prop_type_handle_inp_arr; handler_size =3D ARRAY_SIZE(venc_prop_type_handle_inp_arr); } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 639b75fca1ab..c90b22a75bc5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -601,7 +601,7 @@ static int iris_hfi_gen2_set_super_block(struct iris_in= st *inst, u32 plane) =20 static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { - const struct iris_platform_data *pdata =3D inst->core->iris_platform_data; + const struct iris_firmware_data *fdata =3D inst->core->iris_firmware_data; u32 config_params_size =3D 0, i, j; const u32 *config_params =3D NULL; int ret; @@ -630,31 +630,31 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p if (inst->domain =3D=3D DECODER) { if (V4L2_TYPE_IS_OUTPUT(plane)) { if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { - config_params =3D pdata->dec_input_config_params_default; - config_params_size =3D pdata->dec_input_config_params_default_size; + config_params =3D fdata->dec_input_config_params_default; + config_params_size =3D fdata->dec_input_config_params_default_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { - config_params =3D pdata->dec_input_config_params_hevc; - config_params_size =3D pdata->dec_input_config_params_hevc_size; + config_params =3D fdata->dec_input_config_params_hevc; + config_params_size =3D fdata->dec_input_config_params_hevc_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) { - config_params =3D pdata->dec_input_config_params_vp9; - config_params_size =3D pdata->dec_input_config_params_vp9_size; + config_params =3D fdata->dec_input_config_params_vp9; + config_params_size =3D fdata->dec_input_config_params_vp9_size; } else if (inst->codec =3D=3D V4L2_PIX_FMT_AV1) { - config_params =3D pdata->dec_input_config_params_av1; - config_params_size =3D pdata->dec_input_config_params_av1_size; + config_params =3D fdata->dec_input_config_params_av1; + config_params_size =3D fdata->dec_input_config_params_av1_size; } else { return -EINVAL; } } else { - config_params =3D pdata->dec_output_config_params; - config_params_size =3D pdata->dec_output_config_params_size; + config_params =3D fdata->dec_output_config_params; + config_params_size =3D fdata->dec_output_config_params_size; } } else { if (V4L2_TYPE_IS_OUTPUT(plane)) { - config_params =3D pdata->enc_input_config_params; - config_params_size =3D pdata->enc_input_config_params_size; + config_params =3D fdata->enc_input_config_params; + config_params_size =3D fdata->enc_input_config_params_size; } else { - config_params =3D pdata->enc_output_config_params; - config_params_size =3D pdata->enc_output_config_params_size; + config_params =3D fdata->enc_output_config_params; + config_params_size =3D fdata->enc_output_config_params_size; } } =20 @@ -849,24 +849,24 @@ static int iris_hfi_gen2_subscribe_change_param(struc= t iris_inst *inst, u32 plan =20 switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param =3D core->iris_platform_data->dec_input_config_params_defau= lt; + change_param =3D core->iris_firmware_data->dec_input_config_params_defau= lt; change_param_size =3D - core->iris_platform_data->dec_input_config_params_default_size; + core->iris_firmware_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param =3D core->iris_platform_data->dec_input_config_params_hevc; + change_param =3D core->iris_firmware_data->dec_input_config_params_hevc; change_param_size =3D - core->iris_platform_data->dec_input_config_params_hevc_size; + core->iris_firmware_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param =3D core->iris_platform_data->dec_input_config_params_vp9; + change_param =3D core->iris_firmware_data->dec_input_config_params_vp9; change_param_size =3D - core->iris_platform_data->dec_input_config_params_vp9_size; + core->iris_firmware_data->dec_input_config_params_vp9_size; break; case V4L2_PIX_FMT_AV1: - change_param =3D core->iris_platform_data->dec_input_config_params_av1; + change_param =3D core->iris_firmware_data->dec_input_config_params_av1; change_param_size =3D - core->iris_platform_data->dec_input_config_params_av1_size; + core->iris_firmware_data->dec_input_config_params_av1_size; break; } =20 @@ -996,29 +996,29 @@ static int iris_hfi_gen2_subscribe_property(struct ir= is_inst *inst, u32 plane) return 0; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { - subscribe_prop_size =3D core->iris_platform_data->dec_input_prop_size; - subcribe_prop =3D core->iris_platform_data->dec_input_prop; + subscribe_prop_size =3D core->iris_firmware_data->dec_input_prop_size; + subcribe_prop =3D core->iris_firmware_data->dec_input_prop; } else { switch (inst->codec) { case V4L2_PIX_FMT_H264: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_avc; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_avc; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_avc_size; + core->iris_firmware_data->dec_output_prop_avc_size; break; case V4L2_PIX_FMT_HEVC: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_hevc; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_hevc; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_hevc_size; + core->iris_firmware_data->dec_output_prop_hevc_size; break; case V4L2_PIX_FMT_VP9: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_vp9; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_vp9; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_vp9_size; + core->iris_firmware_data->dec_output_prop_vp9_size; break; case V4L2_PIX_FMT_AV1: - subcribe_prop =3D core->iris_platform_data->dec_output_prop_av1; + subcribe_prop =3D core->iris_firmware_data->dec_output_prop_av1; subscribe_prop_size =3D - core->iris_platform_data->dec_output_prop_av1_size; + core->iris_firmware_data->dec_output_prop_av1_size; break; } } diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index e8a219023aaa..5af6d9f49f01 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -201,44 +201,16 @@ enum platform_pm_domain_type { IRIS_APV_HW_POWER_DOMAIN, }; =20 -struct iris_platform_data { +struct iris_firmware_data { void (*init_hfi_ops)(struct iris_core *core); - u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); - const struct vpu_ops *vpu_ops; - const struct icc_info *icc_tbl; - unsigned int icc_tbl_size; - const struct bw_info *bw_tbl_dec; - unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; - const char * const *opp_pd_tbl; - unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; - const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; - const char * const *clk_rst_tbl; - unsigned int clk_rst_tbl_size; - const char * const *controller_rst_tbl; - unsigned int controller_rst_tbl_size; - u64 dma_mask; - const char *fwname; - struct iris_fmt *inst_iris_fmts; - u32 inst_iris_fmts_size; - struct platform_inst_caps *inst_caps; + + u32 core_arch; + const struct platform_inst_fw_cap *inst_fw_caps_dec; u32 inst_fw_caps_dec_size; const struct platform_inst_fw_cap *inst_fw_caps_enc; u32 inst_fw_caps_enc_size; - const struct tz_cp_config *tz_cp_config_data; - u32 tz_cp_config_data_size; - u32 core_arch; - u32 num_vpp_pipe; - bool no_aon; - u32 max_session_count; - /* max number of macroblocks per frame supported */ - u32 max_core_mbpf; - /* max number of macroblocks per second supported */ - u32 max_core_mbps; + const u32 *dec_input_config_params_default; unsigned int dec_input_config_params_default_size; const u32 *dec_input_config_params_hevc; @@ -253,6 +225,7 @@ struct iris_platform_data { unsigned int enc_input_config_params_size; const u32 *enc_output_config_params; unsigned int enc_output_config_params_size; + const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; @@ -263,6 +236,7 @@ struct iris_platform_data { unsigned int dec_output_prop_vp9_size; const u32 *dec_output_prop_av1; unsigned int dec_output_prop_av1_size; + const u32 *dec_ip_int_buf_tbl; unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; @@ -273,4 +247,45 @@ struct iris_platform_data { unsigned int enc_op_int_buf_tbl_size; }; =20 +struct iris_platform_data { + /* + * XXX: remove firmware_data pointer and consider moving + * get_vpu_buffer_size pointer once we have platforms supporting both + * firmware kinds. + */ + const struct iris_firmware_data *firmware_data; + u32 (*get_vpu_buffer_size)(struct iris_inst *inst, enum iris_buffer_type = buffer_type); + + const struct vpu_ops *vpu_ops; + const struct icc_info *icc_tbl; + unsigned int icc_tbl_size; + const struct bw_info *bw_tbl_dec; + unsigned int bw_tbl_dec_size; + const char * const *pmdomain_tbl; + unsigned int pmdomain_tbl_size; + const char * const *opp_pd_tbl; + unsigned int opp_pd_tbl_size; + const struct platform_clk_data *clk_tbl; + const char * const *opp_clk_tbl; + unsigned int clk_tbl_size; + const char * const *clk_rst_tbl; + unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; + u64 dma_mask; + const char *fwname; + struct iris_fmt *inst_iris_fmts; + u32 inst_iris_fmts_size; + struct platform_inst_caps *inst_caps; + const struct tz_cp_config *tz_cp_config_data; + u32 tz_cp_config_data_size; + u32 num_vpp_pipe; + bool no_aon; + u32 max_session_count; + /* max number of macroblocks per frame supported */ + u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; +}; + #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen1.c b/driver= s/media/platform/qcom/iris/iris_platform_gen1.c index 6ed4c4ae4056..8875f90d487e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen1.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen1.c @@ -332,8 +332,33 @@ static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -const struct iris_platform_data sm8250_data =3D { +const struct iris_firmware_data iris_hfi_gen1_data =3D { .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, + + .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), + + .dec_input_config_params_default =3D + sm8250_vdec_input_config_param_default, + .dec_input_config_params_default_size =3D + ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), + + .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), +}; + +const struct iris_platform_data sm8250_data =3D { + .firmware_data =3D &iris_hfi_gen1_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, @@ -355,35 +380,16 @@ const struct iris_platform_data sm8250_data =3D { .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D tz_cp_config_sm8250, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params =3D sm8250_venc_input_config_param, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; =20 const struct iris_platform_data sc7280_data =3D { - .init_hfi_ops =3D &iris_hfi_gen1_sys_ops_init, + .firmware_data =3D &iris_hfi_gen1_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu2_ops, .icc_tbl =3D sm8250_icc_table, @@ -403,10 +409,6 @@ const struct iris_platform_data sc7280_data =3D { .inst_iris_fmts =3D platform_fmts_sm8250_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8250_dec), .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D tz_cp_config_sm8250, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8250), .num_vpp_pipe =3D 1, @@ -415,19 +417,4 @@ const struct iris_platform_data sc7280_data =3D { .max_core_mbpf =3D 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, /* max spec for SC7280 is 4096x2176@60fps */ .max_core_mbps =3D 4096 * 2176 / 256 * 60, - .dec_input_config_params_default =3D - sm8250_vdec_input_config_param_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8250_vdec_input_config_param_default), - .enc_input_config_params =3D sm8250_venc_input_config_param, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8250_venc_input_config_param), - - .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index abe523db45c2..05fbab276100 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -906,40 +906,16 @@ static const u32 sm8550_enc_op_int_buf_tbl[] =3D { BUF_SCRATCH_2, }; =20 -const struct iris_platform_data sm8550_data =3D { +const struct iris_firmware_data iris_hfi_gen2_data =3D { .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, - .get_vpu_buffer_size =3D iris_vpu_buf_size, - .vpu_ops =3D &iris_vpu3_ops, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - .opp_clk_tbl =3D sm8550_opp_clk_table, - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .inst_iris_fmts =3D platform_fmts_sm8550_dec, - .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), - .inst_caps =3D &platform_inst_cap_sm8550, + + .core_arch =3D VIDEO_ARCH_LX, + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), - .tz_cp_config_data =3D tz_cp_config_sm8550, - .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D NUM_MBS_8K * 2, - .max_core_mbps =3D ((7680 * 4320) / 256) * 60, + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, .dec_input_config_params_default_size =3D @@ -996,6 +972,37 @@ const struct iris_platform_data sm8550_data =3D { .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 +const struct iris_platform_data sm8550_data =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .vpu_ops =3D &iris_vpu3_ops, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + .opp_clk_tbl =3D sm8550_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .inst_iris_fmts =3D platform_fmts_sm8550_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D tz_cp_config_sm8550, + .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, +}; + /* * Shares most of SM8550 data except: * - vpu_ops to iris_vpu33_ops @@ -1004,7 +1011,7 @@ const struct iris_platform_data sm8550_data =3D { * - fwname to "qcom/vpu/vpu33_p4.mbn" */ const struct iris_platform_data sm8650_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, + .firmware_data =3D &iris_hfi_gen2_data, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu33_ops, .icc_tbl =3D sm8550_icc_table, @@ -1028,75 +1035,16 @@ const struct iris_platform_data sm8650_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 const struct iris_platform_data sm8750_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, + .firmware_data =3D &iris_hfi_gen2_data, .get_vpu_buffer_size =3D iris_vpu33_buf_size, .vpu_ops =3D &iris_vpu35_ops, .icc_tbl =3D sm8550_icc_table, @@ -1118,71 +1066,12 @@ const struct iris_platform_data sm8750_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 /* @@ -1190,7 +1079,7 @@ const struct iris_platform_data sm8750_data =3D { * - inst_caps to platform_inst_cap_qcs8300 */ const struct iris_platform_data qcs8300_data =3D { - .init_hfi_ops =3D iris_hfi_gen2_sys_ops_init, + .firmware_data =3D &iris_hfi_gen2_data, .get_vpu_buffer_size =3D iris_vpu_buf_size, .vpu_ops =3D &iris_vpu3_ops, .icc_tbl =3D sm8550_icc_table, @@ -1212,69 +1101,10 @@ const struct iris_platform_data qcs8300_data =3D { .inst_iris_fmts =3D platform_fmts_sm8550_dec, .inst_iris_fmts_size =3D ARRAY_SIZE(platform_fmts_sm8550_dec), .inst_caps =3D &platform_inst_cap_qcs8300, - .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, - .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), - .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, - .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D tz_cp_config_sm8550, .tz_cp_config_data_size =3D ARRAY_SIZE(tz_cp_config_sm8550), - .core_arch =3D VIDEO_ARCH_LX, .num_vpp_pipe =3D 2, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), - .dec_input_config_params_default =3D - sm8550_vdec_input_config_params_default, - .dec_input_config_params_default_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .dec_input_config_params_hevc =3D - sm8550_vdec_input_config_param_hevc, - .dec_input_config_params_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .dec_input_config_params_vp9 =3D - sm8550_vdec_input_config_param_vp9, - .dec_input_config_params_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .dec_input_config_params_av1 =3D - sm8550_vdec_input_config_param_av1, - .dec_input_config_params_av1_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_param_av1), - .dec_output_config_params =3D - sm8550_vdec_output_config_params, - .dec_output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - - .enc_input_config_params =3D - sm8550_venc_input_config_params, - .enc_input_config_params_size =3D - ARRAY_SIZE(sm8550_venc_input_config_params), - .enc_output_config_params =3D - sm8550_venc_output_config_params, - .enc_output_config_params_size =3D - ARRAY_SIZE(sm8550_venc_output_config_params), - - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, - .dec_output_prop_avc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), - .dec_output_prop_hevc =3D sm8550_vdec_subscribe_output_properties_hevc, - .dec_output_prop_hevc_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), - .dec_output_prop_vp9 =3D sm8550_vdec_subscribe_output_properties_vp9, - .dec_output_prop_vp9_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), - .dec_output_prop_av1 =3D sm8550_vdec_subscribe_output_properties_av1, - .dec_output_prop_av1_size =3D - ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), - - .enc_ip_int_buf_tbl =3D sm8550_enc_ip_int_buf_tbl, - .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), - .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, - .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index fa561f6a736c..dd87504c2e67 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -251,6 +251,7 @@ static int iris_probe(struct platform_device *pdev) return core->irq; =20 core->iris_platform_data =3D of_device_get_match_data(core->dev); + core->iris_firmware_data =3D core->iris_platform_data->firmware_data; =20 core->ubwc_cfg =3D qcom_ubwc_config_get_data(); if (IS_ERR(core->ubwc_cfg)) @@ -264,7 +265,7 @@ static int iris_probe(struct platform_device *pdev) disable_irq_nosync(core->irq); =20 iris_init_ops(core); - core->iris_platform_data->init_hfi_ops(core); + core->iris_firmware_data->init_hfi_ops(core); =20 ret =3D iris_init_resources(core); if (ret) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index ecd8a20fedbf..807c9a20b6ba 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -243,7 +243,7 @@ static void iris_session_close(struct iris_inst *inst) =20 static void iris_check_num_queued_internal_buffers(struct iris_inst *inst,= u32 plane) { - const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + const struct iris_firmware_data *firmware_data =3D inst->core->iris_firmw= are_data; struct iris_buffer *buf, *next; struct iris_buffers *buffers; const u32 *internal_buf_type; @@ -251,11 +251,11 @@ static void iris_check_num_queued_internal_buffers(st= ruct iris_inst *inst, u32 p u32 count =3D 0; =20 if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_ip_int_buf_tbl_size; } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + internal_buf_type =3D firmware_data->dec_op_int_buf_tbl; + internal_buffer_count =3D firmware_data->dec_op_int_buf_tbl_size; } =20 for (i =3D 0; i < internal_buffer_count; i++) { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index dbce5aeba06c..c6cfc1d9fd9e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -63,7 +63,7 @@ static void iris_vpu_setup_ucregion_memory_map(struct iri= s_core *core) writel(QTBL_ENABLE, core->reg_base + QTBL_INFO); =20 if (core->sfr_daddr) { - value =3D (u32)core->sfr_daddr + core->iris_platform_data->core_arch; + value =3D (u32)core->sfr_daddr + core->iris_firmware_data->core_arch; writel(value, core->reg_base + SFR_ADDR); } =20 --=20 2.47.3