From nobody Thu Apr 2 14:07:57 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8C5738D006 for ; Sat, 28 Mar 2026 13:55:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774706106; cv=none; b=p4rHOXcy8r0HDfC/7EjP4RP99IvSTy4rEKQLkhOvz4GmI+hpC+/XIhGIcPpPmJKJR6al7yjT9B10HAk9oCe/ww4tF8Uz9ORIzHpwCv9TKhfzPCx5CAOCLmd8CjBfbDh+88LEcHCPxTb+b47pvB0H8JNFLPjlDZPZEmOVSwTGruo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774706106; c=relaxed/simple; bh=Oi0gOGx8Pbzn8cxnk+KDcQyKry6zs4biJs1RjCjCeuk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lhFSVgZcyeb5EeOFj7UgAcNVaYIpMeplLRJC5qc+htw24nzryAJ8PYd6UsKo9p2T9MVTC1/PZDODaaEn0qOQhKw3ErVVBOCMGB3D/7i7J1uB8n7nZpyu+a3eX5BhmSoUz/fraqj4mAr5UoEgoYa3tOYQfdY4pV+eQrRcBeeON2E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=fn7azBtR; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="fn7azBtR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1774706103; bh=Oi0gOGx8Pbzn8cxnk+KDcQyKry6zs4biJs1RjCjCeuk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=fn7azBtRcEOYwiB0nutp/7LpIJDr0JqrM8q2r3j5Im8qnbsr6BT1vWgA1mY3ikyP3 vFpmgVhJ3k0G091xxWBErvDCVI1olapDgF2dXlLSLxaJAp6MIDaaLYALojWuSJ3RlS BmO4C0ct7CWsotykEhr1f0Nkoy/W6COsOx4o5uwYkqcpmstznrUxlONC0KRoGWHfOw LCwXXioKwH6idA0BM/axBLINxqdm3jS62P3Yzo6cGyVUQ+GczpXP8j4ZVNM5HwoJnJ TQW2cE3RGOw3zcOCsrq4pDtAX+ivUCJ5RovjtUO1SaI0mZ3vuQxrwl9esD0TBDL5cc W0ylA6oB4pGbg== Received: from localhost (unknown [86.123.23.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 494AA17E5F39; Sat, 28 Mar 2026 14:55:03 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 28 Mar 2026 15:54:54 +0200 Subject: [PATCH 1/2] phy: hdmi: Add optional FRL TxFFE config options Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260328-hdptx-ffe-v1-1-53ebd5dea20a@collabora.com> References: <20260328-hdptx-ffe-v1-0-53ebd5dea20a@collabora.com> In-Reply-To: <20260328-hdptx-ffe-v1-0-53ebd5dea20a@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.3 During HDMI 2.1 FRL link training, the source and sink can negotiate a Transmitter Feed Forward Equalizer (TxFFE) level to compensate for signal quality degradation. Starting from zero, the source may increment the TxFFE level up to a maximum agreed during the LTS3 stage if the sink keeps reporting FLT failures. It's worth noting TxFFE adjustment is optional and only attempted when both the source and the connected sink support it. Since the existing HDMI PHY configuration API covers the FRL rate/lane selection only, provide the following fields to the frl sub-struct of phy_configure_opts_hdmi: * ffe_level: the TxFFE level to apply, only meaningful when set_ffe_level is set. * set_ffe_level: a 1-bit flag that changes the semantics of the phy_configure() call, i.e. when set, the PHY driver must apply the new ffe_level and ignore the other frl related fields. The flag-based approach reflects an important invariant in the link training process: whenever the FRL rate or lane count changes, the TxFFE level must be reset to zero. A separate phy_configure() call with set_ffe_level can only follow after the rate has been established, making the two operations deliberately distinct. Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index d4cf4430ee8f..1d4b62475079 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -19,6 +19,10 @@ enum phy_hdmi_mode { * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. * @frl.rate_per_lane: HDMI FRL Rate per Lane in Gbps. * @frl.lanes: HDMI FRL lanes count. + * @frl.ffe_level: Transmitter Feed Forward Equalizer Level. + * Optional, only meaningful when set_ffe_level flag is on. + * @frl.set_ffe_level: Flag indicating whether or not to reconfigure ffe_l= evel. + * All the other struct fields must be ignored when this is used. * * This structure is used to represent the configuration state of a HDMI p= hy. */ @@ -29,6 +33,8 @@ struct phy_configure_opts_hdmi { struct { u8 rate_per_lane; u8 lanes; + u8 ffe_level; + u8 set_ffe_level : 1; } frl; }; }; --=20 2.52.0 From nobody Thu Apr 2 14:07:57 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE8B12F83B7 for ; Sat, 28 Mar 2026 13:55:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774706107; cv=none; b=ZC0XJ814EalBDPQ/11VyWCUqyxFH4eUKKgT8cSvYkBYrDbSyt+4fPaflm+rFxo4MZrTSdLERNyiv74vAo+szyl8/mHsbr6E8Ws/AROPQZOwtOkHYYjRXNxHu9GKeLC/ttBvtnEX5jDrJod+5EFFUJACVQ9I8yNfrTdA6ytmIfDA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774706107; c=relaxed/simple; bh=LixLRwS/gYeAuzc200NVhm2SJwSbgTNPuw7cL+mtphg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Cne57G7h5T6JPOuGe/B8VZyy480t68cjO1WJ5VXXNT1agU71l/QpmL7DQgtTAxszQyjeekfwiqhRN+pArA1PpJCnc54ivm0TWTsbOW3J7jqzpeMV+T9HNdM5FHQgR0lDXwMBhe3aHq5jIFdQvqpFXZDnCKf/tnKWoo/SaZWiA+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=nHzRdiNu; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="nHzRdiNu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1774706104; bh=LixLRwS/gYeAuzc200NVhm2SJwSbgTNPuw7cL+mtphg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nHzRdiNuPmHkzrndquE0w8Tw0T/8qnILze85S3fco1vL99HxN+B1vnuY2bWHZ1AU5 rogwJ0Da6NK/PtnJ1ra+YnQt4OgJGV3qY8UZVq3an1siiTUM6P5Y9X9KSMUJvtbS+b 7mKENR64rhW7F+d00D5gtnScIgiIRcuvk3LTMMuviFeK3RN88zFnadpKictTiypj5e FfQJMeMV36py784hop/i383+lI11bE6uZuv7GzQ8Ye23ZF3pG2/W422wNh0WJMKQem JqungLd1IqL7YVLfQ3gWbEoUZP8OEGE85cpAtVbEkbDqDPu5HJDcY6dl0rh6CPWjG2 NY6kpEE7kYcjA== Received: from localhost (unknown [86.123.23.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 35C6717E5F3E; Sat, 28 Mar 2026 14:55:04 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 28 Mar 2026 15:54:55 +0200 Subject: [PATCH 2/2] phy: rockchip: samsung-hdptx: Add support for FRL TxFFE level control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260328-hdptx-ffe-v1-2-53ebd5dea20a@collabora.com> References: <20260328-hdptx-ffe-v1-0-53ebd5dea20a@collabora.com> In-Reply-To: <20260328-hdptx-ffe-v1-0-53ebd5dea20a@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.3 During HDMI 2.1 FRL link training, the source may need to incrementally raise the TxFFE level in response to persistent link failures reported by the sink during LTS3. The phy_configure_opts_hdmi struct now carries ffe_level and set_ffe_level fields to convey such an update independently of a full rate reconfiguration. Wire up the optional TxFFE control in the Samsung HDPTX PHY driver. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 74 +++++++++++++++++++= ++-- 1 file changed, 69 insertions(+), 5 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 3bde7fbb34b1..c4669853ad0e 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -333,6 +333,7 @@ #define FRL_3G3L_RATE 900000000 #define FRL_6G3L_RATE 1800000000 #define FRL_8G4L_RATE 3200000000 +#define FRL_FFE_MAX_LEVEL 3 =20 enum dp_link_rate { DP_BW_RBR, @@ -466,6 +467,16 @@ static const struct ropll_config rk_hdptx_tmds_ropll_c= fg[] =3D { { 25175000ULL, 84, 84, 1, 1, 15, 1, 168, 1, 16, 4, = 1, 1, }, }; =20 +static const struct ffe_config { + u8 pre_shoot; + u8 de_emphasis; +} rk_hdptx_frl_ffe_cfg[FRL_FFE_MAX_LEVEL + 1] =3D { + { 0x3, 0x4 }, + { 0x3, 0x6 }, + { 0x3, 0x8 }, + { 0x3, 0x9 }, +}; + static const struct reg_sequence rk_hdptx_common_cmn_init_seq[] =3D { REG_SEQ0(CMN_REG(0009), 0x0c), REG_SEQ0(CMN_REG(000a), 0x83), @@ -1321,6 +1332,45 @@ static int rk_hdptx_tmds_ropll_mode_config(struct rk= _hdptx_phy *hdptx) return rk_hdptx_post_enable_lane(hdptx); } =20 +static int rk_hdptx_frl_ffe_config(struct rk_hdptx_phy *hdptx, u8 ffe_leve= l) +{ + u8 val; + + if (ffe_level > FRL_FFE_MAX_LEVEL) + return -EINVAL; + + val =3D rk_hdptx_frl_ffe_cfg[ffe_level].pre_shoot; + + regmap_update_bits(hdptx->regmap, LANE_REG(0305), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0405), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0505), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0605), + LN_TX_DRV_PRE_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, val)); + + val =3D rk_hdptx_frl_ffe_cfg[ffe_level].de_emphasis; + + regmap_update_bits(hdptx->regmap, LANE_REG(0304), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0404), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0504), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + regmap_update_bits(hdptx->regmap, LANE_REG(0604), + LN_TX_DRV_POST_LVL_CTRL_MASK, + FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, val)); + return 0; +} + static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) { reset_control_assert(hdptx->rsts[RST_LANE].rstc); @@ -1730,6 +1780,13 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, unsigned long long frl_rate =3D 100000000ULL * hdmi_in->frl.lanes * hdmi_in->frl.rate_per_lane; =20 + if (hdmi_in->frl.set_ffe_level) { + if (hdmi_in->frl.ffe_level > FRL_FFE_MAX_LEVEL) + return -EINVAL; + + return 0; + } + switch (hdmi_in->frl.rate_per_lane) { case 3: case 6: @@ -2076,11 +2133,18 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->pll_config_dirty =3D true; - - dev_dbg(hdptx->dev, "%s %s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.mode ? "FRL" : "TMDS", - hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL && + opts->hdmi.frl.set_ffe_level) { + dev_dbg(hdptx->dev, "%s ffe_level=3D%u\n", __func__, + opts->hdmi.frl.ffe_level); + ret =3D rk_hdptx_frl_ffe_config(hdptx, opts->hdmi.frl.ffe_level); + } else { + hdptx->pll_config_dirty =3D true; + + dev_dbg(hdptx->dev, "%s %s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.mode ? "FRL" : "TMDS", + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); + } } =20 return ret; --=20 2.52.0