From nobody Thu Apr 2 17:23:43 2026 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0D8832C08C4; Fri, 27 Mar 2026 19:25:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.160.252.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774639528; cv=none; b=QvSLIVpp6LW6LKOAIEQjjY9ydHHBgQLXHNT7KY8OWiyhzrvtQu5N6LxyIqSNT0DsQTrCKJ3uIwzbvurWAiSpy8CR+cZNgIjVjn8cJcsPuGG1mKQVqmtO2XDZeMq8nvZwfYekSCoPy0KzSmUyeFqJ5fNU4dWUOjSNvmT9p91j+aI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774639528; c=relaxed/simple; bh=k20QgwAZWpnA6b/c6C/RuK+r57jBn1z7ZB26K2C79vM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sRS7L33NFAZbVzPST+U+N1f2hFxLsFxr/zw/ZZBUPOJ3X1R+jdf/sAmA3axq12q7I2Vd/Drj3aO8VUIEMkCZWrDVzMGMsXCDTRmwHQzr0pUNd2NfF//pl11gdKhDhv5aA2+QVbNYDdyTlzZC9F1xGSHIB1VmBDh27jZ1zEqJ2Os= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com; spf=pass smtp.mailfrom=renesas.com; arc=none smtp.client-ip=210.160.252.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=renesas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=renesas.com X-CSE-ConnectionGUID: OF5gT5nQRQmSZn25Mwi/bA== X-CSE-MsgGUID: oglNec5SRGqnks0lUZLWiw== Received: from unknown (HELO relmlir5.idc.renesas.com) ([10.200.68.151]) by relmlie6.idc.renesas.com with ESMTP; 28 Mar 2026 04:25:24 +0900 Received: from demon-pc.localdomain (unknown [10.226.93.36]) by relmlir5.idc.renesas.com (Postfix) with ESMTP id B63094014C3F; Sat, 28 Mar 2026 04:25:19 +0900 (JST) From: Cosmin Tanislav To: Biju Das , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Lee Jones , Philipp Zabel Cc: linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Cosmin Tanislav Subject: [PATCH 01/11] clk: renesas: r9a09g077: add MTU3 module clock Date: Fri, 27 Mar 2026 21:24:15 +0200 Message-ID: <20260327192425.438263-2-cosmin-gabriel.tanislav.xa@renesas.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com> References: <20260327192425.438263-1-cosmin-gabriel.tanislav.xa@renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a MTU3 block connected to the PCLKH and with a module clock controlled by register 0x308, bit 0. Add support for the module clock. Signed-off-by: Cosmin Tanislav --- drivers/clk/renesas/r9a09g077-cpg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index 93b15e06a19b..f777601a23b9 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -257,6 +257,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] _= _initconst =3D { DEF_MOD("spi0", 104, CLK_SPI0ASYNC), DEF_MOD("spi1", 105, CLK_SPI1ASYNC), DEF_MOD("spi2", 106, CLK_SPI2ASYNC), + DEF_MOD("mtu3", 200, R9A09G077_CLK_PCLKH), DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH), DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH), DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM), --=20 2.53.0