From nobody Thu Apr 2 17:09:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9D683FBED6; Fri, 27 Mar 2026 16:23:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774628633; cv=none; b=lK1XidmT3RAcdfHgFhArK4r47V9CnVROOb34VsLYHGyphbVkB7bGWtx0mc1wwTR9Ann/skQFHHYVLkmQQ5TRw/iAAWzgVgUKwUUUbAIIIkV5yO+J/w9H5ZnGpJ0YwJpkwJcHHDIQrnV3+PCvpffz6mzsFQ0tOny4hChzKt4CSJE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774628633; c=relaxed/simple; bh=p74J85piSN9BkcvDMTXCNhHlHi+VhcHjF9ro/OcIERY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mjXa+cT00xRaO7IIPhFbg1Gge70u6fOb+herwxLPfg0dGlUO/uVfRURinLOJgcEmVxOCSIbU45OrvtiN+YbOLIO5lcf0Mr6WuVYEC5yznCjNYukLGfPT7AYq+RJKi/BPRi4PBoobfKe68l3DGaXqMAdA1aA4N/zZ3OhV1vnVQ54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XL050/D/; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XL050/D/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1774628631; x=1806164631; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p74J85piSN9BkcvDMTXCNhHlHi+VhcHjF9ro/OcIERY=; b=XL050/D/8no3SrgVi1/4WpaKCNKtBrv1qwj3RFLAIQecsur3rE7lQBeQ AE6uy96/JJ9Aav62haqkXG9XiWdSAQvEs9c75/qDjdeQZevxvKVuelqKJ cQKpy/UNRfxytfdqcT2Z/q9ZcA85Hc0RB0YeAJpohGyaUetsvdXESXzz2 RgQTDbfYzRKpVXKMTR9EPcIBOlj7/GW+nJ3Dl/JnJeyXvk/+MhRevRYxz AUa4QiYWaEz0I4RZCHC6+kVecol8s8fI7s13wnoH/MqhNfXH1EKJ1PvkB Hv/N7+z3D82nOJ+p6Z/Nc4KxE7ola2XTLgwJn+6VB0YcdUPSbZ3Fq+d+0 A==; X-CSE-ConnectionGUID: zuY+GoOvSralKgyN+xj5IA== X-CSE-MsgGUID: TddK54gLTBK9KhtRO5fMjg== X-IronPort-AV: E=McAfee;i="6800,10657,11741"; a="79565644" X-IronPort-AV: E=Sophos;i="6.23,144,1770624000"; d="scan'208";a="79565644" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Mar 2026 09:23:51 -0700 X-CSE-ConnectionGUID: NmYVE2SyT9GJw+idXiU8bw== X-CSE-MsgGUID: PuuD2cDqQZWXAnHvUIYGfg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,144,1770624000"; d="scan'208";a="220516334" Received: from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165]) by fmviesa006.fm.intel.com with ESMTP; 27 Mar 2026 09:23:48 -0700 From: Xu Yilun To: linux-coco@lists.linux.dev, linux-pci@vger.kernel.org, dan.j.williams@intel.com, x86@kernel.org Cc: chao.gao@intel.com, dave.jiang@intel.com, baolu.lu@linux.intel.com, yilun.xu@linux.intel.com, yilun.xu@intel.com, zhenzhong.duan@intel.com, kvm@vger.kernel.org, rick.p.edgecombe@intel.com, dave.hansen@linux.intel.com, kas@kernel.org, xiaoyao.li@intel.com, vishal.l.verma@intel.com, linux-kernel@vger.kernel.org Subject: [PATCH v2 21/31] x86/virt/tdx: Add SEAMCALL wrappers for trusted IOMMU setup and clear Date: Sat, 28 Mar 2026 00:01:22 +0800 Message-Id: <20260327160132.2946114-22-yilun.xu@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260327160132.2946114-1-yilun.xu@linux.intel.com> References: <20260327160132.2946114-1-yilun.xu@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Zhenzhong Duan Add SEAMCALLs to setup/clear trusted IOMMU for TDX Connect. Enable TEE I/O support for a target device requires to setup trusted IOMMU for the related IOMMU device first, even only for enabling physical secure links like SPDM/IDE. TDH.IOMMU.SETUP takes the register base address (VTBAR) to position an IOMMU device, and outputs an IOMMU_ID as the trusted IOMMU identifier. TDH.IOMMU.CLEAR takes the IOMMU_ID to reverse the setup. More information see Intel TDX Connect ABI Specification [1] Section 3.2 TDX Connect Host-Side (SEAMCALL) Interface Functions. [1]: https://cdrdv2.intel.com/v1/dl/getContent/858625 Co-developed-by: Xu Yilun Signed-off-by: Xu Yilun Signed-off-by: Zhenzhong Duan --- arch/x86/include/asm/tdx.h | 2 ++ arch/x86/virt/vmx/tdx/tdx.h | 2 ++ arch/x86/virt/vmx/tdx/tdx.c | 32 ++++++++++++++++++++++++++++++-- 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index d7605235aa9b..a59e0e43e465 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -245,6 +245,8 @@ u64 tdh_mem_page_remove(struct tdx_td *td, u64 gpa, u64= level, u64 *ext_err1, u6 u64 tdh_phymem_cache_wb(bool resume); u64 tdh_phymem_page_wbinvd_tdr(struct tdx_td *td); u64 tdh_phymem_page_wbinvd_hkid(u64 hkid, struct page *page); +u64 tdh_iommu_setup(u64 vtbar, struct tdx_page_array *iommu_mt, u64 *iommu= _id); +u64 tdh_iommu_clear(u64 iommu_id, struct tdx_page_array *iommu_mt); #else static inline void tdx_init(void) { } static inline int tdx_cpu_enable(void) { return -ENODEV; } diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index a26fe94c07ff..b25c418f6e61 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -62,6 +62,8 @@ #define TDH_SYS_CONFIG SEAMCALL_LEAF_VER(TDH_SYS_CONFIG_V0, 1) #define TDH_EXT_INIT 60 #define TDH_EXT_MEM_ADD 61 +#define TDH_IOMMU_SETUP 128 +#define TDH_IOMMU_CLEAR 129 =20 /* TDX page types */ #define PT_NDA 0x0 diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 294f36048c03..790713881f1f 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -2084,8 +2084,8 @@ static inline u64 tdx_tdr_pa(struct tdx_td *td) return page_to_phys(td->tdr_page); } =20 -static u64 __maybe_unused __seamcall_ir_resched(sc_func_t sc_func, u64 fn, - struct tdx_module_args *args) +static u64 __seamcall_ir_resched(sc_func_t sc_func, u64 fn, + struct tdx_module_args *args) { struct tdx_module_args _args; u64 r; @@ -2478,3 +2478,31 @@ void tdx_cpu_flush_cache_for_kexec(void) } EXPORT_SYMBOL_FOR_KVM(tdx_cpu_flush_cache_for_kexec); #endif + +u64 tdh_iommu_setup(u64 vtbar, struct tdx_page_array *iommu_mt, u64 *iommu= _id) +{ + struct tdx_module_args args =3D { + .rcx =3D vtbar, + .rdx =3D virt_to_phys(iommu_mt->root), + }; + u64 r; + + tdx_clflush_page_array(iommu_mt); + + r =3D seamcall_ret_ir_resched(TDH_IOMMU_SETUP, &args); + + *iommu_id =3D args.rcx; + return r; +} +EXPORT_SYMBOL_FOR_MODULES(tdh_iommu_setup, "tdx-host"); + +u64 tdh_iommu_clear(u64 iommu_id, struct tdx_page_array *iommu_mt) +{ + struct tdx_module_args args =3D { + .rcx =3D iommu_id, + .rdx =3D virt_to_phys(iommu_mt->root), + }; + + return seamcall_ret_ir_resched(TDH_IOMMU_CLEAR, &args); +} +EXPORT_SYMBOL_FOR_MODULES(tdh_iommu_clear, "tdx-host"); --=20 2.25.1