From nobody Thu Apr 2 17:09:58 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA35B3F7A8E for ; Fri, 27 Mar 2026 13:18:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774617488; cv=none; b=f0TkyG5Xxj60FNt5JCcmmLgdZlPQJmNFbR9x2GW5bLWEtoCp0kMCilR0ohLVdmh+SE/O6B+fhvF2Scw6VSRkQt3LKDQxkwbyOKm6ZULPgK22z1Bx0q8fBmXEWXIWgAHQANF4FvQtvwKeR2EannH5P0oxaYylS8zpAaj2ND/1EIE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774617488; c=relaxed/simple; bh=oSQMFV4a5eQFdGovJkXUHRkZLePRUUpBWPaLvL/RbjE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GOEdLLuv+Ib2Pexznp7tmHm/5yeFUGF7v37TXUdQSu/6Bdea7gmKipejrizb8+eARvqtkubgvcDPXHSFmgQE6a/9sokxEf1ykcVaDgatxG/mYuyI3/y9NalMnxok7mqRQPujLjLc+/JxwSMfimK+y2yUqP+duTLAzinQ+5QMgAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tBYNFCl/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tBYNFCl/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4764AC19423; Fri, 27 Mar 2026 13:18:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774617488; bh=oSQMFV4a5eQFdGovJkXUHRkZLePRUUpBWPaLvL/RbjE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tBYNFCl/dcez8ZnjaNv2Ft2L/2kJhPwTTDVQidbSALXdEkXX5jFqJJ/OlOgixbM+l 98M9r50hV++iwWHLmVI439kq2ofOW4ugrkRnsGdo5zciMHCSBHEKMW2FEecSCAxFxb MAGldl5y9dbd+vahm7tNYIaziHOho7IqfovPkaY2PSu4r1DdTo+DHpqfpGkn3PqZwq FAKxOd2OJSi9iDl+oJJnDZYjsYNisn5G+dchkRnhZ/6DXJCBz2FS+XzAb1hW2dlliS 71lv8oZ5sSFv8ntDTq27sdiMed3hu8i38HO3T+RCtRepv+f8aIq36AnT2QJ4yO9dhk Skz+SKsPDTnOQ== From: srini@kernel.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Finley Xiao , Kever Yang , Heiko Stuebner , Srinivas Kandagatla Subject: [PATCH 7/9] nvmem: rockchip-otp: Add support for RK3568 Date: Fri, 27 Mar 2026 13:17:49 +0000 Message-ID: <20260327131751.3026030-8-srini@kernel.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260327131751.3026030-1-srini@kernel.org> References: <20260327131751.3026030-1-srini@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Finley Xiao This adds the necessary data for handling otp the rk3568. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang Signed-off-by: Heiko Stuebner Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/rockchip-otp.c | 69 ++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index 45bbb6147fb7..cfb69bc58869 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -27,6 +27,7 @@ #define OTPC_USER_CTRL 0x0100 #define OTPC_USER_ADDR 0x0104 #define OTPC_USER_ENABLE 0x0108 +#define OTPC_USER_QP 0x0120 #define OTPC_USER_Q 0x0124 #define OTPC_INT_STATUS 0x0304 #define OTPC_SBPI_CMD0_OFFSET 0x1000 @@ -184,6 +185,58 @@ static int px30_otp_read(void *context, unsigned int o= ffset, return ret; } =20 +static int rk3568_otp_read(void *context, unsigned int offset, void *val, + size_t count) +{ + struct rockchip_otp *otp =3D context; + u16 *buf =3D val; + u32 otp_qp; + int ret; + + ret =3D rockchip_otp_reset(otp); + if (ret) { + dev_err(otp->dev, "failed to reset otp phy\n"); + return ret; + } + + ret =3D rockchip_otp_ecc_enable(otp, true); + if (ret) { + dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); + return ret; + } + + writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); + udelay(5); + + while (count--) { + writel(offset++ | OTPC_USER_ADDR_MASK, + otp->base + OTPC_USER_ADDR); + writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, + otp->base + OTPC_USER_ENABLE); + + ret =3D rockchip_otp_wait_status(otp, OTPC_INT_STATUS, + OTPC_USER_DONE); + if (ret) { + dev_err(otp->dev, "timeout during read setup\n"); + goto read_end; + } + + otp_qp =3D readl(otp->base + OTPC_USER_QP); + if (((otp_qp & 0xc0) =3D=3D 0xc0) || (otp_qp & 0x20)) { + ret =3D -EIO; + dev_err(otp->dev, "ecc check error during read setup\n"); + goto read_end; + } + + *buf++ =3D readl(otp->base + OTPC_USER_Q); + } + +read_end: + writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); + + return ret; +} + static int rk3588_otp_read(void *context, unsigned int offset, void *val, size_t count) { @@ -280,6 +333,18 @@ static const struct rockchip_data px30_data =3D { .reg_read =3D px30_otp_read, }; =20 +static const char * const rk3568_otp_clocks[] =3D { + "otp", "apb_pclk", "phy", "sbpi", +}; + +static const struct rockchip_data rk3568_data =3D { + .size =3D 0x80, + .word_size =3D sizeof(u16), + .clks =3D rk3568_otp_clocks, + .num_clks =3D ARRAY_SIZE(rk3568_otp_clocks), + .reg_read =3D rk3568_otp_read, +}; + static const struct rockchip_data rk3576_data =3D { .size =3D 0x100, .read_offset =3D 0x700, @@ -311,6 +376,10 @@ static const struct of_device_id rockchip_otp_match[] = =3D { .compatible =3D "rockchip,rk3308-otp", .data =3D &px30_data, }, + { + .compatible =3D "rockchip,rk3568-otp", + .data =3D &rk3568_data, + }, { .compatible =3D "rockchip,rk3576-otp", .data =3D &rk3576_data, --=20 2.47.3