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charset="utf-8" Implement the EPC aux-resource API for DesignWare endpoint controllers with integrated eDMA. Currently, only report an interrupt-emulation doorbell register (PCI_EPC_AUX_DOORBELL_MMIO), including its Linux IRQ and the write data needed to trigger the interrupt. If the DMA controller MMIO window is already exposed via a platform-owned fixed BAR subregion, also provide the BAR number and offset so EPF drivers can reuse it without reprogramming the BAR. Signed-off-by: Koichiro Den --- Changes in v12: - Implement the new callback .count_aux_resources(). dw_pcie_ep_get_aux_resources() is refined. .../pci/controller/dwc/pcie-designware-ep.c | 123 ++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 386bfb7b2bf6..b92bc37404c5 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -9,6 +9,7 @@ #include #include #include +#include #include =20 #include "pcie-designware.h" @@ -817,6 +818,126 @@ dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_= no, u8 vfunc_no) return ep->ops->get_features(ep); } =20 +static const struct pci_epc_bar_rsvd_region * +dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep, + enum pci_epc_bar_rsvd_region_type type, + enum pci_barno *bar, + resource_size_t *bar_offset) +{ + const struct pci_epc_features *features; + const struct pci_epc_bar_desc *bar_desc; + const struct pci_epc_bar_rsvd_region *r; + int i, j; + + if (!ep->ops->get_features) + return NULL; + + features =3D ep->ops->get_features(ep); + if (!features) + return NULL; + + for (i =3D BAR_0; i <=3D BAR_5; i++) { + bar_desc =3D &features->bar[i]; + + if (!bar_desc->nr_rsvd_regions || !bar_desc->rsvd_regions) + continue; + + for (j =3D 0; j < bar_desc->nr_rsvd_regions; j++) { + r =3D &bar_desc->rsvd_regions[j]; + + if (r->type !=3D type) + continue; + + if (bar) + *bar =3D i; + if (bar_offset) + *bar_offset =3D r->offset; + return r; + } + } + + return NULL; +} + +static int +dw_pcie_ep_count_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_n= o, + int *num_resources) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + struct dw_edma_chip *edma =3D &pci->edma; + + *num_resources =3D 0; + + if (!pci->edma_reg_size) + return 0; + + if (edma->db_offset =3D=3D ~0) + return 0; + + *num_resources =3D 1; + return 0; +} + +static int +dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + struct pci_epc_aux_resource *resources, + int num_resources) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + const struct pci_epc_bar_rsvd_region *rsvd; + struct dw_edma_chip *edma =3D &pci->edma; + enum pci_barno dma_ctrl_bar =3D NO_BAR; + resource_size_t db_offset =3D edma->db_offset; + resource_size_t dma_ctrl_bar_offset =3D 0; + resource_size_t dma_reg_size; + int count; + int ret; + + ret =3D dw_pcie_ep_count_aux_resources(epc, func_no, vfunc_no, &count); + if (ret) + return ret; + + if (num_resources < count) + return -ENOSPC; + + if (!count) + return 0; + + dma_reg_size =3D pci->edma_reg_size; + + rsvd =3D dw_pcie_ep_find_bar_rsvd_region(ep, + PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO, + &dma_ctrl_bar, + &dma_ctrl_bar_offset); + if (rsvd && rsvd->size < dma_reg_size) + dma_reg_size =3D rsvd->size; + + /* + * For interrupt-emulation doorbells, report a standalone resource + * instead of bundling it into the DMA controller MMIO resource. + */ + if (range_end_overflows_t(resource_size_t, db_offset, + sizeof(u32), dma_reg_size)) + return -EINVAL; + + resources[0] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DOORBELL_MMIO, + .phys_addr =3D pci->edma_reg_phys + db_offset, + .size =3D sizeof(u32), + .bar =3D dma_ctrl_bar, + .bar_offset =3D dma_ctrl_bar !=3D NO_BAR ? + dma_ctrl_bar_offset + db_offset : 0, + .u.db_mmio =3D { + .irq =3D edma->db_irq, + .data =3D 0, /* write 0 to assert */ + }, + }; + + return 0; +} + static const struct pci_epc_ops epc_ops =3D { .write_header =3D dw_pcie_ep_write_header, .set_bar =3D dw_pcie_ep_set_bar, @@ -832,6 +953,8 @@ static const struct pci_epc_ops epc_ops =3D { .start =3D dw_pcie_ep_start, .stop =3D dw_pcie_ep_stop, .get_features =3D dw_pcie_ep_get_features, + .count_aux_resources =3D dw_pcie_ep_count_aux_resources, + .get_aux_resources =3D dw_pcie_ep_get_aux_resources, }; =20 /** --=20 2.51.0