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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KZb6rUOqZFUm49ucvlNo4kBgTsALtw578lYF4qGbRAM=; b=cAbrlM3Hxk6D63eWVIQpT/+91rUxNgpy4nKzRCAvuOOUhoX8QwCg4HfqHhKrKLrgJKDfmb c5wVfbiqO29XNHZyXkI4s1Qre3MqnUiFm02/h8Dnn/KzQ+3OQ9WJJI+aVbFgninh4hEKK9 sHkEFMYy/hETKv449i/YeDyE/HTVWz/5uEYPVDdd57KKPhnFJy8F5MepHRVWYJhpKSQniH xPt49iZDBHKHVJWl4ivSlZe8pnbInHjb0uS3SYRdnngA12U++OSA3hVOjt6qM7gDMZj10E NPjDevZplNmkH9YAkddcN0h6IR7ZW1c4mK9ev93r0xg2xp88+e3u/Pw6ura5Lw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578107; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KZb6rUOqZFUm49ucvlNo4kBgTsALtw578lYF4qGbRAM=; b=KvkYHOBM/Pa2qa21JFvPYDTQavflrdHn2ftrfW+Cc2yhmMqlrCd7WktDeOFmrVEQcYP1fv 20RrKLueKeXodiAQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 73/90] x86/cpu: amd/hygon: Use parsed CPUID(0x80000007) Date: Fri, 27 Mar 2026 03:16:27 +0100 Message-ID: <20260327021645.555257-74-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000007) instead of doing ugly bitwise operations on cpuinfo_x86::x86_power. The latter is backed by a direct CPUID query and will be later removed. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/amd.c | 25 +++++++++++-------------- arch/x86/kernel/cpu/hygon.c | 25 +++++++++++-------------- 2 files changed, 22 insertions(+), 28 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 5fd7f34fa284..96b67b8b694c 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -611,6 +611,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86= *c) =20 static void early_init_amd(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); u32 dummy; =20 if (c->x86 >=3D 0xf) @@ -618,22 +619,18 @@ static void early_init_amd(struct cpuinfo_x86 *c) =20 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); =20 - /* - * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate - * with P/T states and does not stop in deep C-states - */ - if (c->x86_power & (1 << 8)) { - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - } + if (el7) { + if (el7->constant_tsc) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } =20 - /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ - if (c->x86_power & BIT(12)) - set_cpu_cap(c, X86_FEATURE_ACC_POWER); + if (el7->proc_power_reporting) + set_cpu_cap(c, X86_FEATURE_ACC_POWER); =20 - /* Bit 14 indicates the Runtime Average Power Limit interface. */ - if (c->x86_power & BIT(14)) - set_cpu_cap(c, X86_FEATURE_RAPL); + if (el7->rapl_interface) + set_cpu_cap(c, X86_FEATURE_RAPL); + } =20 #ifdef CONFIG_X86_64 set_cpu_cap(c, X86_FEATURE_SYSCALL32); diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 4a63538c2b3f..8f31005bc802 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -125,28 +125,25 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c) =20 static void early_init_hygon(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); u32 dummy; =20 set_cpu_cap(c, X86_FEATURE_K8); =20 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); =20 - /* - * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate - * with P/T states and does not stop in deep C-states - */ - if (c->x86_power & (1 << 8)) { - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - } + if (el7) { + if (el7->constant_tsc) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } =20 - /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ - if (c->x86_power & BIT(12)) - set_cpu_cap(c, X86_FEATURE_ACC_POWER); + if (el7->proc_power_reporting) + set_cpu_cap(c, X86_FEATURE_ACC_POWER); =20 - /* Bit 14 indicates the Runtime Average Power Limit interface. */ - if (c->x86_power & BIT(14)) - set_cpu_cap(c, X86_FEATURE_RAPL); + if (el7->rapl_interface) + set_cpu_cap(c, X86_FEATURE_RAPL); + } =20 #ifdef CONFIG_X86_64 set_cpu_cap(c, X86_FEATURE_SYSCALL32); --=20 2.53.0