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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 57/90] x86/xen: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:11 +0100 Message-ID: <20260327021645.555257-58-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Xen PMU, use parsed CPUID(0xa) instead of a direct CPUID query and ugly bitwise operations. Remove the PMU_{GENERAL,FIXED}_NR macros as they are no longer needed. Signed-off-by: Ahmed S. Darwish --- arch/x86/xen/pmu.c | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 5f50a3ee08f5..b0ef35f2bad3 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -48,18 +48,6 @@ static __read_mostly int amd_num_counters; #define MSR_TYPE_ARCH_COUNTER 3 #define MSR_TYPE_ARCH_CTRL 4 =20 -/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */ -#define PMU_GENERAL_NR_SHIFT 8 -#define PMU_GENERAL_NR_BITS 8 -#define PMU_GENERAL_NR_MASK (((1 << PMU_GENERAL_NR_BITS) - 1) \ - << PMU_GENERAL_NR_SHIFT) - -/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */ -#define PMU_FIXED_NR_SHIFT 0 -#define PMU_FIXED_NR_BITS 5 -#define PMU_FIXED_NR_MASK (((1 << PMU_FIXED_NR_BITS) - 1) \ - << PMU_FIXED_NR_SHIFT) - /* Alias registers (0x4c1) for full-width writes to PMCs */ #define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_PMC0)) =20 @@ -70,6 +58,8 @@ static __read_mostly int intel_num_arch_counters, intel_n= um_fixed_counters; =20 static void xen_pmu_arch_init(void) { + const struct leaf_0xa_0 *leaf_a =3D cpuid_leaf(&boot_cpu_data, 0xa); + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) { =20 switch (boot_cpu_data.x86) { @@ -98,15 +88,9 @@ static void xen_pmu_arch_init(void) amd_ctrls_base =3D MSR_K7_EVNTSEL0; amd_msr_step =3D 1; k7_counters_mirrored =3D 0; - } else { - uint32_t eax, ebx, ecx, edx; - - cpuid(0xa, &eax, &ebx, &ecx, &edx); - - intel_num_arch_counters =3D (eax & PMU_GENERAL_NR_MASK) >> - PMU_GENERAL_NR_SHIFT; - intel_num_fixed_counters =3D (edx & PMU_FIXED_NR_MASK) >> - PMU_FIXED_NR_SHIFT; + } else if (leaf_a) { + intel_num_arch_counters =3D leaf_a->num_counters_gp; + intel_num_fixed_counters =3D leaf_a->num_counters_fixed; } } =20 --=20 2.53.0