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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 56/90] perf/x86/zhaoxin: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:10 +0100 Message-ID: <20260327021645.555257-57-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Zhaoxin perfmon, use parsed CPUID(0xa) instead of issuing CPUID queries and defining custom CPUID output data types. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/zhaoxin/core.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 6ed644fe89aa..1c487d09f65c 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -505,39 +505,36 @@ static __init void zhaoxin_arch_events_quirk(void) =20 __init int zhaoxin_pmu_init(void) { - union cpuid10_edx edx; - union cpuid10_eax eax; - union cpuid10_ebx ebx; + const struct cpuid_regs *regs =3D cpuid_leaf_raw(&boot_cpu_data, 0xa); + const struct leaf_0xa_0 *leaf =3D cpuid_leaf(&boot_cpu_data, 0xa); struct event_constraint *c; - unsigned int unused; - int version; =20 pr_info("Welcome to zhaoxin pmu!\n"); =20 + if (!leaf || !regs) + return -ENODEV; + /* * Check whether the Architectural PerfMon supports * hw_event or not. */ - cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); - - if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT - 1) + if (leaf->events_mask_len < ARCH_PERFMON_EVENTS_COUNT - 1) return -ENODEV; =20 - version =3D eax.split.version_id; - if (version !=3D 2) + if (leaf->pmu_version !=3D 2) return -ENODEV; =20 x86_pmu =3D zhaoxin_pmu; pr_info("Version check pass!\n"); =20 - x86_pmu.version =3D version; - x86_pmu.cntr_mask64 =3D GENMASK_ULL(eax.split.num_counters - 1, 0); - x86_pmu.cntval_bits =3D eax.split.bit_width; - x86_pmu.cntval_mask =3D (1ULL << eax.split.bit_width) - 1; - x86_pmu.events_maskl =3D ebx.full; - x86_pmu.events_mask_len =3D eax.split.mask_length; + x86_pmu.version =3D leaf->pmu_version; + x86_pmu.cntr_mask64 =3D GENMASK_ULL(leaf->num_counters_gp - 1, 0); + x86_pmu.cntval_bits =3D leaf->bit_width_gp; + x86_pmu.cntval_mask =3D (1ULL << leaf->bit_width_gp) - 1; + x86_pmu.events_maskl =3D regs->ebx; + x86_pmu.events_mask_len =3D leaf->events_mask_len; =20 - x86_pmu.fixed_cntr_mask64 =3D GENMASK_ULL(edx.split.num_counters_fixed - = 1, 0); + x86_pmu.fixed_cntr_mask64 =3D GENMASK_ULL(leaf->num_counters_fixed - 1, 0= ); x86_add_quirk(zhaoxin_arch_events_quirk); =20 switch (boot_cpu_data.x86) { @@ -617,4 +614,3 @@ __init int zhaoxin_pmu_init(void) =20 return 0; } - --=20 2.53.0