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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZonDWpy1+jQJ9O62WLSvhrExZUpqVbLHiHBAaECowEM=; b=0gbkCmzHQNGAXAgaA31eliMtYRPXAyLL+UQvD0p+3xcPs9NjFoy2OZOOyD/EDF1sCK6/q/ 9+4kCyiBiLA0Oqns48WjtwK8Ec7SVlyNJMX53SMzN+WvHzeSOJQEp0XSxjSKHd2RWi8Isq tICd5LSllKFk8VgRA0MQ9+yf1oodLk8/2L4p7i+QwA+6weFRKRtpLHQjMTYsaZlpU3Ees2 86AVp3k24OnJkKN0AfNcVzKgZFKwsZ14T/UmWAIW1qA+7MnHSATWK/se9MP/TSmbI2b8kI F+OP+CljayBiLfGjexmPTS8QxBRBH8PVfNc6K8+GZtLIEM6jKCO/H+NwuFFXxg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZonDWpy1+jQJ9O62WLSvhrExZUpqVbLHiHBAaECowEM=; b=QIe3PFxSidIUdj7AoLnk2k5/s9W6UYnjdKTi5D1LGDmMMj1S5LcoY9dsWmiCeU2Ml4PIKc xs6jE3QOh3lYyGAQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 43/90] x86/cacheinfo: Use parsed CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:15:57 +0100 Message-ID: <20260327021645.555257-44-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD cacheinfo, use parsed CPUID(0x80000006) instead of issuing a direct CPUID query. Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their C99 bitfields, instead of doing ugly bitwise operations on CPUID output. For enumerating L3 cache availability, check if CPUID(0x80000006).EDX l3_assoc output is not zero. Per AMD manuals, an L3 associativity of zero implies the absence of a CPU L3 cache. Since cpuid_amd_hygon_has_l3_cache() is now using the CPUID parser APIs, move its definition under the section: "Convenience leaf-specific functions (using parsed CPUID)." Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 20 +++++++++++--------- arch/x86/kernel/amd_nb.c | 3 ++- arch/x86/kernel/cpu/cacheinfo.c | 6 +++--- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index f4bdfe3c9325..611ee8596115 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -212,15 +212,6 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) return 0; } =20 -/* - * CPUID(0x80000006) parsing: - */ - -static inline bool cpuid_amd_hygon_has_l3_cache(void) -{ - return cpuid_edx(0x80000006); -} - /* * 'struct cpuid_leaves' accessors (without sanity checks): * @@ -502,6 +493,17 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) _ptr < &((const union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = =3D &cpuid_0x2_table[*_ptr]);\ _ptr++) =20 +/* + * CPUID(0x80000006) + */ + +static inline bool cpuid_amd_hygon_has_l3_cache(struct cpuinfo_x86 *c) +{ + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); + + return el6 && el6->l3_assoc; +} + /* * CPUID parser exported APIs: */ diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 5d364540673d..06ebbd564945 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -16,6 +16,7 @@ =20 #include #include +#include =20 static u32 *flush_words; =20 @@ -93,7 +94,7 @@ static int amd_cache_northbridges(void) if (amd_gart_present()) amd_northbridges.flags |=3D AMD_NB_GART; =20 - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(&boot_cpu_data)) return 0; =20 /* diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 7dab0d7152cc..3e40bcca1c3b 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -235,7 +235,7 @@ static unsigned int get_cache_id(u32 apicid, const stru= ct _cpuid4_info *id4) =20 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id) { - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return; =20 if (c->x86 < 0x17) { @@ -262,7 +262,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) =20 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c) { - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return; =20 /* @@ -280,7 +280,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) if (boot_cpu_has(X86_FEATURE_TOPOEXT)) ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); else if (el6) - ci->num_leaves =3D (el6->l3_assoc) ? 4 : 3; + ci->num_leaves =3D cpuid_amd_hygon_has_l3_cache(c) ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) --=20 2.53.0