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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=84dJ5ZsqsImkHCTBhgFQOb5wNlKJl20ElzbvXguKl00=; b=CRjYU7qIqaxpekBbItuS/1Q9n77jHEexHyWioAF3wl+qiRTjiUC3rh6QXVCU42FezAN/34 Oa+ml96jRbe9Nw/aqkY1mP6+nkbHIOY9zKhUO0vOEPeyT4xtl+AGFMRJvXFnQxYadgJIvx IkDMNja6QE/tBDiKxA1sJaNhX/xsl/ngxlcCuCnBLxNgpFKcu6rn6CuLUySZ5Ylg+BNrWQ PkTmFGE9Iw2cTExtsCct7udoe+Y8Noez+u5NexpKyi/lLUP3xA3pm1ICIuY0WEHFOGU8TT +Tvck7jk6iNx1wPrjaUiNsJdrLjBl5vlYHW4jM8onpY5NX0W9Lzy3n19uqStcA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=84dJ5ZsqsImkHCTBhgFQOb5wNlKJl20ElzbvXguKl00=; b=uMXPLQOk2QqpI72AU1DzJBx6YfWtAFpMaRUKGXG7iaAOu/bq8m+tgVOmHf4dR6wuTBFCsi /UIWJzta1O/643Ag== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 38/90] x86/cacheinfo: Use parsed CPUID(0x4) Date: Fri, 27 Mar 2026 03:15:52 +0100 Message-ID: <20260327021645.555257-39-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Intel cacheinfo, use parsed CPUID(0x4) instead of a direct CPUID query. Use the CPUID API cpuid_subleaf_count(c, 0x4) to determine the number of CPUID(0x4) cache subleaves instead of calling find_num_cache_leaves(). The latter function internally invokes direct CPUID(0x4) queries. Since find_num_cache_leaves() is no longer needed for Intel code paths, make its name and implementation AMD-specific. Adjust the AMD code paths accordingly. At intel_cacheinfo_0x4(), remove the max CPUID level check since cpuid_subleaf_count(c, 0x4) will return zero if CPUID(0x4) is not valid. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 40 ++++++++++++++------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 07f7e7b667ed..91020f85c000 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,16 +252,17 @@ static int amd_fill_cpuid4_info(int index, struct _cp= uid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; - u32 ignored; + const struct cpuid_regs *regs =3D cpuid_subleaf_n_raw(c, 0x4, index); =20 - cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &ignored); + if (!regs) + return -EIO; =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, + (union _cpuid4_leaf_eax)(regs->eax), + (union _cpuid4_leaf_ebx)(regs->ebx), + (union _cpuid4_leaf_ecx)(regs->ecx)); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -273,17 +274,16 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf intel_fill_cpuid4_info(c, index, id4); } =20 -static int find_num_cache_leaves(struct cpuinfo_x86 *c) +static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) { - unsigned int eax, ebx, ecx, edx, op; union _cpuid4_leaf_eax cache_eax; + unsigned int eax, ebx, ecx, edx; int i =3D -1; =20 - /* Do a CPUID(op) loop to calculate num_cache_leaves */ - op =3D (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_V= ENDOR_HYGON) ? 0x8000001d : 4; + /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ do { ++i; - cpuid_count(op, i, &eax, &ebx, &ecx, &edx); + cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); cache_eax.full =3D eax; } while (cache_eax.split.type !=3D CTYPE_NULL); return i; @@ -328,7 +328,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) * Newer families: LLC ID is calculated from the number * of threads sharing the L3 cache. */ - u32 llc_index =3D find_num_cache_leaves(c) - 1; + u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; struct _cpuid4_info id4 =3D {}; =20 if (!amd_fill_cpuid4_info(llc_index, &id4)) @@ -353,7 +353,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -362,7 +362,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, @@ -426,15 +426,9 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) unsigned int l2_id =3D BAD_APICID, l3_id =3D BAD_APICID; unsigned int l1d =3D 0, l1i =3D 0, l2 =3D 0, l3 =3D 0; =20 - if (c->cpuid_level < 4) - return false; - - /* - * There should be at least one leaf. A non-zero value means - * that the number of leaves has been previously initialized. - */ + /* Non-zero means that it has been previously initialized */ if (!ci->num_leaves) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x4); =20 if (!ci->num_leaves) return false; --=20 2.53.0