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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577952; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UUQ76hlD26YEpumyfNSfOXMLQXNffvEAUoB8LCX9+mM=; b=KF2d8+i5QLjXQptX4EN17Ya8ckBvdX5XITYRTqSm/5axap/fb7ETx1dxoOnWw0qwgAjZcI 1DoCoRfTlcCqQreuJZXE4lughRLHYFOnrQQwldKJevzYhrdDYDNA1cAIIiRDtiUaCNEGOc 3VMNxfkF4FDiR21x00EMXyeS3Dm4eu8aQEYE/VtCVdykTTxFEQrE0FSyYURsMHbNLcZOGU 1FA+GJx/0YR4yLPtuizm5cJtEN+HvbRZzPU7wMGNfmCkapL9n1gumRpIoVdrDy1UIar48A +fITjgA2bZDuASzHhbEa7r+OIZ32uRlEAVFVVFcRa9OoKjhZ+WKT1TX217LiZw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577952; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UUQ76hlD26YEpumyfNSfOXMLQXNffvEAUoB8LCX9+mM=; b=YqnH6KaHeatTKx3JxQtPYcXF4kIusu1F3+YI1U3OB4wxNdfVTWzoaqJWdxDh7ePuzxasCD tJEPyWLZh8YqOhBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 31/90] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Date: Fri, 27 Mar 2026 03:15:45 +0100 Message-ID: <20260327021645.555257-32-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CPUID(0x2) output includes a "query count" byte. That byte was supposed to specify the number of repeated CPUID(0x2) subleaf 0 queries needed to extract all of the CPU's cache and TLB descriptors. Per current Intel manuals, all CPUs supporting this leaf "will always" return an iteration count of 1. Since the CPUID parser ignores any CPUID(0x2) output with an invalid iteration count, lightly warn about this once in the kernel log. Do not emit a warning if some of the CPUID(0x2) output registers, or even all of them, are invalid. This is an architecturally-defined response. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish References: b5969494c8d8 ("x86/cpu: Remove CPUID leaf 0x2 parsing loop") Link: https://lore.kernel.org/lkml/aBnmy_Bmf-H0wxqz@gmail.com --- arch/x86/kernel/cpu/cpuid_parser.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index be340b202182..bddd9937bb2b 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -3,6 +3,8 @@ * CPUID parser; for populating the system's CPUID tables. */ =20 +#define pr_fmt(fmt) "x86/cpuid: " fmt + #include =20 #include @@ -54,8 +56,11 @@ cpuid_read_0x2(const struct cpuid_parse_entry *e, const = struct cpuid_read_output * keep the leaf marked as invalid at the CPUID table. */ cpuid_read_subleaf(e->leaf, e->subleaf, l); - if (l->iteration_count !=3D 0x01) + if (l->iteration_count !=3D 0x01) { + pr_warn_once("Ignoring CPUID(0x2) due to invalid iteration count =3D %d", + l->iteration_count); return; + } =20 /* * The most significant bit (MSB) of each CPUID(0x2) register must be cle= ar. --=20 2.53.0