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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 29/90] x86/cpu: zhaoxin: Use parsed CPUID(0xc0000001) Date: Fri, 27 Mar 2026 03:15:43 +0100 Message-ID: <20260327021645.555257-30-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0xc0000001). Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their full C99 bitfields, instead of doing ugly bitwise operations on the CPUID output. Keep the x86_capability[] CPUID(0xc0000001).EDX assignment. It will be removed once X86_FEATURE translation is integrated into the CPUID model. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/zhaoxin.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 55bc656aaa95..ea76e9594453 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -11,35 +11,26 @@ =20 #define MSR_ZHAOXIN_FCR57 0x00001257 =20 -#define ACE_PRESENT (1 << 6) -#define ACE_ENABLED (1 << 7) #define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */ - -#define RNG_PRESENT (1 << 2) -#define RNG_ENABLED (1 << 3) #define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */ =20 static void init_zhaoxin_cap(struct cpuinfo_x86 *c) { - u32 lo, hi; - - /* Test for Extended Feature Flags presence */ - if (cpuid_eax(0xC0000000) >=3D 0xC0000001) { - u32 tmp =3D cpuid_edx(0xC0000001); + const struct leaf_0xc0000001_0 *l1 =3D cpuid_leaf(c, 0xc0000001); + u32 lo, hi; =20 + if (l1) { /* Enable ACE unit, if present and disabled */ - if ((tmp & (ACE_PRESENT | ACE_ENABLED)) =3D=3D ACE_PRESENT) { + if (l1->ace && !l1->ace_en) { rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); - /* Enable ACE unit */ lo |=3D ACE_FCR; wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); pr_info("CPU: Enabled ACE h/w crypto\n"); } =20 /* Enable RNG unit, if present and disabled */ - if ((tmp & (RNG_PRESENT | RNG_ENABLED)) =3D=3D RNG_PRESENT) { + if (l1->rng && !l1->rng_en) { rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); - /* Enable RNG unit */ lo |=3D RNG_ENABLE; wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); pr_info("CPU: Enabled h/w RNG\n"); --=20 2.53.0