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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k6RexfKn63PVkV40YkO5QUPdJNYkFm5PzRZKkuBaxtE=; b=06dDE2LINebR3R871GYXU9Yoc35wmmPAdyWXO04zbCXL3pqOiigRM+jYoJhFgnmSuDyRFe 4RHf3iRX5fA3zcuyEaRtvg8AMYE+oOZ5600x/+qrm3/7JkfvmlJUy3x1+O9lQu4dUX4aUC xY3cqkkX4Nu/DjUwzVmX3GBy4TaDagaSBRFBUUomnn63S3xmt2UzSCAPFKBr7+2/EK+y3g sn/w14jjZ5Z6xAoLNUFAw0E/0e8uLkH2E4gPjHJ0iFEqo4J/4ReMYffr/ZOMwTGtAjVkot R6BhPuoutNFIEHvDrsEfKntHUzNqyyMSkRhs9KtEBNEEKQSWbz/WSBtVLJcj6Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k6RexfKn63PVkV40YkO5QUPdJNYkFm5PzRZKkuBaxtE=; b=/3cNmJ9G1FPF1OlirO3vxQmUPL2+jumGfbsWxbZEMQIFGS1uRDUDFNDljymvVzrXmLjsw4 MNoPyut9ReSG35Cg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 28/90] x86/cpu: centaur: Use parsed CPUID(0xc0000001) Date: Fri, 27 Mar 2026 03:15:42 +0100 Message-ID: <20260327021645.555257-29-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0xc0000001). Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their full C99 bitfields, instead of doing ugly bitwise operations on the CPUID output. Keep the x86_capability[] CPUID(0xc0000001).EDX assignment. It will be removed once X86_FEATURE translation is integrated into the CPUID model. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index a97e38fa6a9f..5f09bce3aaa7 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -12,34 +12,27 @@ =20 #include "cpu.h" =20 -#define ACE_PRESENT (1 << 6) -#define ACE_ENABLED (1 << 7) #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ - -#define RNG_PRESENT (1 << 2) -#define RNG_ENABLED (1 << 3) #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ =20 static void init_c3(struct cpuinfo_x86 *c) { - u32 lo, hi; - - /* Test for Centaur Extended Feature Flags presence */ - if (cpuid_eax(0xC0000000) >=3D 0xC0000001) { - u32 tmp =3D cpuid_edx(0xC0000001); + const struct leaf_0xc0000001_0 *l1 =3D cpuid_leaf(c, 0xc0000001); + u32 lo, hi; =20 - /* enable ACE unit, if present and disabled */ - if ((tmp & (ACE_PRESENT | ACE_ENABLED)) =3D=3D ACE_PRESENT) { + if (l1) { + /* Enable ACE unit, if present and disabled */ + if (l1->ace && !l1->ace_en) { rdmsr(MSR_VIA_FCR, lo, hi); - lo |=3D ACE_FCR; /* enable ACE unit */ + lo |=3D ACE_FCR; wrmsr(MSR_VIA_FCR, lo, hi); pr_info("CPU: Enabled ACE h/w crypto\n"); } =20 - /* enable RNG unit, if present and disabled */ - if ((tmp & (RNG_PRESENT | RNG_ENABLED)) =3D=3D RNG_PRESENT) { + /* Enable RNG unit, if present and disabled */ + if (l1->rng && !l1->rng_en) { rdmsr(MSR_VIA_RNG, lo, hi); - lo |=3D RNG_ENABLE; /* enable RNG unit */ + lo |=3D RNG_ENABLE; wrmsr(MSR_VIA_RNG, lo, hi); pr_info("CPU: Enabled h/w RNG\n"); } --=20 2.53.0