From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 47D3930E82D for ; Fri, 27 Mar 2026 02:17:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577845; cv=none; b=Gz7P8ozd+MBsAXjcUPUAcR/nfkG9aitDmqy5e/XnvKmeZVSGBM944lVw41CXSNtaYcUPkjM2ZmBA6ygq4L4jXMBVokSosLkjkj1KZ7NPCWv87XxRU/MoTKQqp3uuBUrMstgfKYHYXD8VTJqQAKzU/C0FTqutLB2bM0osjix8ntY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577845; c=relaxed/simple; bh=ih2nxDk2dwtWmrvO2nQ/VdnvKPJKjCoQJoK5xF1/Ecs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d9K3LLYHZ88JeGdxyEhuN/Qp9Q/735nhUC+IY2WJ615rgnNzNGymk+gbQD29FZtr4Xil4cghWG2kgvz4c0llxSZkY2k5qUeYun7UPWwQEjivTwZ8ThmJjHnOeyB3EeN1dgLRieVoy3Tdzf+644WqyN0F5LBaN2aI309DiNB9icY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bJ81nGEX; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=svrTCv9i; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bJ81nGEX"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="svrTCv9i" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vJq6K4+bcb3KelCrkP8+8wkoczV5o5s+TfbA+fjW2nQ=; b=bJ81nGEXfUDW8Cq5qyIThDlEgmpChdfVdupT+JP8srRdszZxO4w9/i8QhvSFbyUe6Enezl /m7nWjA5FisATqjEjY8IudZAi6bYXd1WpRTmclXEibDML/qGmL1sF4XRICT3hqCQyO1FJt YEwD4xaBcDhTeAAlwa6fb8xIfpij3KbK0yi+PVu8rzULUnuqZcSkPKaHa37/+e5waYCAZ3 4SFBSi7FEPBQ9P7fhxWDoWMs2a0Mz/v/rgDH1SOv59XEltNwuCr/sg/zWI/REznOzot0Bu 2XjO0uythBoGdkvjxthbXu+DiT+JqFwayzicpQNI7TsieDeVi+EuWSKZsqw9gQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vJq6K4+bcb3KelCrkP8+8wkoczV5o5s+TfbA+fjW2nQ=; b=svrTCv9iBPfUHjYTv/qp1SE8qsqoEUntQAVjDJg8pdgcYjPgo23ZNvzHcZ6rWDUc2OHLeE d7zt9dn7fCS/qGCQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 01/90] ASoC: Intel: avs: Check maximum valid CPUID leaf Date: Fri, 27 Mar 2026 03:15:15 +0100 Message-ID: <20260327021645.555257-2-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel AVS driver queries CPUID(0x15) before checking if the CPUID leaf is available. Check the maximum-valid CPU standard leaf beforehand. Use the CPUID_LEAF_TSC macro instead of defining a custom local one for the CPUID(0x15) leaf number. Note, the inclusion of a header file from within a C function will be fixed in a separate commit next. Fixes: cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platf= orms") Signed-off-by: Ahmed S. Darwish Acked-by: Cezary Rojewski --- sound/soc/intel/avs/tgl.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c index afb066516101..4649d749b41e 100644 --- a/sound/soc/intel/avs/tgl.c +++ b/sound/soc/intel/avs/tgl.c @@ -11,8 +11,6 @@ #include "debug.h" #include "messages.h" =20 -#define CPUID_TSC_LEAF 0x15 - static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, boo= l power) { core_mask &=3D AVS_MAIN_CORE_MASK; @@ -49,7 +47,11 @@ static int avs_tgl_config_basefw(struct avs_dev *adev) unsigned int ecx; =20 #include - ecx =3D cpuid_ecx(CPUID_TSC_LEAF); + + if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) + goto no_cpuid; + + ecx =3D cpuid_ecx(CPUID_LEAF_TSC); if (ecx) { ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(e= cx), &ecx); if (ret) @@ -57,6 +59,7 @@ static int avs_tgl_config_basefw(struct avs_dev *adev) } #endif =20 +no_cpuid: hwid.device =3D pci->device; hwid.subsystem =3D pci->subsystem_vendor | (pci->subsystem_device << 16); hwid.revision =3D pci->revision; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88F3A330330 for ; Fri, 27 Mar 2026 02:17:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577849; cv=none; b=ms1shzWLOKURr0ZS7EEas/iMd5D9L8kzsUfFjchi8cgocrmYIQzIrPg8qJ7vRoHJF0WMY/MaEl7RcVNQKwoAhEOAMfA8A1EAu8T76275FP4iUS+ipXzqVPMifN2VtEnTq7htZnDFUZWVfBuho4TPij3nC9F6gvRJZ5IWdhDEJMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577849; c=relaxed/simple; bh=f+/iJHeyDwYH3sBCvhNNFtLCIBZtC3JZoaVR7r/mweU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FEPQoR1/U0wAMMUffRGo2xrev73PZYzmK0Km2LQPzcR1+CQcQtr2WNUwz+PnZr5jxG7ArU9L59k+ma53CSTu4rEbDBT75vwJEoKj0BPB/1UwoFyN/2ycN9ZSE6WOu36/ARDsHgVZCOHTutU0z6cQNrECV9wqaeOjko3bjnAKh1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=B2hs0m9t; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ush0OZai; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="B2hs0m9t"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ush0OZai" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Mrl8XmJ7o7sgBcCDvX+j3CF0YEVIJIsLch2G1f2gE5o=; b=B2hs0m9tJM54bUwBQMd4fwHZemVx3mtfZnvwNQncjg/D/Emg55G+RFLzHuAwOSIj8YBJn4 6GF0q9qQ1MgkUaBfILtUgNP8gzow2IJrWHXMKCz0f1InTZ17h0ioKoxTxu5HwSaA239Vue 4Jp8Bx/UYYCRHPhwDiSNoGgMHD7XwiMzsODQMslgEiK9VHXHvX1GbxtkCK/mKsUa57YKnj X7D9Ytt9ASGHj8DSjKH88KHcN85A5yQsLdsJ5Po88II3YpU/KtBcyib9X2TwvyrCaYVa5W Mh+ABE97/DmAhlbx0dcKDIkN4MbW4edHBJ32JT0M9+QjAEk86MShO2caMkLuow== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Mrl8XmJ7o7sgBcCDvX+j3CF0YEVIJIsLch2G1f2gE5o=; b=ush0OZaiZ+DjWux+fuUy4iQpQPI5NCWi3f0UPck7dLzy8MwHGqEPSfbLKe8Tv6XVGW0wqS cw2R99Vb41SN9TDQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 02/90] ASoC: Intel: avs: Include CPUID header at file scope Date: Fri, 27 Mar 2026 03:15:16 +0100 Message-ID: <20260327021645.555257-3-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platform= s") includes the main CPUID header from within a C function. This works by luck and forbids valid refactorings inside that header. Include the CPUID header at file scope instead. Remove the COMPILE_TEST build flag so that the CONFIG_X86 conditionals can be removed. The driver gets enough compilation testing already on x86. For clarity, refactor the CPUID(0x15) code into its own function without changing any of the driver's logic. Suggested-by: Borislav Petkov # CONFIG_X86 removal Signed-off-by: Ahmed S. Darwish Fixes: cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platf= orms") References: 47a1886a610a ("ASoC: Intel: avs: Enable AVS driver only on x86 = platforms") Link: https://lore.kernel.org/r/20251016105514.GCaPDPEu016XyDocfY@fat_crate= .local Link: https://lore.kernel.org/r/da5bf77b-5bdb-440f-92b5-db35d8687987@intel.= com Acked-by: Cezary Rojewski --- sound/soc/intel/Kconfig | 2 +- sound/soc/intel/avs/tgl.c | 37 ++++++++++++++++++++++++------------- 2 files changed, 25 insertions(+), 14 deletions(-) diff --git a/sound/soc/intel/Kconfig b/sound/soc/intel/Kconfig index 412555e626b8..63367364916a 100644 --- a/sound/soc/intel/Kconfig +++ b/sound/soc/intel/Kconfig @@ -95,7 +95,7 @@ config SND_SOC_INTEL_KEEMBAY =20 config SND_SOC_INTEL_AVS tristate "Intel AVS driver" - depends on X86 || COMPILE_TEST + depends on X86 depends on PCI depends on COMMON_CLK select ACPI_NHLT if ACPI diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c index 4649d749b41e..a7123639de43 100644 --- a/sound/soc/intel/avs/tgl.c +++ b/sound/soc/intel/avs/tgl.c @@ -7,6 +7,7 @@ // =20 #include +#include #include "avs.h" #include "debug.h" #include "messages.h" @@ -38,28 +39,38 @@ static int avs_tgl_dsp_core_stall(struct avs_dev *adev,= u32 core_mask, bool stal return avs_dsp_core_stall(adev, core_mask, stall); } =20 -static int avs_tgl_config_basefw(struct avs_dev *adev) +/* + * Succeed if CPUID(0x15) is not available, or if the nominal core crystal= clock + * frequency cannot be enumerated from it. There is nothing to do in both= cases. + */ +static int avs_tgl_set_xtal_freq(struct avs_dev *adev) { - struct pci_dev *pci =3D adev->base.pci; - struct avs_bus_hwid hwid; + unsigned int freq; int ret; -#ifdef CONFIG_X86 - unsigned int ecx; - -#include =20 if (boot_cpu_data.cpuid_level < CPUID_LEAF_TSC) - goto no_cpuid; + return 0; =20 - ecx =3D cpuid_ecx(CPUID_LEAF_TSC); - if (ecx) { - ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(e= cx), &ecx); + freq =3D cpuid_ecx(CPUID_LEAF_TSC); + if (freq) { + ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(f= req), &freq); if (ret) return AVS_IPC_RET(ret); } -#endif =20 -no_cpuid: + return 0; +} + +static int avs_tgl_config_basefw(struct avs_dev *adev) +{ + struct pci_dev *pci =3D adev->base.pci; + struct avs_bus_hwid hwid; + int ret; + + ret =3D avs_tgl_set_xtal_freq(adev); + if (ret) + return ret; + hwid.device =3D pci->device; hwid.subsystem =3D pci->subsystem_vendor | (pci->subsystem_device << 16); hwid.revision =3D pci->revision; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EFD032D0D4 for ; Fri, 27 Mar 2026 02:17:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577858; cv=none; b=sTR8lA8VC+rWBrQhQYJOCMllOCpPBu8cShG59TmJHnxhwNbMs05Etml+8AwEybASMRtsomxhbUNlkDBjazdNK27nectBgJhW9Z4DPZUwDlbQpOHF66x9eM0hjgq/84bcQilHXmT2C2mZNipn+A67PZtppTqWpAEh/itLgc0Esko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577858; c=relaxed/simple; bh=ghFshrFU3jYkQYkp2GZQNg4pjmSAIctdSBS9OCvCZSQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X5oDMYbn6RvGCEcwg7Hixu1ID69NBQROJqH0adlfJ4LPKRs6KxJwBAN3dOl/nb6bLM8PTgn+uByKMDd7/DbUP8F0I9Weh6ITV0A84IyS3pJpusmDP9+e4mWGn86JV7USihX61hlBIiIzfFoyljRg9KML/8JSjJMdlCi69xsjiy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZemopYc3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+NgVXT6u; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZemopYc3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+NgVXT6u" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yrRAKSp2IM5U3oZgmSYIS+CiNAzj3Dt6AM+Z0DHVR1Y=; b=ZemopYc3m3K/N9NIFI0AatQF6yXtKh7pSdZ5kiRw5n6wSgmeOx/NoqEEDY0uNkfBtqE/nD JuBg/EJXdk+KrZM5YVXXtCsPoDZBmINO9tvJM7+zKuROZEghiD3UyLM0Vp4bTVC58hJoT9 TTYk6XKkoZ6vzpQB7JFr1eGA3HNBzjZLxV5Gn7igh3F/Gg/b57D7QOJ5/nrNRNZe5OTHWa Syxjc4mi61ywx4j1rNj279WkOK6Euv8oVauommVJuWcRrQushtVUc3xaJiyZMfQBLtmTfn ChgifcYfw607BgPJvzrLvqQWMl1vUskeR0eQ89tvuA6hmX07pjHUZTudAQqDdw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yrRAKSp2IM5U3oZgmSYIS+CiNAzj3Dt6AM+Z0DHVR1Y=; b=+NgVXT6uQG3VwZoEJpeWtCZjdjawK/bnmyRwaK8fUpCuCGxOz6X7Wzy/cTM2a9A9iKLuNQ t+p+uxOe/PYYBvDg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 03/90] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v3.0 Date: Fri, 27 Mar 2026 03:15:17 +0100 Message-ID: <20260327021645.555257-4-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV to version 3.0, as generated by x86-cpuid-db. Summary of the v2.5 changes: - Reduce the verbosity of leaf and bitfields descriptions, as formerly requested by Boris. - Leaf 0x8000000a: Add Page Modification Logging (PML) bit. Summary of the v3.0 changes: - Leaf 0x23: Introduce subleaf 2, Auto Counter Reload (ACR) - Leaf 0x23: Introduce subleaf 4/5, PEBS capabilities and counters - Leaf 0x1c: Return LBR depth as a bitmask instead of individual bits - Leaf 0x0a: Use more descriptive PMU bitfield names - Leaf 0x0a: Add various missing PMU events - Leaf 0x06: Add missing IA32_HWP_CTL flag - Leaf 0x0f: Add missing non-CPU (IO) Intel RDT bits Thanks to Dave Hansen for reporting multiple missing bits. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.5/CHANGELOG.r= st Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.0/CHANGELOG.r= st --- tools/arch/x86/kcpuid/cpuid.csv | 671 +++++++++++++++++--------------- 1 file changed, 347 insertions(+), 324 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index 8d925ce9750f..9f5155c825ca 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.4 +# Generator: x86-cpuid-db v3.0 =20 # # Auto-generated file. @@ -10,9 +10,9 @@ # LEAF, SUBLEAVES, reg, bits, short_name , long_des= cription =20 # Leaf 0H -# Maximum standard leaf number + CPU vendor string +# Maximum standard leaf + CPU vendor string =20 - 0x0, 0, eax, 31:0, max_std_leaf , Highest = standard CPUID leaf supported + 0x0, 0, eax, 31:0, max_std_leaf , Highest = standard CPUID leaf 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 @@ -134,23 +134,23 @@ 0x4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) =20 # Leaf 5H -# MONITOR/MWAIT instructions enumeration +# MONITOR/MWAIT instructions =20 0x5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes 0x5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes - 0x5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported - 0x5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported - 0x5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT - 0x5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT - 0x5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT - 0x5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT - 0x5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT - 0x5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT - 0x5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT - 0x5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT + 0x5, 0, ecx, 0, mwait_ext , MONITOR/= MWAIT extensions + 0x5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break event for MWAIT + 0x5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states + 0x5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states + 0x5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states + 0x5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states + 0x5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states + 0x5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states + 0x5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states + 0x5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states =20 # Leaf 6H -# Thermal and Power Management enumeration +# Thermal and power management =20 0x6, 0, eax, 0, dtherm , Digital = temperature sensor 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost @@ -158,24 +158,25 @@ 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event 0x6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension 0x6, 0, eax, 6, pts , Package = thermal management - 0x6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported + 0x6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers 0x6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) - 0x6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) 0x6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference 0x6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request - 0x6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported + 0x6, 0, eax, 13, hdc_base_regs , HDC base= registers 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 0x6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change 0x6, 0, eax, 16, hwp_peci_override , HWP PECI= override 0x6, 0, eax, 17, hwp_flexible , Flexible= HWP 0x6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode - 0x6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported - 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported - 0x6, 0, eax, 23, thread_director , Intel th= read director support - 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported + 0x6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP request is supported + 0x6, 0, eax, 22, hwp_ctl , IA32_HWP= _CTL MSR + 0x6, 0, eax, 23, thread_director , Intel th= read director + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) - 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support + 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting @@ -183,11 +184,11 @@ 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU hardware feedback interface index =20 # Leaf 7H -# Extended CPU features enumeration +# Extended CPU features =20 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f leaf 0x7 subleaves - 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support - 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported + 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) 0x7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 0x7, 0, ebx, 4, hle , Hardware= Lock Elision @@ -227,7 +228,7 @@ 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions 0x7, 0, ecx, 9, vaes , Vector A= ES instructions - 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bitwise algorithms 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption @@ -235,34 +236,34 @@ 0x7, 0, ecx, 16, la57 , 57-bit l= inear addresses (five-level paging) 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode 0x7, 0, ecx, 22, rdpid , RDPID in= struction - 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support + 0x7, 0, ecx, 23, key_locker , Intel ke= y locker 0x7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection 0x7, 0, ecx, 25, cldemote , CLDEMOTE= instruction 0x7, 0, ecx, 27, movdiri , MOVDIRI = instruction 0x7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction - 0x7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 29, enqcmd , Enqueue = stores (ENQCMD{,S}) 0x7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration 0x7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV - 0x7, 0, edx, 5, uintr , CPU supp= orts user interrupts + 0x7, 0, edx, 5, uintr , User int= errupts 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available - 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR + 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts - 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit 0x7, 0, edx, 14, serialize , SERIALIZ= E instruction 0x7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' 0x7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking 0x7, 0, edx, 18, pconfig , PCONFIG = instruction 0x7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs 0x7, 0, edx, 20, ibt , CET indi= rect branch tracking - 0x7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 0x7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions - 0x7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support - 0x7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support + 0x7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture + 0x7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer 0x7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) 0x7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors 0x7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR @@ -273,7 +274,7 @@ 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bfloat16 instructions 0x7, 1, eax, 6, lass , Linear a= ddress space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: leaf 0x23 is supported + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: leaf 0x23 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB @@ -282,7 +283,7 @@ 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instruction (WRMSR-non-serializing) 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations - 0x7, 1, eax, 22, hreset , History = reset support + 0x7, 1, eax, 22, hreset , HRESET (= Thread director history reset) 0x7, 1, eax, 23, avx_ifma , Integer = fused multiply add 0x7, 1, eax, 26, lam , Linear a= ddress masking 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions @@ -298,35 +299,40 @@ 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed - 0x7, 2, edx, 6, uclock_disable , UC-lock = disable is supported + 0x7, 2, edx, 6, uclock_disable , UC-lock = disable =20 # Leaf 9H -# Intel DCA (Direct Cache Access) enumeration +# Intel DCA (Direct Cache Access) =20 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS =20 # Leaf AH -# Intel PMU (Performance Monitoring Unit) enumeration +# Intel PMU (Performance Monitoring Unit) =20 0xa, 0, eax, 7:0, pmu_version , Performa= nce monitoring unit version ID - 0xa, 0, eax, 15:8, pmu_n_gcounters , Number o= f general PMU counters per logical CPU - 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth= of PMU general counters - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f leaf 0xa EBX bit vector - 0xa, 0, ebx, 0, no_core_cycle_evt , Core cyc= le event not available - 0xa, 0, ebx, 1, no_insn_retired_evt , Instruct= ion retired event not available - 0xa, 0, ebx, 2, no_refcycle_evt , Referenc= e cycles event not available - 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-refe= rence event not available - 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-miss= es event not available - 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch i= nstruction retired event not available - 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch m= ispredict retired event not available - 0xa, 0, ebx, 7, no_td_slots_evt , Topdown = slots event not available + 0xa, 0, eax, 15:8, num_counters_gp , Number o= f general-purpose PMU counters per logical CPU + 0xa, 0, eax, 23:16, bit_width_gp , Bitwidth= of PMU general-purpose counters + 0xa, 0, eax, 31:24, events_mask_len , Length o= f CPUID(0xa).EBX bit vector + 0xa, 0, ebx, 0, no_core_cycle , Core cyc= le event not available + 0xa, 0, ebx, 1, no_instruction_retired , Instruct= ion retired event not available + 0xa, 0, ebx, 2, no_reference_cycles , Referenc= e cycles event not available + 0xa, 0, ebx, 3, no_llc_reference , LLC-refe= rence event not available + 0xa, 0, ebx, 4, no_llc_misses , LLC-miss= es event not available + 0xa, 0, ebx, 5, no_br_insn_retired , Branch i= nstruction retired event not available + 0xa, 0, ebx, 6, no_br_misses_retired , Branch m= ispredict retired event not available + 0xa, 0, ebx, 7, no_topdown_slots , Topdown = slots event not available + 0xa, 0, ebx, 8, no_backend_bound , Topdown = backend bound not available + 0xa, 0, ebx, 9, no_bad_speculation , Topdown = bad speculation not available + 0xa, 0, ebx, 10, no_frontend_bound , Topdown = frontend bound not available + 0xa, 0, ebx, 11, no_retiring , Topdown = retiring not available + 0xa, 0, ebx, 12, no_lbr_inserts , LBR inse= rts not available 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-fu= nction PMU counters support bitmap - 0xa, 0, edx, 4:0, pmu_n_fcounters , Number o= f fixed PMU counters - 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth= of PMU fixed counters - 0xa, 0, edx, 15, anythread_depr , AnyThrea= d deprecation + 0xa, 0, edx, 4:0, num_counters_fixed , Number o= f fixed PMU counters + 0xa, 0, edx, 12:5, bitwidth_fixed , Bitwidth= of PMU fixed counters + 0xa, 0, edx, 15, anythread_deprecation , AnyThrea= d mode deprecation =20 # Leaf BH -# CPUs v1 extended topology enumeration +# CPU extended topology v1 =20 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit widt= h of this level (previous levels inclusive) 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical = CPUs count across all instances of this domain @@ -335,107 +341,109 @@ 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU =20 # Leaf DH -# Processor extended state enumeration - - 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87= (bit 0) supported - 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE= (bit 1) supported - 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX= (bit 2) supported - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 registers) - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 registers) - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU registers) - 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET= _U (bit 11) supported (CET user state) - 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET= _S (bit 12) supported (CET supervisor state) - 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TIL= ECONFIG (bit 17) supported (AMX can manage TILECONFIG) - 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TIL= EDATA (bit 18) supported (AMX can manage TILEDATA) - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STOR area byte size, for XCR0 enabled features +# CPU extended state + + 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 + 0xd, 0, eax, 1, xcr0_sse , XCR0.SSE + 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS: MPX BND0-BND3 registers + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR: MPX BNDCFGU/BNDSTATUS registers + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK: AVX-512 k0-k7 registers + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256: AVX-512 ZMM0->ZMM7/15 registers + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM: AVX-512 ZMM16->ZMM31 registers + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U: XSAVE PKRU registers + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET= _U: CET user state + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET= _S: CET supervisor state + 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TIL= ECONFIG: AMX can manage TILECONFIG + 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TIL= EDATA: AMX can manage TILEDATA + 0xd, 0, ebx, 31:0, xsave_sz_xcr0 , XSAVE/XR= STOR area byte size, for XCR0 enabled features 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STOR area max byte size, all CPU features - 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0= .LWP (bit 62) supported (Light-weight Profiling) + 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0= .LWP: Light-weight Profiling 0xd, 1, eax, 0, xsaveopt , XSAVEOPT= instruction 0xd, 1, eax, 1, xsavec , XSAVEC i= nstruction 0xd, 1, eax, 2, xgetbv1 , XGETBV i= nstruction with ECX =3D 1 0xd, 1, eax, 3, xsaves , XSAVES/X= RSTORS instructions (and XSS MSR) - 0xd, 1, eax, 4, xfd , Extended= feature disable support - 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE= area size, all XCR0 and XMMS features enabled - 0xd, 1, ecx, 8, xss_pt , PT state= , supported - 0xd, 1, ecx, 10, xss_pasid , PASID st= ate, supported - 0xd, 1, ecx, 11, xss_cet_u , CET user= state, supported - 0xd, 1, ecx, 12, xss_cet_p , CET supe= rvisor state, supported - 0xd, 1, ecx, 13, xss_hdc , HDC stat= e, supported - 0xd, 1, ecx, 14, xss_uintr , UINTR st= ate, supported - 0xd, 1, ecx, 15, xss_lbr , LBR stat= e, supported - 0xd, 1, ecx, 16, xss_hwp , HWP stat= e, supported - 0xd, 63:2, eax, 31:0, xsave_sz , Size of = save area for subleaf-N feature, in bytes - 0xd, 63:2, ebx, 31:0, xsave_offset , Offset o= f save area for subleaf-N feature, in bytes - 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf = N describes an XSS bit, otherwise XCR0 bit - 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature XSAVE area is 64-byte aligned + 0xd, 1, eax, 4, xfd , Extended= feature disable + 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xss , XSAVES/X= SAVEC area byte size, for XCR0|XSS enabled features + 0xd, 1, ecx, 8, xss_pt , PT state + 0xd, 1, ecx, 10, xss_pasid , PASID st= ate + 0xd, 1, ecx, 11, xss_cet_u , CET user= state + 0xd, 1, ecx, 12, xss_cet_p , CET supe= rvisor state + 0xd, 1, ecx, 13, xss_hdc , HDC state + 0xd, 1, ecx, 14, xss_uintr , UINTR st= ate + 0xd, 1, ecx, 15, xss_lbr , LBR state + 0xd, 1, ecx, 16, xss_hwp , HWP state + 0xd, 63:2, eax, 31:0, xsave_sz , Subleaf-= N feature save area size, in bytes + 0xd, 63:2, ebx, 31:0, xsave_offset , Subleaf-= N feature save area offset, in bytes + 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf = N describes an XSS bit (otherwise XCR0) + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N XSAVE area is 64-byte aligned =20 # Leaf FH # Intel RDT / AMD PQoS resource monitoring =20 - 0xf, 0, ebx, 31:0, core_rmid_max , RMID max= , within this core, all types (0-based) - 0xf, 0, edx, 1, cqm_llc , LLC QoS-= monitoring supported + 0xf, 0, ebx, 31:0, core_rmid_max , RMID max= within this core (0-based) + 0xf, 0, edx, 1, cqm_llc , LLC QoS-= monitoring 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-m= onitoring counter bitwidth (24-based) 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR M= SR bit 61 is an overflow bit + 0xf, 1, eax, 9, io_rdt_cmt , non-CPU = agent supporting Intel RDT CMT present + 0xf, 1, eax, 10, io_rdt_mbm , non-CPU = agent supporting Intel RDT MBM present 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR M= SR conversion factor to bytes 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-m= onitoring max RMID - 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS o= ccupancy monitoring supported - 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS t= otal bandwidth monitoring supported - 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS l= ocal bandwidth monitoring supported + 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS o= ccupancy monitoring + 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS t= otal bandwidth monitoring + 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS l= ocal bandwidth monitoring =20 # Leaf 10H -# Intel RDT / AMD PQoS allocation enumeration +# Intel RDT / AMD PQoS allocation =20 - 0x10, 0, ebx, 1, cat_l3 , L3 Cache= Allocation Technology supported - 0x10, 0, ebx, 2, cat_l2 , L2 Cache= Allocation Technology supported - 0x10, 0, ebx, 3, mba , Memory B= andwidth Allocation supported + 0x10, 0, ebx, 1, cat_l3 , L3 Cache= Allocation Technology + 0x10, 0, ebx, 2, cat_l2 , L2 Cache= Allocation Technology + 0x10, 0, ebx, 3, mba , Memory B= andwidth Allocation 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CA= T capacity bitmask length, minus-one notation - 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CA= T bitmap of allocation units + 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CA= T allocation units bitmap 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT= COS updates should be infrequent - 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CA= T CDP (Code and Data Prioritization) - 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CA= T non-contiguous 1s value supported - 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CA= T max COS (Class of Service) supported + 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CA= T Code and Data Prioritization + 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CA= T non-contiguous 1s value + 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CA= T max Class of Service 0x10, 3, eax, 11:0, mba_max_delay , Max MBA = throttling value; minus-one notation - 0x10, 3, ecx, 0, per_thread_mba , Per-thre= ad MBA controls are supported + 0x10, 3, ecx, 0, per_thread_mba , Per-thre= ad MBA controls 0x10, 3, ecx, 2, mba_delay_linear , Delay va= lues are linear - 0x10, 3, edx, 15:0, mba_cos_max , MBA max = Class of Service supported + 0x10, 3, edx, 15:0, mba_cos_max , MBA max = Class of Service =20 # Leaf 12H -# Intel Software Guard Extensions (SGX) enumeration - - 0x12, 0, eax, 0, sgx1 , SGX1 lea= f functions supported - 0x12, 0, eax, 1, sgx2 , SGX2 lea= f functions supported - 0x12, 0, eax, 5, enclv_leaves , ENCLV le= aves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported - 0x12, 0, eax, 6, encls_leaves , ENCLS le= aves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported - 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU le= af EVERIFYREPORT2 supported - 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS le= af EUPDATESVN supported - 0x12, 0, eax, 11, sgx_edeccssa , ENCLU le= af EDECCSSA supported - 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC= frame: reporting #PF and #GP exceptions inside enclave supported - 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC= frame: reporting #CP exceptions inside enclave supported +# Intel SGX (Software Guard Extensions) + + 0x12, 0, eax, 0, sgx1 , SGX1 lea= f functions + 0x12, 0, eax, 1, sgx2 , SGX2 lea= f functions + 0x12, 0, eax, 5, enclv_leaves , ENCLV le= aves + 0x12, 0, eax, 6, encls_leaves , ENCLS le= aves + 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU le= af EVERIFYREPORT2 + 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS le= af EUPDATESVN + 0x12, 0, eax, 11, sgx_edeccssa , ENCLU le= af EDECCSSA + 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC= frame: Enclave #PF and #GP reporting + 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC= frame: Enclave #CP reporting 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum = enclave size in non-64-bit mode (log2) 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum = enclave size in 64-bit mode (log2) - 0x12, 1, eax, 0, secs_attr_init , ATTRIBUT= ES.INIT supported (enclave initialized by EINIT) - 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUT= ES.DEBUG supported (enclave permits debugger read/write) - 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUT= ES.MODE64BIT supported (enclave runs in 64-bit mode) - 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUT= ES.PROVISIONKEY supported (provisioning key available) - 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBU= TES.EINITTOKEN_KEY supported (EINIT token key available) - 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUT= ES.CET supported (enable CET attributes) - 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUT= ES.KSS supported (Key Separation and Sharing enabled) - 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUT= ES.AEXNOTIFY supported (enclave threads may get AEX notifications - 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 (bit 0) supported - 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE (bit 1) supported - 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX (bit 2) supported - 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) - 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) - 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) - 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) - 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) - 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU registers) - 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave = XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) - 0x12, 1, ecx, 18, xfrm_tiledata , Enclave = XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) - 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf = type (dictates output layout) + 0x12, 1, eax, 0, secs_attr_init , Enclave = initialized by EINIT + 0x12, 1, eax, 1, secs_attr_debug , Enclave = permits debugger read/write + 0x12, 1, eax, 2, secs_attr_mode64bit , Enclave = runs in 64-bit mode + 0x12, 1, eax, 4, secs_attr_provisionkey , Provisio= ning key + 0x12, 1, eax, 5, secs_attr_einittoken_key, EINIT t= oken key + 0x12, 1, eax, 6, secs_attr_cet , CET attr= ibutes + 0x12, 1, eax, 7, secs_attr_kss , Key Sepa= ration and Sharing + 0x12, 1, eax, 10, secs_attr_aexnotify , Enclave = threads: AEX notifications + 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 + 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE + 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (MPX BND0-BND3 registers) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS registers) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (AVX-512 k0-k7 registers) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (AVX-512 ZMM0->ZMM7/15 registers) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (AVX-512 ZMM16->ZMM31 registers) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (XSAVE PKRU registers) + 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave = XFRM.TILECONFIG (AMX can manage TILECONFIG) + 0x12, 1, ecx, 18, xfrm_tiledata , Enclave = XFRM.TILEDATA (AMX can manage TILEDATA) + 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf = type 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base address, bits[12:31] 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base address, bits[32:51] 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC sect= ion type / property encoding @@ -443,44 +451,44 @@ 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC sect= ion size, bits[32:51] =20 # Leaf 14H -# Intel Processor Trace enumeration +# Intel Processor Trace =20 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum = leaf 0x14 subleaf 0x14, 0, ebx, 0, cr3_filtering , IA32_RTI= T_CR3_MATCH is accessible 0x14, 0, ebx, 1, psb_cyc , Configur= able PSB and cycle-accurate mode 0x14, 0, ebx, 2, ip_filtering , IP/Trace= Stop filtering; Warm-reset PT MSRs preservation 0x14, 0, ebx, 3, mtc_timing , MTC timi= ng packet; COFI-based packets suppression - 0x14, 0, ebx, 4, ptwrite , PTWRITE = support - 0x14, 0, ebx, 5, power_event_trace , Power Ev= ent Trace support - 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and = PMI preservation support - 0x14, 0, ebx, 7, event_trace , Event Tr= ace packet generation through IA32_RTIT_CTL.EventEn - 0x14, 0, ebx, 8, tnt_disable , TNT pack= et generation disable through IA32_RTIT_CTL.DisTNT - 0x14, 0, ecx, 0, topa_output , ToPA out= put scheme support + 0x14, 0, ebx, 4, ptwrite , PTWRITE = instruction + 0x14, 0, ebx, 5, power_event_trace , Power Ev= ent Trace + 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and = PMI preservation + 0x14, 0, ebx, 7, event_trace , Event Tr= ace packet generation + 0x14, 0, ebx, 8, tnt_disable , TNT pack= et generation disable + 0x14, 0, ecx, 0, topa_output , ToPA out= put scheme 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tab= les can hold multiple entries - 0x14, 0, ecx, 2, single_range_output , Single-r= ange output scheme supported - 0x14, 0, ecx, 3, trance_transport_output, Trace Tr= ansport subsystem output support + 0x14, 0, ecx, 2, single_range_output , Single-r= ange output + 0x14, 0, ecx, 3, trance_transport_output, Trace Tr= ansport subsystem output 0x14, 0, ecx, 31, ip_payloads_lip , IP paylo= ads have LIP values (CS base included) - 0x14, 1, eax, 2:0, num_address_ranges , Filterin= g number of configurable Address Ranges - 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap o= f supported MTC period encodings - 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap o= f supported Cycle Threshold encodings - 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap o= f supported Configurable PSB frequency encodings + 0x14, 1, eax, 2:0, num_address_ranges , Number o= f configurable Address Ranges + 0x14, 1, eax, 31:16, mtc_periods_bmp , MTC peri= od encodings bitmap + 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Cycle Th= reshold encodings bitmap + 0x14, 1, ebx, 31:16, psb_periods_bmp , Configur= able PSB frequency encodings bitmap =20 # Leaf 15H -# Intel TSC (Time Stamp Counter) enumeration +# Intel TSC (Time Stamp Counter) =20 0x15, 0, eax, 31:0, tsc_denominator , Denomina= tor of the TSC/'core crystal clock' ratio 0x15, 0, ebx, 31:0, tsc_numerator , Numerato= r of the TSC/'core crystal clock' ratio 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core cry= stal clock nominal frequency, in Hz =20 # Leaf 16H -# Intel processor frequency enumeration +# Intel processor frequency =20 0x16, 0, eax, 15:0, cpu_base_mhz , Processo= r base frequency, in MHz 0x16, 0, ebx, 15:0, cpu_max_mhz , Processo= r max frequency, in MHz 0x16, 0, ecx, 15:0, bus_mhz , Bus refe= rence frequency, in MHz =20 # Leaf 17H -# Intel SoC vendor attributes enumeration +# Intel SoC vendor attributes =20 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum = leaf 0x17 subleaf 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID @@ -493,32 +501,32 @@ 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor B= rand ID string, bytes subleaf_nr * (12 -> 15) =20 # Leaf 18H -# Intel determenestic address translation (TLB) parameters +# Intel deterministic address translation (TLB) parameters =20 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum = leaf 0x18 subleaf - 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-= page entries supported - 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-= page entries supported - 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-= page entries supported - 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-= page entries supported - 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this structure + 0x18, 31:0, ebx, 0, tlb_4k_page , TLB supp= orts 4KB-page entries + 0x18, 31:0, ebx, 1, tlb_2m_page , TLB supp= orts 2MB-page entries + 0x18, 31:0, ebx, 2, tlb_4m_page , TLB supp= orts 4MB-page entries + 0x18, 31:0, ebx, 3, tlb_1g_page , TLB supp= orts 1GB-page entries + 0x18, 31:0, ebx, 10:8, hard_partitioning , Partitio= ning between logical CPUs 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of = associativity 0x18, 31:0, ecx, 31:0, n_sets , Number o= f sets 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) - 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative structure - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs for logical CPUs sharing this TLB - 1 + 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs - 1 =20 # Leaf 19H -# Intel Key Locker enumeration +# Intel key locker =20 - 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key Locker restriction supported - 0x19, 0, eax, 1, kl_no_encrypt , No-encry= pt key locker restriction supported - 0x19, 0, eax, 2, kl_no_decrypt , No-decry= pt key locker restriction supported - 0x19, 0, ebx, 0, aes_keylocker , AES key = locker instructions supported - 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide= key locker instructions supported - 0x19, 0, ebx, 4, kl_msr_iwkey , Key lock= er MSRs and IWKEY backups supported - 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKE= Y NoBackup parameter supported - 0x19, 0, ecx, 1, iwkey_rand , IWKEY ra= ndomization (KeySource encoding 1) supported + 0x19, 0, eax, 0, kl_cpl0_only , CPL0-onl= y key Locker restriction + 0x19, 0, eax, 1, kl_no_encrypt , No-encry= pt key locker restriction + 0x19, 0, eax, 2, kl_no_decrypt , No-decry= pt key locker restriction + 0x19, 0, ebx, 0, aes_keylocker , AES key = locker instructions + 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide= key locker instructions + 0x19, 0, ebx, 4, kl_msr_iwkey , Key lock= er MSRs and IWKEY backups + 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKE= Y NoBackup parameter + 0x19, 0, ecx, 1, iwkey_rand , IWKEY ra= ndomization =20 # Leaf 1AH # Intel hybrid CPUs identification (e.g. Atom, Core) @@ -527,7 +535,7 @@ 0x1a, 0, eax, 31:24, core_type , This cor= e's type =20 # Leaf 1BH -# Intel PCONFIG (Platform configuration) enumeration +# Intel PCONFIG (Platform configuration) =20 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x= 1b subleaf type 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A suppor= ted PCONFIG target ID @@ -535,25 +543,18 @@ 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A suppor= ted PCONFIG target ID =20 # Leaf 1CH -# Intel LBR (Last Branch Record) enumeration - - 0x1c, 0, eax, 0, lbr_depth_8 , Max stac= k depth (number of LBR entries) =3D 8 - 0x1c, 0, eax, 1, lbr_depth_16 , Max stac= k depth (number of LBR entries) =3D 16 - 0x1c, 0, eax, 2, lbr_depth_24 , Max stac= k depth (number of LBR entries) =3D 24 - 0x1c, 0, eax, 3, lbr_depth_32 , Max stac= k depth (number of LBR entries) =3D 32 - 0x1c, 0, eax, 4, lbr_depth_40 , Max stac= k depth (number of LBR entries) =3D 40 - 0x1c, 0, eax, 5, lbr_depth_48 , Max stac= k depth (number of LBR entries) =3D 48 - 0x1c, 0, eax, 6, lbr_depth_56 , Max stac= k depth (number of LBR entries) =3D 56 - 0x1c, 0, eax, 7, lbr_depth_64 , Max stac= k depth (number of LBR entries) =3D 64 +# Intel LBR (Last Branch Record) + + 0x1c, 0, eax, 7:0, lbr_depth_mask , Max LBR = stack depth bitmask 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs may= be cleared on MWAIT C-state > C1 - 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP c= ontain Last IP, otherwise effective IP - 0x1c, 0, ebx, 0, lbr_cpl , CPL filt= ering (non-zero IA32_LBR_CTL[2:1]) supported - 0x1c, 0, ebx, 1, lbr_branch_filter , Branch f= iltering (non-zero IA32_LBR_CTL[22:16]) supported - 0x1c, 0, ebx, 2, lbr_call_stack , Call-sta= ck mode (IA32_LBR_CTL[3] =3D 1) supported - 0x1c, 0, ecx, 0, lbr_mispredict , Branch m= isprediction bit supported (IA32_LBR_x_INFO[63]) - 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LB= Rs (CPU cycles since last LBR entry) supported - 0x1c, 0, ecx, 2, lbr_branch_type , Branch t= ype field (IA32_LBR_INFO_x[59:56]) supported - 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-= events logging support; bitmap for first 4 GP (general-purpose) Counters + 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP c= ontain Last IP (otherwise effective IP) + 0x1c, 0, ebx, 0, lbr_cpl , CPL filt= ering + 0x1c, 0, ebx, 1, lbr_branch_filter , Branch f= iltering + 0x1c, 0, ebx, 2, lbr_call_stack , Call-sta= ck mode + 0x1c, 0, ecx, 0, lbr_mispredict , Branch m= isprediction bit + 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LB= Rs (CPU cycles since last LBR entry) + 0x1c, 0, ecx, 2, lbr_branch_type , Branch t= ype field + 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , PMU-even= ts logging support =20 # Leaf 1DH # Intel AMX (Advanced Matrix Extensions) tile information @@ -566,13 +567,13 @@ 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile= max number of rows =20 # Leaf 1EH -# Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration +# Intel TMUL (Tile-matrix Multiply) =20 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL uni= t maximum height, K (rows or columns) 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maximum SIMD dimension, N (column bytes) =20 # Leaf 1FH -# Intel extended topology enumeration v2 +# Intel extended topology v2 =20 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit widt= h of this level (previous levels inclusive) 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical = CPUs count across all instances of this domain @@ -581,13 +582,13 @@ 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU =20 # Leaf 20H -# Intel HRESET (History Reset) enumeration +# Intel HRESET (History Reset) =20 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x= 20 max subleaf + 1 - 0x20, 0, ebx, 0, hreset_thread_director , HRESET o= f Intel thread director is supported + 0x20, 0, ebx, 0, hreset_thread_director , Intel th= read director HRESET =20 # Leaf 21H -# Intel TD (Trust Domain) guest execution environment enumeration +# Intel TD (Trust Domain) =20 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vend= or ID string bytes 0 - 3 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vend= or ID string bytes 8 - 11 @@ -596,43 +597,64 @@ # Leaf 23H # Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) =20 - 0x23, 0, eax, 1, subleaf_1_counters , Subleaf = 1, PMU counters bitmaps, is valid - 0x23, 0, eax, 3, subleaf_3_events , Subleaf = 3, PMU events bitmaps, is valid - 0x23, 0, ebx, 0, unitmask2 , IA32_PER= FEVTSELx MSRs UnitMask2 is supported - 0x23, 0, ebx, 1, zbit , IA32_PER= FEVTSELx MSRs Z-bit is supported - 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-= purpose PMU counters bitmap - 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PM= U counters bitmap - 0x23, 3, eax, 0, core_cycles_evt , Core cyc= les event supported - 0x23, 3, eax, 1, insn_retired_evt , Instruct= ions retired event supported - 0x23, 3, eax, 2, ref_cycles_evt , Referenc= e cycles event supported - 0x23, 3, eax, 3, llc_refs_evt , Last-lev= el cache references event supported - 0x23, 3, eax, 4, llc_misses_evt , Last-lev= el cache misses event supported - 0x23, 3, eax, 5, br_insn_ret_evt , Branch i= nstruction retired event supported - 0x23, 3, eax, 6, br_mispr_evt , Branch m= ispredict retired event supported - 0x23, 3, eax, 7, td_slots_evt , Topdown = slots event supported - 0x23, 3, eax, 8, td_backend_bound_evt , Topdown = backend bound event supported - 0x23, 3, eax, 9, td_bad_spec_evt , Topdown = bad speculation event supported - 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown = frontend bound event supported - 0x23, 3, eax, 11, td_retiring_evt , Topdown = retiring event support + 0x23, 0, eax, 0, subleaf_0 , Subleaf = 0, this subleaf + 0x23, 0, eax, 1, counters_subleaf , Subleaf = 1, PMU counter bitmaps + 0x23, 0, eax, 2, acr_subleaf , Subleaf = 2, Auto Counter Reload bitmaps + 0x23, 0, eax, 3, events_subleaf , Subleaf = 3, PMU event bitmaps + 0x23, 0, eax, 4, pebs_caps_subleaf , Subleaf = 4, PEBS capabilities + 0x23, 0, eax, 5, pebs_subleaf , Subleaf = 5, Arch PEBS bitmaps + 0x23, 0, ebx, 0, unitmask2 , IA32_PER= FEVTSELx MSRs UnitMask2 bit + 0x23, 0, ebx, 1, eq , IA32_PER= FEVTSELx MSRs EQ bit + 0x23, 0, ebx, 2, rdpmc_user_disable , RDPMC us= erspace disable + 0x23, 1, eax, 31:0, gp_counters , Bitmap o= f general-purpose PMU counters + 0x23, 1, ebx, 31:0, fixed_counters , Bitmap o= f fixed PMU counters + 0x23, 2, eax, 31:0, acr_gp_reload , Bitmap o= f general-purpose counters that can be reloaded + 0x23, 2, ebx, 31:0, acr_fixed_reload , Bitmap o= f fixed counters that can be reloaded + 0x23, 2, ecx, 31:0, acr_gp_trigger , Bitmap o= f general-purpose counters that can trigger reloads + 0x23, 2, edx, 31:0, acr_fixed_trigger , Bitmap o= f fixed counters that can trigger reloads + 0x23, 3, eax, 0, core_cycles_evt , Core cyc= les event + 0x23, 3, eax, 1, insn_retired_evt , Instruct= ions retired event + 0x23, 3, eax, 2, ref_cycles_evt , Referenc= e cycles event + 0x23, 3, eax, 3, llc_refs_evt , Last-lev= el cache references event + 0x23, 3, eax, 4, llc_misses_evt , Last-lev= el cache misses event + 0x23, 3, eax, 5, br_insn_ret_evt , Branch i= nstruction retired event + 0x23, 3, eax, 6, br_mispr_evt , Branch m= ispredict retired event + 0x23, 3, eax, 7, td_slots_evt , Topdown = slots event + 0x23, 3, eax, 8, td_backend_bound_evt , Topdown = backend bound event + 0x23, 3, eax, 9, td_bad_spec_evt , Topdown = bad speculation event + 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown = frontend bound event + 0x23, 3, eax, 11, td_retiring_evt , Topdown = retiring event + 0x23, 4, ebx, 3, allow_in_record , ALLOW_IN= _RECORD bit in MSRs + 0x23, 4, ebx, 4, counters_gp , Counters= group sub-group general-purpose counters + 0x23, 4, ebx, 5, counters_fixed , Counters= group sub-group fixed-function counters + 0x23, 4, ebx, 6, counters_metrics , Counters= group sub-group performance metrics + 0x23, 4, ebx, 9:8, lbr , LBR group + 0x23, 4, ebx, 23:16, xer , XER group + 0x23, 4, ebx, 29, gpr , GPR group + 0x23, 4, ebx, 30, aux , AUX group + 0x23, 5, eax, 31:0, pebs_gp , Architec= tural PEBS general-purpose counters + 0x23, 5, ebx, 31:0, pebs_pdist_gp , Architec= tural PEBS PDIST general-purpose counters + 0x23, 5, ecx, 31:0, pebs_fixed , Architec= tural PEBS fixed counters + 0x23, 5, edx, 31:0, pebs_pdist_fixed , Architec= tural PEBS PDIST fixed counters =20 # Leaf 40000000H -# Maximum hypervisor standard leaf + hypervisor vendor string +# Maximum hypervisor leaf + hypervisor vendor string =20 -0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum = hypervisor standard leaf number +0x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum = hypervisor leaf 0x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervis= or ID string bytes 0 - 3 0x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervis= or ID string bytes 4 - 7 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervis= or ID string bytes 8 - 11 =20 # Leaf 80000000H -# Maximum extended leaf number + AMD/Transmeta CPU vendor string +# Maximum extended leaf + CPU vendor string =20 -0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended CPUID leaf supported +0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended CPUID leaf 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor I= D string bytes 8 - 11 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor I= D string bytes 4 - 7 =20 # Leaf 80000001H -# Extended CPU feature identifiers +# Extended CPU features =20 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping= ID 0x80000001, 0, eax, 7:4, e_base_model , Base pro= cessor model @@ -723,7 +745,7 @@ 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU bran= d ID string, bytes 44 - 47 =20 # Leaf 80000005H -# AMD/Transmeta L1 cache and L1 TLB enumeration +# AMD/Transmeta L1 cache and TLB =20 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages @@ -743,7 +765,7 @@ 0x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icach= e size, in KB =20 # Leaf 80000006H -# (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration +# (Mostly AMD) L2/L3 cache and TLB =20 0x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB = #entries, 2M and 4M pages 0x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB = associativity, 2M and 4M pages @@ -763,7 +785,7 @@ 0x80000006, 0, edx, 31:18, l3_size_range , L3 cache= size range =20 # Leaf 80000007H -# CPU power management (mostly AMD) and AMD RAS enumeration +# CPU power management (mostly AMD) and AMD RAS =20 0x80000007, 0, ebx, 0, overflow_recov , MCA over= flow conditions not fatal 0x80000007, 0, ebx, 1, succor , Software= containment of uncorrectable errors @@ -792,14 +814,14 @@ 0x80000008, 0, eax, 7:0, phys_addr_bits , Max phys= ical address bits 0x80000008, 0, eax, 15:8, virt_addr_bits , Max virt= ual address bits 0x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nest= ed-paging guest physical address bits -0x80000008, 0, ebx, 0, clzero , CLZERO s= upported +0x80000008, 0, ebx, 0, clzero , CLZERO i= nstruction 0x80000008, 0, ebx, 1, irperf , Instruct= ion retired counter MSR 0x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XR= STOR always saves/restores FPU error pointers -0x80000008, 0, ebx, 3, invlpgb , INVLPGB = broadcasts a TLB invalidate to all threads -0x80000008, 0, ebx, 4, rdpru , RDPRU (R= ead Processor Register at User level) supported +0x80000008, 0, ebx, 3, invlpgb , INVLPGB = broadcasts a TLB invalidate +0x80000008, 0, ebx, 4, rdpru , RDPRU (R= ead Processor Register at User level) 0x80000008, 0, ebx, 6, mba , Memory B= andwidth Allocation (AMD bit) -0x80000008, 0, ebx, 8, mcommit , MCOMMIT = (Memory commit) supported -0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD= supported +0x80000008, 0, ebx, 8, mcommit , MCOMMIT = instruction +0x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD= instruction 0x80000008, 0, ebx, 12, amd_ibpb , Indirect= Branch Prediction Barrier 0x80000008, 0, ebx, 13, wbinvd_int , Interrup= tible WBINVD/WBNOINVD 0x80000008, 0, ebx, 14, amd_ibrs , Indirect= Branch Restricted Speculation @@ -808,8 +830,8 @@ 0x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP al= ways-on preferred 0x80000008, 0, ebx, 18, ibrs_fast , IBRS is = preferred over software solution 0x80000008, 0, ebx, 19, ibrs_same_mode , IBRS pro= vides same mode protection -0x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMS= LE] bit (Long-Mode Segment Limit Enable) unsupported -0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB = RAX[5] bit can be set (nested translations) +0x80000008, 0, ebx, 20, no_efer_lmsle , Long-Mod= e Segment Limit Enable unsupported +0x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB = RAX[5] bit can be set 0x80000008, 0, ebx, 23, amd_ppin , Protecte= d Processor Inventory Number 0x80000008, 0, ebx, 24, amd_ssbd , Speculat= ive Store Bypass Disable 0x80000008, 0, ebx, 25, virt_ssbd , virtuali= zed SSBD (Speculative Store Bypass Disable) @@ -818,7 +840,7 @@ 0x80000008, 0, ebx, 28, amd_psfd , Predicti= ve Store Forward Disable 0x80000008, 0, ebx, 29, btc_no , CPU not = affected by Branch Type Confusion 0x80000008, 0, ebx, 30, ibpb_ret , IBPB cle= ars RSB/RAS too -0x80000008, 0, ebx, 31, brs , Branch S= ampling supported +0x80000008, 0, ebx, 31, brs , Branch S= ampling 0x80000008, 0, ecx, 7:0, cpu_nthreads , Number o= f physical threads - 1 0x80000008, 0, ecx, 15:12, apicid_coreid_len , Number o= f thread core ID bits (shift) in APIC ID 0x80000008, 0, ecx, 17:16, perf_tsc_len , Performa= nce time-stamp counter size @@ -826,10 +848,11 @@ 0x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU ma= x register ID (ECX input) =20 # Leaf 8000000AH -# AMD SVM (Secure Virtual Machine) enumeration +# AMD SVM (Secure Virtual Machine) =20 0x8000000a, 0, eax, 7:0, svm_version , SVM revi= sion number 0x8000000a, 0, ebx, 31:0, svm_nasid , Number o= f address space identifiers (ASID) +0x8000000a, 0, ecx, 4, pml , Page Mod= ification Logging (PML) 0x8000000a, 0, edx, 0, npt , Nested p= aging 0x8000000a, 0, edx, 1, lbrv , LBR virt= ualization 0x8000000a, 0, edx, 2, svm_lock , SVM lock @@ -856,7 +879,7 @@ 0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME address check =20 # Leaf 80000019H -# AMD TLB 1G-pages enumeration +# AMD TLB characteristics for 1GB pages =20 0x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB = #entries, 1G pages 0x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB = associativity, 1G pages @@ -868,64 +891,64 @@ 0x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB = associativity, 1G pages =20 # Leaf 8000001AH -# AMD instruction optimizations enumeration +# AMD instruction optimizations =20 0x8000001a, 0, eax, 0, fp_128 , Internal= FP/SIMD exec data path is 128-bits wide 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOV= U* better than MOVL*/MOVH* 0x8000001a, 0, eax, 2, fp_256 , internal= FP/SSE exec data path is 256-bits wide =20 # Leaf 8000001BH -# AMD IBS (Instruction-Based Sampling) enumeration - -0x8000001b, 0, eax, 0, ibs_flags_valid , IBS feat= ure flags valid -0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetc= h sampling supported -0x8000001b, 0, eax, 2, ibs_op_sampling , IBS exec= ution sampling supported -0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read= /write of op counter supported -0x8000001b, 0, eax, 4, ibs_op_count , IBS OP c= ounting mode supported -0x8000001b, 0, eax, 5, ibs_branch_target , IBS bran= ch target address reporting supported +# AMD IBS (Instruction-Based Sampling) + +0x8000001b, 0, eax, 0, ibs_flags , IBS feat= ure flags +0x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetc= h sampling +0x8000001b, 0, eax, 2, ibs_op_sampling , IBS exec= ution sampling +0x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read= /write of op counter +0x8000001b, 0, eax, 4, ibs_op_count , IBS OP c= ounting mode +0x8000001b, 0, eax, 5, ibs_branch_target , IBS bran= ch target address reporting 0x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsO= pCurCnt/IbsOpMaxCnt extend by 7 bits -0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS inva= lid RIP indication supported -0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fuse= d branch micro-op indication supported -0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetc= h Control Extended MSR (0xc001103c) supported -0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op d= ata 4 MSR supported -0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-m= iss filtering supported (Zen4+) +0x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS inva= lid RIP indication +0x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fuse= d branch micro-op indication +0x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetc= h Control Extended MSR +0x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op d= ata 4 MSR +0x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-m= iss filtering (Zen4+) =20 # Leaf 8000001CH # AMD LWP (Lightweight Profiling) =20 -0x8000001c, 0, eax, 0, os_lwp_avail , LWP is a= vailable to application programs (supported by OS) -0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction is supported by OS -0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event is supported by OS -0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event is supported by OS -0x8000001c, 0, eax, 4, os_lwp_dme , Dcache M= iss Event is supported by OS -0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event is supported by OS -0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event is supported by OS -0x8000001c, 0, eax, 29, os_lwp_cont , LWP samp= ling in continuous mode is supported by OS -0x8000001c, 0, eax, 30, os_lwp_ptsc , Performa= nce Time Stamp Counter in event records is supported by OS -0x8000001c, 0, eax, 31, os_lwp_int , Interrup= t on threshold overflow is supported by OS -0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Cont= rol Block size, in quadwords -0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP even= t record size, in bytes -0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventID value (EventID 255 not included) -0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP even= ts area offset in the LWP Control Block -0x8000001c, 0, ecx, 4:0, lwp_latency_max , Number o= f bits in cache latency counters (10 to 31) -0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache mi= ss events report the data address of the reference -0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount b= y which cache latency is rounded -0x8000001c, 0, ecx, 15:9, lwp_version , LWP impl= ementation version -0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, in units of 32 event records +0x8000001c, 0, eax, 0, os_lwp_avail , OS: LWP = is available to application programs +0x8000001c, 0, eax, 1, os_lpwval , OS: LWPV= AL instruction +0x8000001c, 0, eax, 2, os_lwp_ire , OS: Inst= ructions Retired Event +0x8000001c, 0, eax, 3, os_lwp_bre , OS: Bran= ch Retired Event +0x8000001c, 0, eax, 4, os_lwp_dme , OS: Dcac= he Miss Event +0x8000001c, 0, eax, 5, os_lwp_cnh , OS: CPU = Clocks Not Halted event +0x8000001c, 0, eax, 6, os_lwp_rnh , OS: CPU = Reference clocks Not Halted event +0x8000001c, 0, eax, 29, os_lwp_cont , OS: LWP = sampling in continuous mode +0x8000001c, 0, eax, 30, os_lwp_ptsc , OS: Perf= ormance Time Stamp Counter in event records +0x8000001c, 0, eax, 31, os_lwp_int , OS: Inte= rrupt on threshold overflow +0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , Control = Block size, in quadwords +0x8000001c, 0, ebx, 15:8, lwp_event_sz , Event re= cord size, in bytes +0x8000001c, 0, ebx, 23:16, lwp_max_events , Max Even= tID supported +0x8000001c, 0, ebx, 31:24, lwp_event_offset , Control = Block events area offset +0x8000001c, 0, ecx, 4:0, lwp_latency_max , Cache la= tency counters number of bits +0x8000001c, 0, ecx, 5, lwp_data_addr , Cache mi= ss events report data cache address +0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Cache la= tency rounding amount +0x8000001c, 0, ecx, 15:9, lwp_version , LWP vers= ion +0x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP even= t ring buffer min size, 32 event records units 0x8000001c, 0, ecx, 28, lwp_branch_predict , Branches= Retired events can be filtered -0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported -0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events can be filtered by cache level -0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events can be filtered by latency -0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in hardware -0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction is available in hardware -0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event is available in hardware -0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event is available in hardware -0x8000001c, 0, edx, 4, hw_lwp_dme , Dcache M= iss Event is available in hardware -0x8000001c, 0, edx, 5, hw_lwp_cnh , Clocks N= ot Halted event is available in hardware -0x8000001c, 0, edx, 6, hw_lwp_rnh , Referenc= e clocks Not Halted event is available in hardware -0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in hardware -0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in hardware -0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in hardware +0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) +0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events: filter by cache level +0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events: filter by latency +0x8000001c, 0, edx, 0, hw_lwp_avail , HW: LWP = available +0x8000001c, 0, edx, 1, hw_lpwval , HW: LWPV= AL available +0x8000001c, 0, edx, 2, hw_lwp_ire , HW: Inst= ructions Retired Event +0x8000001c, 0, edx, 3, hw_lwp_bre , HW: Bran= ch Retired Event +0x8000001c, 0, edx, 4, hw_lwp_dme , HW: Dcac= he Miss Event +0x8000001c, 0, edx, 5, hw_lwp_cnh , HW: Cloc= ks Not Halted event +0x8000001c, 0, edx, 6, hw_lwp_rnh , HW: Refe= rence clocks Not Halted event +0x8000001c, 0, edx, 29, hw_lwp_cont , HW: LWP = sampling in continuous mode +0x8000001c, 0, edx, 30, hw_lwp_ptsc , HW: Perf= ormance Time Stamp Counter in event records +0x8000001c, 0, edx, 31, hw_lwp_int , HW: Inte= rrupt on threshold overflow =20 # Leaf 8000001DH # AMD deterministic cache parameters @@ -943,49 +966,49 @@ 0x8000001d, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches =20 # Leaf 8000001EH -# AMD CPU topology enumeration +# AMD CPU topology =20 0x8000001e, 0, eax, 31:0, ext_apic_id , Extended= APIC ID 0x8000001e, 0, ebx, 7:0, core_id , Unique p= er-socket logical core unit ID -0x8000001e, 0, ebx, 15:8, core_nthreas , #Threads= per core (zero-based) +0x8000001e, 0, ebx, 15:8, core_nthreads , #Threads= per core (zero-based) 0x8000001e, 0, ecx, 7:0, node_id , Node (di= e) ID of invoking logical CPU 0x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes i= n invoking logical CPU's package/socket =20 # Leaf 8000001FH -# AMD encrypted memory capabilities enumeration (SME/SEV) - -0x8000001f, 0, eax, 0, sme , Secure M= emory Encryption supported -0x8000001f, 0, eax, 1, sev , Secure E= ncrypted Virtualization supported -0x8000001f, 0, eax, 2, vm_page_flush , VM Page = Flush MSR (0xc001011e) available -0x8000001f, 0, eax, 3, sev_es , SEV Encr= ypted State supported -0x8000001f, 0, eax, 4, sev_nested_paging , SEV secu= re nested paging supported -0x8000001f, 0, eax, 5, vm_permission_levels , VMPL sup= ported -0x8000001f, 0, eax, 6, rpmquery , RPMQUERY= instruction supported -0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadow stack supported -0x8000001f, 0, eax, 8, secure_tsc , Secure T= SC supported +# AMD encrypted memory capabilities (SME/SEV) + +0x8000001f, 0, eax, 0, sme , Secure M= emory Encryption +0x8000001f, 0, eax, 1, sev , Secure E= ncrypted Virtualization +0x8000001f, 0, eax, 2, vm_page_flush , VM Page = Flush MSR +0x8000001f, 0, eax, 3, sev_es , SEV Encr= ypted State +0x8000001f, 0, eax, 4, sev_nested_paging , SEV secu= re nested paging +0x8000001f, 0, eax, 5, vm_permission_levels , VMPL +0x8000001f, 0, eax, 6, rpmquery , RPMQUERY= instruction +0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadow stack +0x8000001f, 0, eax, 8, secure_tsc , Secure T= SC 0x8000001f, 0, eax, 9, v_tsc_aux , Hardware= virtualizes TSC_AUX -0x8000001f, 0, eax, 10, sme_coherent , Cache co= herency is enforced across encryption domains +0x8000001f, 0, eax, 10, sme_coherent , Cache co= herency enforcement across encryption domains 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV gues= t mandates 64-bit hypervisor 0x8000001f, 0, eax, 12, restricted_injection , Restrict= ed Injection supported 0x8000001f, 0, eax, 13, alternate_injection , Alternat= e Injection supported -0x8000001f, 0, eax, 14, debug_swap , SEV-ES: = full debug state swap is supported -0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: = Disallowing IBS use by the host is supported +0x8000001f, 0, eax, 14, debug_swap , SEV-ES: = Full debug state swap +0x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: = Disallowing IBS use by the host 0x8000001f, 0, eax, 16, virt_transparent_enc , Virtual = Transparent Encryption -0x8000001f, 0, eax, 17, vmgexit_paremeter , VmgexitP= arameter is supported in SEV_FEATURES -0x8000001f, 0, eax, 18, virt_tom_msr , Virtual = TOM MSR is supported -0x8000001f, 0, eax, 19, virt_ibs , IBS stat= e virtualization is supported for SEV-ES guests -0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA reg= ister protection is supported -0x8000001f, 0, eax, 25, smt_protection , SMT prot= ection is supported -0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000) is supported -0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMP= UPDATE/VIRT_PSMASH MSRs are supported -0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit = number used to enable memory encryption -0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduct= ion of phys address space when encryption is enabled, in bits -0x8000001f, 0, ebx, 15:12, vmpl_count , Number o= f VM permission levels (VMPL) supported -0x8000001f, 0, ecx, 31:0, enc_guests_max , Max supp= orted number of simultaneous encrypted guests +0x8000001f, 0, eax, 17, vmgexit_parameter , SEV_FEAT= URES: VmgexitParameter +0x8000001f, 0, eax, 18, virt_tom_msr , Virtual = TOM MSR +0x8000001f, 0, eax, 19, virt_ibs , SEV-ES g= uests: IBS state virtualization +0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA reg= ister protection +0x8000001f, 0, eax, 25, smt_protection , SMT prot= ection +0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR +0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMP= UPDATE/VIRT_PSMASH MSRs +0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit = number to enable memory encryption +0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduct= ion of phys address space in bits +0x8000001f, 0, ebx, 15:12, vmpl_count , Number o= f VM permission levels (VMPL) +0x8000001f, 0, ecx, 31:0, enc_guests_max , Max numb= er of simultaneous encrypted guests 0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum = ASID for SEV-enabled SEV-ES-disabled guest =20 # Leaf 80000020H -# AMD Platform QoS extended feature IDs +# AMD PQoS (Platform QoS) extended features =20 0x80000020, 0, ebx, 1, mba , Memory B= andwidth Allocation support 0x80000020, 0, ebx, 2, smba , Slow Mem= ory Bandwidth Allocation support @@ -1007,7 +1030,7 @@ 0x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty Qo= S victims to all types of memory can be tracked =20 # Leaf 80000021H -# AMD extended features enumeration 2 +# AMD extended CPU features 2 =20 0x80000021, 0, eax, 0, no_nested_data_bp , No neste= d data breakpoints 0x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to= {FS,GS,KERNEL_GS}_BASE is non-serializing @@ -1016,43 +1039,43 @@ 0x80000021, 0, eax, 6, null_sel_clr_base , Null sel= ector clears base 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore 0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS -0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not available +0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR not available 0x80000021, 0, eax, 10, fsrs , Fast Sho= rt Rep STOSB 0x80000021, 0, eax, 11, fsrc , Fast Sho= rt Rep CMPSB -0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is available +0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR 0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space -0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 is supported +0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 0x80000021, 0, eax, 18, epsf , Enhanced= Predictive Store Forwarding 0x80000021, 0, eax, 22, wl_feedback , Workload= -based heuristic feedback to OS 0x80000021, 0, eax, 24, eraps , Enhanced= Return Address Predictor Security 0x80000021, 0, eax, 27, sbpb , Selectiv= e Branch Predictor Barrier 0x80000021, 0, eax, 28, ibpb_brtype , Branch p= redictions flushed from CPU branch predictor -0x80000021, 0, eax, 29, srso_no , CPU is n= ot subject to the SRSO vulnerability -0x80000021, 0, eax, 30, srso_uk_no , CPU is n= ot vulnerable to SRSO at user-kernel boundary -0x80000021, 0, eax, 31, srso_msr_fix , Software= may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO -0x80000021, 0, ebx, 15:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, eax, 29, srso_no , No SRSO = vulnerability +0x80000021, 0, eax, 30, srso_uk_no , No SRSO = at user-kernel boundary +0x80000021, 0, eax, 31, srso_msr_fix , MSR BP_C= FG[BpSpecReduce] SRSO mitigation +0x80000021, 0, ebx, 15:0, microcode_patch_size , Microcod= e patch size, in 16-byte units 0x80000021, 0, ebx, 23:16, rap_size , Return A= ddress Predictor size =20 # Leaf 80000022H -# AMD Performance Monitoring v2 enumeration +# AMD extended performance monitoring =20 -0x80000022, 0, eax, 0, perfmon_v2 , Performa= nce monitoring v2 supported +0x80000022, 0, eax, 0, perfmon_v2 , Performa= nce monitoring v2 0x80000022, 0, eax, 1, lbr_v2 , Last Bra= nch Record v2 extensions (LBR Stack) -0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing= core performance counters / LBR Stack supported +0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing= core performance counters / LBR Stack 0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core performance counters -0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number o= f available LBR stack entries -0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number o= f available northbridge (data fabric) performance counters -0x80000022, 0, ebx, 21:16, n_pmc_umc , Number o= f available UMC performance counters +0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number o= f LBR stack entries +0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number o= f northbridge performance counters +0x80000022, 0, ebx, 21:16, n_pmc_umc , Number o= f UMC performance counters 0x80000022, 0, ecx, 31:0, active_umc_bitmask , Active U= MCs bitmask =20 # Leaf 80000023H -# AMD Secure Multi-key Encryption enumeration +# AMD multi-key encrypted memory =20 -0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK = encryption mode is supported -0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total number of available encryption keys +0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK = encryption mode +0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , Total nu= mber of available encryption keys =20 # Leaf 80000026H -# AMD extended topology enumeration v2 +# AMD extended CPU topology =20 0x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit widt= h of this level (previous levels inclusive) 0x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This cor= e has a power efficiency ranking @@ -1067,15 +1090,15 @@ 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU =20 # Leaf 80860000H -# Maximum Transmeta leaf number + CPU vendor ID string +# Maximum Transmeta leaf + CPU vendor string =20 -0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = supported Transmeta leaf number +0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = Transmeta leaf 0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 =20 # Leaf 80860001H -# Transmeta extended CPU information +# Transmeta extended CPU features =20 0x80860001, 0, eax, 3:0, stepping , Stepping= ID 0x80860001, 0, eax, 7:4, base_model , Base CPU= model ID @@ -1091,7 +1114,7 @@ 0x80860001, 0, edx, 3, lrti , LongRun = Table Interface =20 # Leaf 80860002H -# Transmeta Code Morphing Software (CMS) enumeration +# Transmeta CMS (Code Morphing Software) =20 0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revi= sion ID 0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revi= sion ID, mask component 2 @@ -1141,9 +1164,9 @@ 0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds =20 # Leaf C0000000H -# Maximum Centaur/Zhaoxin leaf number +# Maximum Centaur/Zhaoxin leaf =20 -0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum = Centaur/Zhaoxin leaf number +0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum = Centaur/Zhaoxin leaf =20 # Leaf C0000001H # Centaur/Zhaoxin extended CPU features --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA3263101B6 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cdHr7eG/Ol2o29GSKW2TlnXF9dm8s5Pzz85jiROEkzc=; b=mq0kdgRqtvH209QqAw/bLNIGkeJM1xTtPcdYBG4KJ2XaGyqdb5rYrt7CSM/w4B3um6e/N1 ORKbocC1lK5S6kSz2h8tlpPhQUFyHzIUtVXzyXXgbAQGvLlRXYM/wVZ5WbTk7IsCXZVaoe qeTCRmazpyxaWF1isbpu5hYn9R3k1T5UriKDaVdx4Af26Gqv2yfeTN73gtxYAySBHpNEfl Ggg+wl8zyU+skx4LY0S9drYmbKeqkDEfrzRVzN3rImO0sFB0l/VoqTEoidsglEt+FM5PSK NqN80F6p5gT7YX5jNZnc90AAiPG1vnZspS/GT41Sz8CECBzU4/GlZiB61H0RPA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cdHr7eG/Ol2o29GSKW2TlnXF9dm8s5Pzz85jiROEkzc=; b=AuzgfHwoSiDUivcWcd+jzefar7oC49OVb3Ru6ns1WGTKX9HSWnZE5vcpX+m57/LmN+36qD jkncFCh3bVGc8ZBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 04/90] treewide: Explicitly include the x86 CPUID headers Date: Fri, 27 Mar 2026 03:15:18 +0100 Message-ID: <20260327021645.555257-5-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Modify all CPUID call sites which implicitly include any of the CPUID headers to explicitly include them instead. For KVM's reverse_cpuid.h, just include since it references the CPUID_EAX..EDX symbols without using the CPUID APIs. Note, this allows removing the inclusion of from within next. That allows the CPUID API headers to include without introducing a circular dependency. Signed-off-by: Ahmed S. Darwish --- arch/x86/boot/compressed/pgtable_64.c | 1 + arch/x86/boot/startup/sme.c | 1 + arch/x86/coco/tdx/tdx.c | 1 + arch/x86/events/amd/core.c | 2 ++ arch/x86/events/amd/ibs.c | 1 + arch/x86/events/amd/lbr.c | 2 ++ arch/x86/events/amd/power.c | 3 +++ arch/x86/events/amd/uncore.c | 1 + arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/lbr.c | 1 + arch/x86/events/zhaoxin/core.c | 1 + arch/x86/include/asm/acrn.h | 2 ++ arch/x86/include/asm/microcode.h | 1 + arch/x86/include/asm/xen/hypervisor.h | 1 + arch/x86/kernel/apic/apic.c | 1 + arch/x86/kernel/cpu/amd.c | 1 + arch/x86/kernel/cpu/centaur.c | 1 + arch/x86/kernel/cpu/hygon.c | 1 + arch/x86/kernel/cpu/mce/core.c | 1 + arch/x86/kernel/cpu/mce/inject.c | 1 + arch/x86/kernel/cpu/microcode/amd.c | 1 + arch/x86/kernel/cpu/microcode/core.c | 1 + arch/x86/kernel/cpu/microcode/intel.c | 1 + arch/x86/kernel/cpu/mshyperv.c | 1 + arch/x86/kernel/cpu/resctrl/core.c | 1 + arch/x86/kernel/cpu/resctrl/monitor.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + arch/x86/kernel/cpu/sgx/driver.c | 3 +++ arch/x86/kernel/cpu/sgx/main.c | 3 +++ arch/x86/kernel/cpu/topology_amd.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + arch/x86/kernel/cpu/topology_ext.c | 1 + arch/x86/kernel/cpu/transmeta.c | 3 +++ arch/x86/kernel/cpu/vmware.c | 1 + arch/x86/kernel/cpu/zhaoxin.c | 1 + arch/x86/kernel/cpuid.c | 1 + arch/x86/kernel/jailhouse.c | 1 + arch/x86/kernel/kvm.c | 1 + arch/x86/kernel/paravirt.c | 1 + arch/x86/kvm/mmu/mmu.c | 1 + arch/x86/kvm/mmu/spte.c | 1 + arch/x86/kvm/reverse_cpuid.h | 2 ++ arch/x86/kvm/svm/sev.c | 1 + arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/vmx/pmu_intel.c | 1 + arch/x86/kvm/vmx/sgx.c | 1 + arch/x86/kvm/vmx/vmx.c | 1 + arch/x86/mm/pti.c | 1 + arch/x86/pci/xen.c | 1 + arch/x86/xen/enlighten_hvm.c | 1 + arch/x86/xen/pmu.c | 1 + arch/x86/xen/time.c | 1 + drivers/char/agp/efficeon-agp.c | 1 + drivers/cpufreq/longrun.c | 1 + drivers/cpufreq/powernow-k7.c | 1 + drivers/cpufreq/powernow-k8.c | 1 + drivers/cpufreq/speedstep-lib.c | 1 + drivers/firmware/efi/libstub/x86-5lvl.c | 1 + drivers/gpu/drm/gma500/mmu.c | 2 ++ drivers/hwmon/fam15h_power.c | 1 + drivers/hwmon/k10temp.c | 2 ++ drivers/hwmon/k8temp.c | 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 1 + drivers/ras/amd/fmpm.c | 1 + drivers/thermal/intel/intel_hfi.c | 1 + drivers/thermal/intel/x86_pkg_temp_thermal.c | 1 + drivers/virt/acrn/hsm.c | 1 + drivers/xen/events/events_base.c | 1 + drivers/xen/grant-table.c | 1 + drivers/xen/xenbus/xenbus_xs.c | 3 +++ 70 files changed, 86 insertions(+) diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compress= ed/pgtable_64.c index 0e89e197e112..1b2fb35704f9 100644 --- a/arch/x86/boot/compressed/pgtable_64.c +++ b/arch/x86/boot/compressed/pgtable_64.c @@ -2,6 +2,7 @@ #include "misc.h" #include #include +#include #include #include #include diff --git a/arch/x86/boot/startup/sme.c b/arch/x86/boot/startup/sme.c index b76a7c95dfe1..c07a2c381ed1 100644 --- a/arch/x86/boot/startup/sme.c +++ b/arch/x86/boot/startup/sme.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include =20 diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 7b2833705d47..168388be3a3e 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 0c92ed5f464b..d66a357f219d 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -8,8 +8,10 @@ #include #include #include + #include #include +#include #include #include =20 diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index aca89f23d2e0..1bb94f1f4334 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -15,6 +15,7 @@ #include =20 #include +#include #include =20 #include "../perf_event.h" diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index d24da377df77..5b437dc8e4ce 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -1,5 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include + +#include #include #include =20 diff --git a/arch/x86/events/amd/power.c b/arch/x86/events/amd/power.c index dad42790cf7d..744dffa42dee 100644 --- a/arch/x86/events/amd/power.c +++ b/arch/x86/events/amd/power.c @@ -10,8 +10,11 @@ #include #include #include + #include +#include #include + #include "../perf_event.h" =20 /* Event code: LSB 8 bits, passed in attr->config any other bit is reserve= d. */ diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index dd956cfcadef..05cff39968ec 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -16,6 +16,7 @@ #include =20 #include +#include #include =20 #define NUM_COUNTERS_NB 4 diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 36c68210d4d2..d1107129d5ad 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 72f2adcda7c6..cae2e02fe6cc 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -4,6 +4,7 @@ #include =20 #include +#include #include #include =20 diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 4bdfcf091200..6ed644fe89aa 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -13,6 +13,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h index fab11192c60a..db42b477c41d 100644 --- a/arch/x86/include/asm/acrn.h +++ b/arch/x86/include/asm/acrn.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_ACRN_H #define _ASM_X86_ACRN_H =20 +#include + /* * This CPUID returns feature bitmaps in EAX. * Guest VM uses this to detect the appropriate feature bit. diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microc= ode.h index 8b41f26f003b..645e65ac1586 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -3,6 +3,7 @@ #define _ASM_X86_MICROCODE_H =20 #include +#include =20 struct cpu_signature { unsigned int sig; diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/x= en/hypervisor.h index c2fc7869b996..7c596cebfb78 100644 --- a/arch/x86/include/asm/xen/hypervisor.h +++ b/arch/x86/include/asm/xen/hypervisor.h @@ -37,6 +37,7 @@ extern struct shared_info *HYPERVISOR_shared_info; extern struct start_info *xen_start_info; =20 #include +#include #include =20 #define XEN_SIGNATURE "XenVMMXenVMM" diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 961714e6adae..28fe5f5672da 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -64,6 +64,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 09de584e4c8f..224420f53ea9 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 81695da9c524..681d2da49341 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 7f95a74e4c65..3e8891a9caf2 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 8dd424ac5de8..f6499132cba6 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -49,6 +49,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index d02c4f556cd0..42c82c14c48a 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -26,6 +26,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/micr= ocode/amd.c index e533881284a1..874b5b70c0d2 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -34,6 +34,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 651202e6fefb..56d791aeac4e 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -34,6 +34,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/mi= crocode/intel.c index 8744f3adc2a0..f0cae188b584 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -25,6 +25,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 9befdc557d9e..45705f8e64a4 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 7667cf7c4e94..9c01d2562b7a 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -22,6 +22,7 @@ #include =20 #include +#include #include #include #include "internal.h" diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index 9bd87bae4983..145be7abee52 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -21,6 +21,7 @@ #include =20 #include +#include #include =20 #include "internal.h" diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 42c7eac0c387..226a4796d227 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "cpu.h" diff --git a/arch/x86/kernel/cpu/sgx/driver.c b/arch/x86/kernel/cpu/sgx/dri= ver.c index 473619741bc4..9268289cd9f9 100644 --- a/arch/x86/kernel/cpu/sgx/driver.c +++ b/arch/x86/kernel/cpu/sgx/driver.c @@ -6,7 +6,10 @@ #include #include #include + +#include #include + #include "driver.h" #include "encl.h" =20 diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 38b7fd2f63be..4505f808af5e 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -15,9 +15,12 @@ #include #include #include + +#include #include #include #include + #include "driver.h" #include "encl.h" #include "encls.h" diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 6ac097e13106..cc103c85b96d 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -2,6 +2,7 @@ #include =20 #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/topology_common.c b/arch/x86/kernel/cpu/to= pology_common.c index 71625795d711..fccfac4cd5a6 100644 --- a/arch/x86/kernel/cpu/topology_common.c +++ b/arch/x86/kernel/cpu/topology_common.c @@ -6,6 +6,7 @@ #include #include #include +#include #include =20 #include "cpu.h" diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topol= ogy_ext.c index 467b0326bf1a..eb915c73895f 100644 --- a/arch/x86/kernel/cpu/topology_ext.c +++ b/arch/x86/kernel/cpu/topology_ext.c @@ -2,6 +2,7 @@ #include =20 #include +#include #include #include =20 diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmet= a.c index 42c939827621..1fdcd69c625c 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -3,8 +3,11 @@ #include #include #include + #include +#include #include + #include "cpu.h" =20 static void early_init_transmeta(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c index a3e6936839b1..121512951f10 100644 --- a/arch/x86/kernel/cpu/vmware.c +++ b/arch/x86/kernel/cpu/vmware.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 031379b7d4fa..761aef5590ac 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -4,6 +4,7 @@ =20 #include #include +#include #include =20 #include "cpu.h" diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index dae436253de4..cbd04b677fd1 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -37,6 +37,7 @@ #include #include =20 +#include #include #include =20 diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index 9e9a591a5fec..f58ce9220e0f 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c index 3bc062363814..f1240d5605b2 100644 --- a/arch/x86/kernel/kvm.c +++ b/arch/x86/kernel/kvm.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index a6ed52cae003..22c7ba9a1bcc 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c index b922a8b00057..f134fc70cc17 100644 --- a/arch/x86/kvm/mmu/mmu.c +++ b/arch/x86/kvm/mmu/mmu.c @@ -52,6 +52,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kvm/mmu/spte.c b/arch/x86/kvm/mmu/spte.c index 85a0473809b0..4e753386c8d4 100644 --- a/arch/x86/kvm/mmu/spte.c +++ b/arch/x86/kvm/mmu/spte.c @@ -15,6 +15,7 @@ #include "x86.h" #include "spte.h" =20 +#include #include #include #include diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index 657f5f743ed9..2ad25781cefb 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -3,8 +3,10 @@ #define ARCH_X86_KVM_REVERSE_CPUID_H =20 #include + #include #include +#include =20 /* * Define a KVM-only feature flag. diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 3f9c1aa39a0a..9da85c9bec05 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -23,6 +23,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index e6477affac9a..9d3b8df7b658 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 27eb76e6b6a0..74e0b01185b8 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "x86.h" #include "cpuid.h" #include "lapic.h" diff --git a/arch/x86/kvm/vmx/sgx.c b/arch/x86/kvm/vmx/sgx.c index df1d0cf76947..29a1f8e3be60 100644 --- a/arch/x86/kvm/vmx/sgx.c +++ b/arch/x86/kvm/vmx/sgx.c @@ -2,6 +2,7 @@ /* Copyright(c) 2021 Intel Corporation. */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 +#include #include #include =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 8b24e682535b..54ac6e26dc57 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index f7546e9e8e89..4bc0150b1f70 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -31,6 +31,7 @@ =20 #include #include +#include #include #include #include diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c index 6818515a501b..550c631bc77f 100644 --- a/arch/x86/pci/xen.c +++ b/arch/x86/pci/xen.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #include =20 diff --git a/arch/x86/xen/enlighten_hvm.c b/arch/x86/xen/enlighten_hvm.c index fe57ff85d004..bd57259a02e6 100644 --- a/arch/x86/xen/enlighten_hvm.c +++ b/arch/x86/xen/enlighten_hvm.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include =20 diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 8f89ce0b67e3..5f50a3ee08f5 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -2,6 +2,7 @@ #include #include =20 +#include #include #include #include diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c index 6f9f665bb7ae..d62c14334b35 100644 --- a/arch/x86/xen/time.c +++ b/arch/x86/xen/time.c @@ -18,6 +18,7 @@ #include #include =20 +#include #include #include #include diff --git a/drivers/char/agp/efficeon-agp.c b/drivers/char/agp/efficeon-ag= p.c index 0d25bbdc7e6a..4d0b7d7c0aad 100644 --- a/drivers/char/agp/efficeon-agp.c +++ b/drivers/char/agp/efficeon-agp.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "agp.h" #include "intel-agp.h" =20 diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c index 1caaec7c280b..f3aaca0496a4 100644 --- a/drivers/cpufreq/longrun.c +++ b/drivers/cpufreq/longrun.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 static struct cpufreq_driver longrun_driver; =20 diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c index 6b7caf4ae20d..6a930d7e6a5c 100644 --- a/drivers/cpufreq/powernow-k7.c +++ b/drivers/cpufreq/powernow-k7.c @@ -29,6 +29,7 @@ #include /* Needed for recalibrate_cpu_khz() */ #include #include +#include =20 #ifdef CONFIG_X86_POWERNOW_K7_ACPI #include diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c index 4d77eef53fe0..2b791f1ec51b 100644 --- a/drivers/cpufreq/powernow-k8.c +++ b/drivers/cpufreq/powernow-k8.c @@ -39,6 +39,7 @@ =20 #include #include +#include =20 #include #include diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-li= b.c index f8b42e981635..973716c1c29c 100644 --- a/drivers/cpufreq/speedstep-lib.c +++ b/drivers/cpufreq/speedstep-lib.c @@ -15,6 +15,7 @@ #include #include =20 +#include #include #include #include "speedstep-lib.h" diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi= /libstub/x86-5lvl.c index c00d0ae7ed5d..c3da05c0df8b 100644 --- a/drivers/firmware/efi/libstub/x86-5lvl.c +++ b/drivers/firmware/efi/libstub/x86-5lvl.c @@ -2,6 +2,7 @@ #include =20 #include +#include #include #include =20 diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c index 6b6b44e426cf..4fbc22a59ac7 100644 --- a/drivers/gpu/drm/gma500/mmu.c +++ b/drivers/gpu/drm/gma500/mmu.c @@ -7,6 +7,8 @@ #include #include =20 +#include + #include "mmu.h" #include "psb_drv.h" #include "psb_reg.h" diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c index efcbea2d070e..ad4ed4162b57 100644 --- a/drivers/hwmon/fam15h_power.c +++ b/drivers/hwmon/fam15h_power.c @@ -19,6 +19,7 @@ #include #include #include +#include #include =20 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor"); diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index a5d8f45b7881..de0760dc597d 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -20,7 +20,9 @@ #include #include #include + #include +#include #include =20 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor"); diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c index 2b80ac410cd1..53241164570e 100644 --- a/drivers/hwmon/k8temp.c +++ b/drivers/hwmon/k8temp.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #define TEMP_FROM_REG(val) (((((val) >> 16) & 0xff) - 49) * 1000) #define REG_TEMP 0xe4 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/ne= t/ethernet/stmicro/stmmac/dwmac-intel.c index 92d77b0c2f54..abed30a5efbb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -6,6 +6,7 @@ #include #include #include +#include #include "dwmac-intel.h" #include "dwmac4.h" #include "stmmac.h" diff --git a/drivers/ras/amd/fmpm.c b/drivers/ras/amd/fmpm.c index 34ef75af31cb..4ccaaf7b70bf 100644 --- a/drivers/ras/amd/fmpm.c +++ b/drivers/ras/amd/fmpm.c @@ -52,6 +52,7 @@ #include =20 #include +#include #include =20 #include "../debugfs.h" diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/inte= l_hfi.c index 1a1a95b39405..640df74f1a77 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -41,6 +41,7 @@ #include #include =20 +#include #include =20 #include "intel_hfi.h" diff --git a/drivers/thermal/intel/x86_pkg_temp_thermal.c b/drivers/thermal= /intel/x86_pkg_temp_thermal.c index 540109761f0a..d1dd2f5910e4 100644 --- a/drivers/thermal/intel/x86_pkg_temp_thermal.c +++ b/drivers/thermal/intel/x86_pkg_temp_thermal.c @@ -20,6 +20,7 @@ #include =20 #include +#include #include =20 #include "thermal_interrupt.h" diff --git a/drivers/virt/acrn/hsm.c b/drivers/virt/acrn/hsm.c index 74f2086fa59f..f170ff4617fd 100644 --- a/drivers/virt/acrn/hsm.c +++ b/drivers/virt/acrn/hsm.c @@ -16,6 +16,7 @@ #include =20 #include +#include #include =20 #include "acrn_drv.h" diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_b= ase.c index bc9a41662efc..6ea945508a89 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -40,6 +40,7 @@ #include =20 #ifdef CONFIG_X86 +#include #include #include #include diff --git a/drivers/xen/grant-table.c b/drivers/xen/grant-table.c index 97e27f754d39..9a62023966d1 100644 --- a/drivers/xen/grant-table.c +++ b/drivers/xen/grant-table.c @@ -59,6 +59,7 @@ #include #include #ifdef CONFIG_X86 +#include #include #endif #include diff --git a/drivers/xen/xenbus/xenbus_xs.c b/drivers/xen/xenbus/xenbus_xs.c index 82b0a34ded70..c202e7c553a6 100644 --- a/drivers/xen/xenbus/xenbus_xs.c +++ b/drivers/xen/xenbus/xenbus_xs.c @@ -47,6 +47,9 @@ #include #include #include +#ifdef CONFIG_X86 +#include +#endif #include #include #include "xenbus.h" --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4C12F329C6D for ; Fri, 27 Mar 2026 02:17:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577863; cv=none; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 05/90] x86/cpu: : Do not include the CPUID API header Date: Fri, 27 Mar 2026 03:15:19 +0100 Message-ID: <20260327021645.555257-6-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" includes but it does not need it. Remove the include. This allows the CPUID APIs header to include at a later step without introducing a circular dependency. Note, all call sites which implicitly included the CPUID API through have been modified to explicitly include the CPUID APIs instead. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/processor.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index a24c7805acdb..bea05fea5729 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -16,7 +16,6 @@ struct vm86; #include #include #include -#include #include #include #include --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7A7C32A3F3 for ; Fri, 27 Mar 2026 02:17:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577868; cv=none; b=f6656rF+OIRY+DOKN0Xo3/SzLfoswVPo0Bo9hC2h0iIKOmodYMpaVNZd+I4pCcKUxbAoZSIbJLeh/RntCbyZ0sDKEmsQuJaHq4NLyzn4B9ijyDy2ElUoT0S5UDTe1Y70yXDURh8QmuQ4fxNW5bZ9LNmEyXdyOQf8JPUerr7S6do= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577868; c=relaxed/simple; bh=EsBHQYK6+5al2u+eK+rXHdnfCVMU0JWkDjtPoocw2Ac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CpvOULwFJny0SveHAqqD0nF/nCAV4pindpwyigt1ZDT1uWzPueUzZ0zfaWlhbpQ75Ri+EAcUJm5PXrG0Iq/KAOhuxTpirg/IJuus4/GMgZKDHtlrfheYI/tDJBwBx3Rw4EKZ9eWeHX8FxMMAKoQNETIFk35Knuny+1lyb0ClFJk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=zaEE313e; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=8NWbH8RP; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="zaEE313e"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="8NWbH8RP" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577865; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9tjJwbIpAvJLZM6ERmV+GrAOiDL8jHN5NYfWYPm7crU=; b=zaEE313eO71lF5IJuAEz9461isge04JNn3JPt2NVFPAClpJ7vYgdXiklzhR41vscwZgBX0 dERaZ7j0hWuzofQROoArN0jQhTRbQyvSOGaqT8+zFi50gKvjS1kHp/QSm1B7RRSo0KpG1S ly3YgSOwW22dHO84nkDVCB73l0z4RYejkjVqvg46DdL/bL0HXeE4nOgn8XwrUpYHdzm9W+ dwBDtKyyYS9HbtRdXlQL43PNfghPV7XeHLRclYZ4jBVKRa1mwHOOGhXH8PLCTDGXWZKrR+ 7CFZaBx1wznWS8ZsP8Ds8OmaaekER9ysA/UOkdx06lqIXYJhnOhIxfl7TROJoA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577865; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9tjJwbIpAvJLZM6ERmV+GrAOiDL8jHN5NYfWYPm7crU=; b=8NWbH8RP3UcuVBkTDob1LU4ozPv5/6e29ZSLS4mezLDZ6D24FXU+N1QMJbWRHezGgdSprA JAbxBxGsxmR7RRAg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 06/90] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Date: Fri, 27 Mar 2026 03:15:20 +0100 Message-ID: <20260327021645.555257-7-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A new CPUID model will be added where its APIs will be designated as the official CPUID API. Free the cpuid_leaf() and cpuid_subleaf() function names for that API. Rename them accordingly to cpuid_read() and cpuid_read_subleaf(). For kernel/cpuid.c, rename its local file operations read function from cpuid_read() to cpuid_read_f() so that it does not conflict with the new API. No functional change. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/kernel/cpu/topology_amd.c | 2 +- arch/x86/kernel/cpu/topology_ext.c | 2 +- arch/x86/kernel/cpuid.c | 5 ++--- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 44fa82e1267c..2b9750cc8a75 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -131,12 +131,12 @@ static inline void __cpuid_read(u32 leaf, u32 subleaf= , u32 *regs) __cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUI= D_EDX); } =20 -#define cpuid_subleaf(leaf, subleaf, regs) { \ +#define cpuid_read_subleaf(leaf, subleaf, regs) { \ static_assert(sizeof(*(regs)) =3D=3D 16); \ __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ } =20 -#define cpuid_leaf(leaf, regs) { \ +#define cpuid_read(leaf, regs) { \ static_assert(sizeof(*(regs)) =3D=3D 16); \ __cpuid_read(leaf, 0, (u32 *)(regs)); \ } @@ -228,7 +228,7 @@ static inline u32 cpuid_base_hypervisor(const char *sig= , u32 leaves) */ static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) { - cpuid_leaf(0x2, regs); + cpuid_read(0x2, regs); =20 /* * All Intel CPUs must report an iteration count of 1. In case diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index cc103c85b96d..da080d732e10 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -80,7 +80,7 @@ static bool parse_8000_001e(struct topo_scan *tscan) if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) return false; =20 - cpuid_leaf(0x8000001e, &leaf); + cpuid_read(0x8000001e, &leaf); =20 /* * If leaf 0xb/0x26 is available, then the APIC ID and the domain diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topol= ogy_ext.c index eb915c73895f..60dfaa02ffd0 100644 --- a/arch/x86/kernel/cpu/topology_ext.c +++ b/arch/x86/kernel/cpu/topology_ext.c @@ -71,7 +71,7 @@ static inline bool topo_subleaf(struct topo_scan *tscan, = u32 leaf, u32 subleaf, default: return false; } =20 - cpuid_subleaf(leaf, subleaf, &sl); + cpuid_read_subleaf(leaf, subleaf, &sl); =20 if (!sl.num_processors || sl.type =3D=3D INVALID_TYPE) return false; diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index cbd04b677fd1..b55fe9c7359a 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -59,8 +59,7 @@ static void cpuid_smp_cpuid(void *cmd_block) complete(&cmd->done); } =20 -static ssize_t cpuid_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static ssize_t cpuid_read_f(struct file *file, char __user *buf, size_t co= unt, loff_t *ppos) { char __user *tmp =3D buf; struct cpuid_regs_done cmd; @@ -120,7 +119,7 @@ static int cpuid_open(struct inode *inode, struct file = *file) static const struct file_operations cpuid_fops =3D { .owner =3D THIS_MODULE, .llseek =3D no_seek_end_llseek, - .read =3D cpuid_read, + .read =3D cpuid_read_f, .open =3D cpuid_open, }; =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E3EE33555B for ; Fri, 27 Mar 2026 02:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577876; cv=none; b=PGJfKtSKKT2RucCDaz45R+eh2DTrshnOoqa4nR58UxTH40dnGILhIFUTisGe9N/CwC+1BTrdtmL1ahvGuGZbVUlFux/JWQlRRA2oi6TIMfJu1NYFZ8xkyJnG2GaCTZY5iLRAnpax47k/JyvtcFGO5oQqWK9t1ZeSHtx6LoKXKRE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577876; c=relaxed/simple; bh=qv/D6QC0520t/uC9clDJHlnVW8jGrxH/Fse/dd3kzGk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OMK0jxNgCovjKot9oCimUQc75uSSZdZQbPhroTLV2w6pCdFE1sXSix7fKv4NhalGRSUQM97Ko/3UDPZRtEIwIc7zNOKQMkkU/JyRJUmQmxtdpvbSev6kocU/AE18T8nz1KvVr7WJwkYWg2fDUP7WHJmVje7FhlpsxM+KZl6GWP4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kbqpGAqW; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=6OidD+t7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kbqpGAqW"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="6OidD+t7" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 07/90] x86/cpuid: Introduce Date: Fri, 27 Mar 2026 03:15:21 +0100 Message-ID: <20260327021645.555257-8-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To centralize all CPUID access across the x86 subsystem, introduce . It is generated by the x86-cpuid-db project and provides C99 bitfield listings for all publicly known CPUID leaves. Add the header to MAINTAINERS "x86 CPUID database" entry as well. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.0/CHANGELOG.r= st --- MAINTAINERS | 1 + arch/x86/include/asm/cpuid/leaf_types.h | 2350 +++++++++++++++++++++++ 2 files changed, 2351 insertions(+) create mode 100644 arch/x86/include/asm/cpuid/leaf_types.h diff --git a/MAINTAINERS b/MAINTAINERS index 7d10988cbc62..8cb3b9fcface 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28564,6 +28564,7 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org +F: arch/x86/include/asm/cpuid/leaf_types.h F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm= /cpuid/leaf_types.h new file mode 100644 index 000000000000..5b0008e455e2 --- /dev/null +++ b/arch/x86/include/asm/cpuid/leaf_types.h @@ -0,0 +1,2350 @@ +/* SPDX-License-Identifier: MIT */ +/* Generator: x86-cpuid-db v3.0 */ + +/* + * Auto-generated file. + * Please submit all updates and bugfixes to https://x86-cpuid.org + */ + +#ifndef _ASM_X86_CPUID_LEAF_TYPES +#define _ASM_X86_CPUID_LEAF_TYPES + +#include + +/* + * Leaf 0x0 + * Maximum standard leaf + CPU vendor string + */ + +struct leaf_0x0_0 { + // eax + u32 max_std_leaf : 32; // Highest standard CPUID leaf + // ebx + u32 cpu_vendorid_0 : 32; // CPU vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x1 + * CPU FMS (Family/Model/Stepping) + standard feature flags + */ + +struct leaf_0x1_0 { + // eax + u32 stepping : 4, // Stepping ID + base_model : 4, // Base CPU model ID + base_family_id : 4, // Base CPU family ID + cpu_type : 2, // CPU type + : 2, // Reserved + ext_model : 4, // Extended CPU model ID + ext_family : 8, // Extended CPU family ID + : 4; // Reserved + // ebx + u32 brand_id : 8, // Brand index + clflush_size : 8, // CLFLUSH instruction cache line size + n_logical_cpu : 8, // Logical CPU count + local_apic_id : 8; // Initial local APIC physical ID + // ecx + u32 sse3 : 1, // Streaming SIMD Extensions 3 (SSE3) + pclmulqdq : 1, // PCLMULQDQ instruction support + dtes64 : 1, // 64-bit DS save area + monitor : 1, // MONITOR/MWAIT support + dscpl : 1, // CPL Qualified Debug Store + vmx : 1, // Virtual Machine Extensions + smx : 1, // Safer Mode Extensions + est : 1, // Enhanced Intel SpeedStep + tm2 : 1, // Thermal Monitor 2 + ssse3 : 1, // Supplemental SSE3 + cntxt_id : 1, // L1 Context ID + sdbg : 1, // Silicon Debug + fma : 1, // FMA extensions using YMM state + cx16 : 1, // CMPXCHG16B instruction support + xtpr_update : 1, // xTPR Update Control + pdcm : 1, // Perfmon and Debug Capability + : 1, // Reserved + pcid : 1, // Process-context identifiers + dca : 1, // Direct Cache Access + sse4_1 : 1, // SSE4.1 + sse4_2 : 1, // SSE4.2 + x2apic : 1, // X2APIC support + movbe : 1, // MOVBE instruction support + popcnt : 1, // POPCNT instruction support + tsc_deadline_timer : 1, // APIC timer one-shot operation + aes : 1, // AES instructions + xsave : 1, // XSAVE (and related instructions) support + osxsave : 1, // XSAVE (and related instructions) are enabled by OS + avx : 1, // AVX instructions support + f16c : 1, // Half-precision floating-point conversion support + rdrand : 1, // RDRAND instruction support + guest_status : 1; // System is running as guest; (para-)virtualized s= ystem + // edx + u32 fpu : 1, // Floating-Point Unit on-chip (x87) + vme : 1, // Virtual-8086 Mode Extensions + de : 1, // Debugging Extensions + pse : 1, // Page Size Extension + tsc : 1, // Time Stamp Counter + msr : 1, // Model-Specific Registers (RDMSR and WRMSR support) + pae : 1, // Physical Address Extensions + mce : 1, // Machine Check Exception + cx8 : 1, // CMPXCHG8B instruction + apic : 1, // APIC on-chip + : 1, // Reserved + sep : 1, // SYSENTER, SYSEXIT, and associated MSRs + mtrr : 1, // Memory Type Range Registers + pge : 1, // Page Global Extensions + mca : 1, // Machine Check Architecture + cmov : 1, // Conditional Move Instruction + pat : 1, // Page Attribute Table + pse36 : 1, // Page Size Extension (36-bit) + psn : 1, // Processor Serial Number + clflush : 1, // CLFLUSH instruction + : 1, // Reserved + ds : 1, // Debug Store + acpi : 1, // Thermal monitor and clock control + mmx : 1, // MMX instructions + fxsr : 1, // FXSAVE and FXRSTOR instructions + sse : 1, // SSE instructions + sse2 : 1, // SSE2 instructions + selfsnoop : 1, // Self Snoop + htt : 1, // Hyper-threading + tm : 1, // Thermal Monitor + ia64 : 1, // Legacy IA-64 (Itanium) support bit, now reserved + pbe : 1; // Pending Break Enable +}; + +/* + * Leaf 0x2 + * Intel cache and TLB information one-byte descriptors + */ + +struct leaf_0x2_0 { + // eax + u32 iteration_count : 8, // Number of times this leaf must be queried + desc1 : 8, // Descriptor #1 + desc2 : 8, // Descriptor #2 + desc3 : 7, // Descriptor #3 + eax_invalid : 1; // Descriptors 1-3 are invalid if set + // ebx + u32 desc4 : 8, // Descriptor #4 + desc5 : 8, // Descriptor #5 + desc6 : 8, // Descriptor #6 + desc7 : 7, // Descriptor #7 + ebx_invalid : 1; // Descriptors 4-7 are invalid if set + // ecx + u32 desc8 : 8, // Descriptor #8 + desc9 : 8, // Descriptor #9 + desc10 : 8, // Descriptor #10 + desc11 : 7, // Descriptor #11 + ecx_invalid : 1; // Descriptors 8-11 are invalid if set + // edx + u32 desc12 : 8, // Descriptor #12 + desc13 : 8, // Descriptor #13 + desc14 : 8, // Descriptor #14 + desc15 : 7, // Descriptor #15 + edx_invalid : 1; // Descriptors 12-15 are invalid if set +}; + +/* + * Leaf 0x4 + * Intel deterministic cache parameters + */ + +struct leaf_0x4_n { + // eax + u32 cache_type : 5, // Cache type field + cache_level : 3, // Cache level (1-based) + cache_self_init : 1, // Self-initializing cache level + fully_associative : 1, // Fully-associative cache + : 4, // Reserved + num_threads_sharing : 12, // Number logical CPUs sharing this cache + num_cores_on_die : 6; // Number of cores in the physical package + // ebx + u32 cache_linesize : 12, // System coherency line size (0-based) + cache_npartitions : 10, // Physical line partitions (0-based) + cache_nways : 10; // Ways of associativity (0-based) + // ecx + u32 cache_nsets : 31, // Cache number of sets (0-based) + : 1; // Reserved + // edx + u32 wbinvd_rll_no_guarantee : 1, // WBINVD/INVD not guaranteed for Remo= te Lower-Level caches + ll_inclusive : 1, // Cache is inclusive of Lower-Level caches + complex_indexing : 1, // Not a direct-mapped cache (complex function) + : 29; // Reserved +}; + +#define LEAF_0x4_SUBLEAF_N_FIRST 0 +#define LEAF_0x4_SUBLEAF_N_LAST 31 + +/* + * Leaf 0x5 + * MONITOR/MWAIT instructions + */ + +struct leaf_0x5_0 { + // eax + u32 min_mon_size : 16, // Smallest monitor-line size, in bytes + : 16; // Reserved + // ebx + u32 max_mon_size : 16, // Largest monitor-line size, in bytes + : 16; // Reserved + // ecx + u32 mwait_ext : 1, // MONITOR/MWAIT extensions + mwait_irq_break : 1, // Interrupts as a break event for MWAIT + : 30; // Reserved + // edx + u32 n_c0_substates : 4, // Number of C0 sub C-states + n_c1_substates : 4, // Number of C1 sub C-states + n_c2_substates : 4, // Number of C2 sub C-states + n_c3_substates : 4, // Number of C3 sub C-states + n_c4_substates : 4, // Number of C4 sub C-states + n_c5_substates : 4, // Number of C5 sub C-states + n_c6_substates : 4, // Number of C6 sub C-states + n_c7_substates : 4; // Number of C7 sub C-states +}; + +/* + * Leaf 0x6 + * Thermal and power management + */ + +struct leaf_0x6_0 { + // eax + u32 digital_temp : 1, // Digital temperature sensor + turbo_boost : 1, // Intel Turbo Boost + lapic_timer_always_on : 1, // Always-Running APIC Timer (not affected = by p-state) + : 1, // Reserved + power_limit_event : 1, // Power Limit Notification (PLN) event + ecmd : 1, // Clock modulation duty cycle extension + package_thermal : 1, // Package thermal management + hwp_base_regs : 1, // HWP (Hardware P-states) base registers + hwp_notify : 1, // HWP notification (IA32_HWP_INTERRUPT MSR) + hwp_activity_window : 1, // HWP activity window (IA32_HWP_REQUEST[bits= 41:32]) + hwp_energy_perf_pr : 1, // HWP Energy Performance Preference + hwp_package_req : 1, // HWP Package Level Request + : 1, // Reserved + hdc_base_regs : 1, // HDC base registers + turbo_boost_3_0 : 1, // Intel Turbo Boost Max 3.0 + hwp_capabilities : 1, // HWP Highest Performance change + hwp_peci_override : 1, // HWP PECI override + hwp_flexible : 1, // Flexible HWP + hwp_fast : 1, // IA32_HWP_REQUEST MSR fast access mode + hw_feedback : 1, // HW_FEEDBACK MSRs + hwp_ignore_idle : 1, // Ignoring idle logical CPU HWP request is supp= orted + : 1, // Reserved + hwp_ctl : 1, // IA32_HWP_CTL MSR + thread_director : 1, // Intel thread director + therm_interrupt_bit25 : 1, // IA32_THERM_INTERRUPT MSR bit 25 + : 7; // Reserved + // ebx + u32 n_therm_thresholds : 4, // Digital thermometer thresholds + : 28; // Reserved + // ecx + u32 aperf_mperf : 1, // MPERF/APERF MSRs (effective frequency interfac= e) + : 2, // Reserved + energy_perf_bias : 1, // IA32_ENERGY_PERF_BIAS MSR + : 4, // Reserved + thrd_director_nclasses : 8, // Number of classes, Intel thread director + : 16; // Reserved + // edx + u32 perfcap_reporting : 1, // Performance capability reporting + encap_reporting : 1, // Energy efficiency capability reporting + : 6, // Reserved + feedback_sz : 4, // Feedback interface structure size, in 4K pages + : 4, // Reserved + this_lcpu_hwfdbk_idx : 16; // This logical CPU hardware feedback interf= ace index +}; + +/* + * Leaf 0x7 + * Extended CPU features + */ + +struct leaf_0x7_0 { + // eax + u32 leaf7_n_subleaves : 32; // Number of leaf 0x7 subleaves + // ebx + u32 fsgsbase : 1, // FSBASE/GSBASE read/write + tsc_adjust : 1, // IA32_TSC_ADJUST MSR + sgx : 1, // Intel SGX (Software Guard Extensions) + bmi1 : 1, // Bit manipulation extensions group 1 + hle : 1, // Hardware Lock Elision + avx2 : 1, // AVX2 instruction set + fdp_excptn_only : 1, // FPU Data Pointer updated only on x87 exceptio= ns + smep : 1, // Supervisor Mode Execution Protection + bmi2 : 1, // Bit manipulation extensions group 2 + erms : 1, // Enhanced REP MOVSB/STOSB + invpcid : 1, // INVPCID instruction (Invalidate Processor Context ID) + rtm : 1, // Intel restricted transactional memory + pqm : 1, // Intel RDT-CMT / AMD Platform-QoS cache monitoring + zero_fcs_fds : 1, // Deprecated FPU CS/DS (stored as zero) + mpx : 1, // Intel memory protection extensions + rdt_a : 1, // Intel RDT / AMD Platform-QoS Enforcement + avx512f : 1, // AVX-512 foundation instructions + avx512dq : 1, // AVX-512 double/quadword instructions + rdseed : 1, // RDSEED instruction + adx : 1, // ADCX/ADOX instructions + smap : 1, // Supervisor mode access prevention + avx512ifma : 1, // AVX-512 integer fused multiply add + : 1, // Reserved + clflushopt : 1, // CLFLUSHOPT instruction + clwb : 1, // CLWB instruction + intel_pt : 1, // Intel processor trace + avx512pf : 1, // AVX-512 prefetch instructions + avx512er : 1, // AVX-512 exponent/reciprocal instructions + avx512cd : 1, // AVX-512 conflict detection instructions + sha : 1, // SHA/SHA256 instructions + avx512bw : 1, // AVX-512 byte/word instructions + avx512vl : 1; // AVX-512 VL (128/256 vector length) extensions + // ecx + u32 prefetchwt1 : 1, // PREFETCHWT1 (Intel Xeon Phi only) + avx512vbmi : 1, // AVX-512 Vector byte manipulation instructions + umip : 1, // User mode instruction protection + pku : 1, // Protection keys for user-space + ospke : 1, // OS protection keys enable + waitpkg : 1, // WAITPKG instructions + avx512_vbmi2 : 1, // AVX-512 vector byte manipulation instructions gr= oup 2 + cet_ss : 1, // CET shadow stack features + gfni : 1, // Galois field new instructions + vaes : 1, // Vector AES instructions + vpclmulqdq : 1, // VPCLMULQDQ 256-bit instruction + avx512_vnni : 1, // Vector neural network instructions + avx512_bitalg : 1, // AVX-512 bitwise algorithms + tme : 1, // Intel total memory encryption + avx512_vpopcntdq : 1, // AVX-512: POPCNT for vectors of DWORD/QWORD + : 1, // Reserved + la57 : 1, // 57-bit linear addresses (five-level paging) + mawau_val_lm : 5, // BNDLDX/BNDSTX MAWAU value in 64-bit mode + rdpid : 1, // RDPID instruction + key_locker : 1, // Intel key locker + bus_lock_detect : 1, // OS bus-lock detection + cldemote : 1, // CLDEMOTE instruction + : 1, // Reserved + movdiri : 1, // MOVDIRI instruction + movdir64b : 1, // MOVDIR64B instruction + enqcmd : 1, // Enqueue stores (ENQCMD{,S}) + sgx_lc : 1, // Intel SGX launch configuration + pks : 1; // Protection keys for supervisor-mode pages + // edx + u32 : 1, // Reserved + sgx_keys : 1, // Intel SGX attestation services + avx512_4vnniw : 1, // AVX-512 neural network instructions + avx512_4fmaps : 1, // AVX-512 multiply accumulation single precision + fsrm : 1, // Fast short REP MOV + uintr : 1, // User interrupts + : 2, // Reserved + avx512_vp2intersect : 1, // VP2INTERSECT{D,Q} instructions + srdbs_ctrl : 1, // SRBDS mitigation MSR + md_clear : 1, // VERW MD_CLEAR microcode + rtm_always_abort : 1, // XBEGIN (RTM transaction) always aborts + : 1, // Reserved + tsx_force_abort : 1, // MSR TSX_FORCE_ABORT, RTM_ABORT bit + serialize : 1, // SERIALIZE instruction + hybrid_cpu : 1, // The CPU is identified as a 'hybrid part' + tsxldtrk : 1, // TSX suspend/resume load address tracking + : 1, // Reserved + pconfig : 1, // PCONFIG instruction + arch_lbr : 1, // Intel architectural LBRs + cet_ibt : 1, // CET indirect branch tracking + : 1, // Reserved + amx_bf16 : 1, // AMX-BF16: tile bfloat16 + avx512_fp16 : 1, // AVX-512 FP16 instructions + amx_tile : 1, // AMX-TILE: tile architecture + amx_int8 : 1, // AMX-INT8: tile 8-bit integer + spec_ctrl : 1, // Speculation Control (IBRS/IBPB: indirect branch res= trictions) + intel_stibp : 1, // Single thread indirect branch predictors + flush_l1d : 1, // FLUSH L1D cache: IA32_FLUSH_CMD MSR + arch_capabilities : 1, // Intel IA32_ARCH_CAPABILITIES MSR + core_capabilities : 1, // IA32_CORE_CAPABILITIES MSR + spec_ctrl_ssbd : 1; // Speculative store bypass disable +}; + +struct leaf_0x7_1 { + // eax + u32 : 4, // Reserved + avx_vnni : 1, // AVX-VNNI instructions + avx512_bf16 : 1, // AVX-512 bfloat16 instructions + lass : 1, // Linear address space separation + cmpccxadd : 1, // CMPccXADD instructions + arch_perfmon_ext : 1, // ArchPerfmonExt: leaf 0x23 + : 1, // Reserved + fzrm : 1, // Fast zero-length REP MOVSB + fsrs : 1, // Fast short REP STOSB + fsrc : 1, // Fast Short REP CMPSB/SCASB + : 4, // Reserved + fred : 1, // FRED: Flexible return and event delivery transitions + lkgs : 1, // LKGS: Load 'kernel' (userspace) GS + wrmsrns : 1, // WRMSRNS instruction (WRMSR-non-serializing) + nmi_src : 1, // NMI-source reporting with FRED event data + amx_fp16 : 1, // AMX-FP16: FP16 tile operations + hreset : 1, // HRESET (Thread director history reset) + avx_ifma : 1, // Integer fused multiply add + : 2, // Reserved + lam : 1, // Linear address masking + rd_wr_msrlist : 1, // RDMSRLIST/WRMSRLIST instructions + : 4; // Reserved + // ebx + u32 intel_ppin : 1, // Protected processor inventory number (PPIN{,_CT= L} MSRs) + : 31; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 4, // Reserved + avx_vnni_int8 : 1, // AVX-VNNI-INT8 instructions + avx_ne_convert : 1, // AVX-NE-CONVERT instructions + : 2, // Reserved + amx_complex : 1, // AMX-COMPLEX instructions (starting from Granite R= apids) + : 5, // Reserved + prefetchit_0_1 : 1, // PREFETCHIT0/1 instructions + : 3, // Reserved + cet_sss : 1, // CET supervisor shadow stacks safe to use + : 13; // Reserved +}; + +struct leaf_0x7_2 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 intel_psfd : 1, // Intel predictive store forward disable + ipred_ctrl : 1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S} + rrsba_ctrl : 1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U + bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S + mcdt_no : 1, // MCDT mitigation not needed + uclock_disable : 1, // UC-lock disable + : 25; // Reserved +}; + +/* + * Leaf 0x9 + * Intel DCA (Direct Cache Access) + */ + +struct leaf_0x9_0 { + // eax + u32 dca_enabled_in_bios : 1, // DCA is enabled in BIOS + : 31; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xa + * Intel PMU (Performance Monitoring Unit) + */ + +struct leaf_0xa_0 { + // eax + u32 pmu_version : 8, // Performance monitoring unit version ID + num_counters_gp : 8, // Number of general-purpose PMU counters per lo= gical CPU + bit_width_gp : 8, // Bitwidth of PMU general-purpose counters + events_mask_len : 8; // Length of CPUID(0xa).EBX bit vector + // ebx + u32 no_core_cycle : 1, // Core cycle event not available + no_instruction_retired : 1, // Instruction retired event not available + no_reference_cycles : 1, // Reference cycles event not available + no_llc_reference : 1, // LLC-reference event not available + no_llc_misses : 1, // LLC-misses event not available + no_br_insn_retired : 1, // Branch instruction retired event not availa= ble + no_br_misses_retired : 1, // Branch mispredict retired event not avail= able + no_topdown_slots : 1, // Topdown slots event not available + no_backend_bound : 1, // Topdown backend bound not available + no_bad_speculation : 1, // Topdown bad speculation not available + no_frontend_bound : 1, // Topdown frontend bound not available + no_retiring : 1, // Topdown retiring not available + no_lbr_inserts : 1, // LBR inserts not available + : 19; // Reserved + // ecx + u32 pmu_fcounters_bitmap : 32; // Fixed-function PMU counters support bi= tmap + // edx + u32 num_counters_fixed : 5, // Number of fixed PMU counters + bitwidth_fixed : 8, // Bitwidth of PMU fixed counters + : 2, // Reserved + anythread_deprecation : 1, // AnyThread mode deprecation + : 16; // Reserved +}; + +/* + * Leaf 0xb + * CPU extended topology v1 + */ + +struct leaf_0xb_n { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 27; // Reserved + // ebx + u32 domain_lcpus_count : 16, // Logical CPUs count across all instances = of this domain + : 16; // Reserved + // ecx + u32 domain_nr : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +#define LEAF_0xb_SUBLEAF_N_FIRST 0 +#define LEAF_0xb_SUBLEAF_N_LAST 1 + +/* + * Leaf 0xd + * CPU extended state + */ + +struct leaf_0xd_0 { + // eax + u32 xcr0_x87 : 1, // XCR0.X87 + xcr0_sse : 1, // XCR0.SSE + xcr0_avx : 1, // XCR0.AVX + xcr0_mpx_bndregs : 1, // XCR0.BNDREGS: MPX BND0-BND3 registers + xcr0_mpx_bndcsr : 1, // XCR0.BNDCSR: MPX BNDCFGU/BNDSTATUS registers + xcr0_avx512_opmask : 1, // XCR0.OPMASK: AVX-512 k0-k7 registers + xcr0_avx512_zmm_hi256 : 1, // XCR0.ZMM_Hi256: AVX-512 ZMM0->ZMM7/15 re= gisters + xcr0_avx512_hi16_zmm : 1, // XCR0.HI16_ZMM: AVX-512 ZMM16->ZMM31 regis= ters + : 1, // Reserved + xcr0_pkru : 1, // XCR0.PKRU: XSAVE PKRU registers + : 1, // Reserved + xcr0_cet_u : 1, // XCR0.CET_U: CET user state + xcr0_cet_s : 1, // XCR0.CET_S: CET supervisor state + : 4, // Reserved + xcr0_tileconfig : 1, // XCR0.TILECONFIG: AMX can manage TILECONFIG + xcr0_tiledata : 1, // XCR0.TILEDATA: AMX can manage TILEDATA + : 13; // Reserved + // ebx + u32 xsave_sz_xcr0 : 32; // XSAVE/XRSTOR area byte size, for XCR0 enable= d features + // ecx + u32 xsave_sz_max : 32; // XSAVE/XRSTOR area max byte size, all CPU feat= ures + // edx + u32 : 30, // Reserved + xcr0_lwp : 1, // AMD XCR0.LWP: Light-weight Profiling + : 1; // Reserved +}; + +struct leaf_0xd_1 { + // eax + u32 xsaveopt : 1, // XSAVEOPT instruction + xsavec : 1, // XSAVEC instruction + xgetbv1 : 1, // XGETBV instruction with ECX =3D 1 + xsaves : 1, // XSAVES/XRSTORS instructions (and XSS MSR) + xfd : 1, // Extended feature disable + : 27; // Reserved + // ebx + u32 xsave_sz_xcr0_xss : 32; // XSAVES/XSAVEC area byte size, for XCR0|XS= S enabled features + // ecx + u32 : 8, // Reserved + xss_pt : 1, // PT state + : 1, // Reserved + xss_pasid : 1, // PASID state + xss_cet_u : 1, // CET user state + xss_cet_p : 1, // CET supervisor state + xss_hdc : 1, // HDC state + xss_uintr : 1, // UINTR state + xss_lbr : 1, // LBR state + xss_hwp : 1, // HWP state + : 15; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0xd_n { + // eax + u32 xsave_sz : 32; // Subleaf-N feature save area size, in bytes + // ebx + u32 xsave_offset : 32; // Subleaf-N feature save area offset, in bytes + // ecx + u32 is_xss_bit : 1, // Subleaf N describes an XSS bit (otherwise XCR0) + compacted_xsave_64byte_aligned : 1, // When compacted, subleaf-N XSAVE = area is 64-byte aligned + : 30; // Reserved + // edx + u32 : 32; // Reserved +}; + +#define LEAF_0xd_SUBLEAF_N_FIRST 2 +#define LEAF_0xd_SUBLEAF_N_LAST 63 + +/* + * Leaf 0xf + * Intel RDT / AMD PQoS resource monitoring + */ + +struct leaf_0xf_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 core_rmid_max : 32; // RMID max within this core (0-based) + // ecx + u32 : 32; // Reserved + // edx + u32 : 1, // Reserved + llc_qos_mon : 1, // LLC QoS-monitoring + : 30; // Reserved +}; + +struct leaf_0xf_1 { + // eax + u32 l3c_qm_bitwidth : 8, // L3 QoS-monitoring counter bitwidth (24-bas= ed) + l3c_qm_overflow_bit : 1, // QM_CTR MSR bit 61 is an overflow bit + io_rdt_cmt : 1, // non-CPU agent supporting Intel RDT CMT present + io_rdt_mbm : 1, // non-CPU agent supporting Intel RDT MBM present + : 21; // Reserved + // ebx + u32 l3c_qm_conver_factor : 32; // QM_CTR MSR conversion factor to bytes + // ecx + u32 l3c_qm_rmid_max : 32; // L3 QoS-monitoring max RMID + // edx + u32 l3c_qm_occupancy : 1, // L3 QoS occupancy monitoring + l3c_qm_mbm_total : 1, // L3 QoS total bandwidth monitoring + l3c_qm_mbm_local : 1, // L3 QoS local bandwidth monitoring + : 29; // Reserved +}; + +/* + * Leaf 0x10 + * Intel RDT / AMD PQoS allocation + */ + +struct leaf_0x10_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 1, // Reserved + cat_l3 : 1, // L3 Cache Allocation Technology + cat_l2 : 1, // L2 Cache Allocation Technology + mba : 1, // Memory Bandwidth Allocation + : 28; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x10_n { + // eax + u32 cat_cbm_len : 5, // L3/L2_CAT capacity bitmask length, minus-one n= otation + : 27; // Reserved + // ebx + u32 cat_units_bitmap : 32; // L3/L2_CAT allocation units bitmap + // ecx + u32 : 1, // Reserved + l3_cat_cos_infreq_updates : 1, // L3_CAT COS updates should be infreque= nt + cat_cdp_supported : 1, // L3/L2_CAT Code and Data Prioritization + cat_sparse_1s : 1, // L3/L2_CAT non-contiguous 1s value + : 28; // Reserved + // edx + u32 cat_cos_max : 16, // L3/L2_CAT max Class of Service + : 16; // Reserved +}; + +#define LEAF_0x10_SUBLEAF_N_FIRST 1 +#define LEAF_0x10_SUBLEAF_N_LAST 2 + +struct leaf_0x10_3 { + // eax + u32 mba_max_delay : 12, // Max MBA throttling value; minus-one notation + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 mba_per_thread : 1, // Per-thread MBA controls + : 1, // Reserved + mba_delay_linear : 1, // Delay values are linear + : 29; // Reserved + // edx + u32 mba_cos_max : 16, // MBA max Class of Service + : 16; // Reserved +}; + +/* + * Leaf 0x12 + * Intel SGX (Software Guard Extensions) + */ + +struct leaf_0x12_0 { + // eax + u32 sgx1 : 1, // SGX1 leaf functions + sgx2 : 1, // SGX2 leaf functions + : 3, // Reserved + enclv_leaves : 1, // ENCLV leaves + encls_leaves : 1, // ENCLS leaves + enclu_everifyreport2 : 1, // ENCLU leaf EVERIFYREPORT2 + : 2, // Reserved + encls_eupdatesvn : 1, // ENCLS leaf EUPDATESVN + enclu_edeccssa : 1, // ENCLU leaf EDECCSSA + : 20; // Reserved + // ebx + u32 miscselect_exinfo : 1, // SSA.MISC frame: Enclave #PF and #GP repor= ting + miscselect_cpinfo : 1, // SSA.MISC frame: Enclave #CP reporting + : 30; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 max_enclave_sz_not64 : 8, // Maximum enclave size in non-64-bit mod= e (log2) + max_enclave_sz_64 : 8, // Maximum enclave size in 64-bit mode (log2) + : 16; // Reserved +}; + +struct leaf_0x12_1 { + // eax + u32 secs_attr_init : 1, // Enclave initialized by EINIT + secs_attr_debug : 1, // Enclave permits debugger read/write + secs_attr_mode64bit : 1, // Enclave runs in 64-bit mode + : 1, // Reserved + secs_attr_provisionkey : 1, // Provisioning key + secs_attr_einittoken_key : 1, // EINIT token key + secs_attr_cet : 1, // CET attributes + secs_attr_kss : 1, // Key Separation and Sharing + : 2, // Reserved + secs_attr_aexnotify : 1, // Enclave threads: AEX notifications + : 21; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 xfrm_x87 : 1, // Enclave XFRM.X87 + xfrm_sse : 1, // Enclave XFRM.SEE + xfrm_avx : 1, // Enclave XFRM.AVX + xfrm_mpx_bndregs : 1, // Enclave XFRM.BNDREGS (MPX BND0-BND3 registers) + xfrm_mpx_bndcsr : 1, // Enclave XFRM.BNDCSR (MPX BNDCFGU/BNDSTATUS re= gisters) + xfrm_avx512_opmask : 1, // Enclave XFRM.OPMASK (AVX-512 k0-k7 register= s) + xfrm_avx512_zmm_hi256 : 1, // Enclave XFRM.ZMM_Hi256 (AVX-512 ZMM0->ZM= M7/15 registers) + xfrm_avx512_hi16_zmm : 1, // Enclave XFRM.HI16_ZMM (AVX-512 ZMM16->ZMM= 31 registers) + : 1, // Reserved + xfrm_pkru : 1, // Enclave XFRM.PKRU (XSAVE PKRU registers) + : 7, // Reserved + xfrm_tileconfig : 1, // Enclave XFRM.TILECONFIG (AMX can manage TILEC= ONFIG) + xfrm_tiledata : 1, // Enclave XFRM.TILEDATA (AMX can manage TILEDATA) + : 13; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x12_n { + // eax + u32 subleaf_type : 4, // Subleaf type + : 8, // Reserved + epc_sec_base_addr_0 : 20; // EPC section base address, bits[12:31] + // ebx + u32 epc_sec_base_addr_1 : 20, // EPC section base address, bits[32:51] + : 12; // Reserved + // ecx + u32 epc_sec_type : 4, // EPC section type / property encoding + : 8, // Reserved + epc_sec_size_0 : 20; // EPC section size, bits[12:31] + // edx + u32 epc_sec_size_1 : 20, // EPC section size, bits[32:51] + : 12; // Reserved +}; + +#define LEAF_0x12_SUBLEAF_N_FIRST 2 +#define LEAF_0x12_SUBLEAF_N_LAST 31 + +/* + * Leaf 0x14 + * Intel Processor Trace + */ + +struct leaf_0x14_0 { + // eax + u32 pt_max_subleaf : 32; // Maximum leaf 0x14 subleaf + // ebx + u32 cr3_filtering : 1, // IA32_RTIT_CR3_MATCH is accessible + psb_cyc : 1, // Configurable PSB and cycle-accurate mode + ip_filtering : 1, // IP/TraceStop filtering; Warm-reset PT MSRs prese= rvation + mtc_timing : 1, // MTC timing packet; COFI-based packets suppression + ptwrite : 1, // PTWRITE instruction + power_event_trace : 1, // Power Event Trace + psb_pmi_preserve : 1, // PSB and PMI preservation + event_trace : 1, // Event Trace packet generation + tnt_disable : 1, // TNT packet generation disable + : 23; // Reserved + // ecx + u32 topa_output : 1, // ToPA output scheme + topa_multiple_entries : 1, // ToPA tables can hold multiple entries + single_range_output : 1, // Single-range output + trance_transport_output : 1, // Trace Transport subsystem output + : 27, // Reserved + ip_payloads_lip : 1; // IP payloads have LIP values (CS base included) + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x14_1 { + // eax + u32 num_address_ranges : 3, // Number of configurable Address Ranges + : 13, // Reserved + mtc_periods_bmp : 16; // MTC period encodings bitmap + // ebx + u32 cycle_thresholds_bmp : 16, // Cycle Threshold encodings bitmap + psb_periods_bmp : 16; // Configurable PSB frequency encodings bitmap + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x15 + * Intel TSC (Time Stamp Counter) + */ + +struct leaf_0x15_0 { + // eax + u32 tsc_denominator : 32; // Denominator of the TSC/'core crystal clock= ' ratio + // ebx + u32 tsc_numerator : 32; // Numerator of the TSC/'core crystal clock' ra= tio + // ecx + u32 cpu_crystal_hz : 32; // Core crystal clock nominal frequency, in Hz + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x16 + * Intel processor frequency + */ + +struct leaf_0x16_0 { + // eax + u32 cpu_base_mhz : 16, // Processor base frequency, in MHz + : 16; // Reserved + // ebx + u32 cpu_max_mhz : 16, // Processor max frequency, in MHz + : 16; // Reserved + // ecx + u32 bus_mhz : 16, // Bus reference frequency, in MHz + : 16; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x17 + * Intel SoC vendor attributes + */ + +struct leaf_0x17_0 { + // eax + u32 soc_max_subleaf : 32; // Maximum leaf 0x17 subleaf + // ebx + u32 soc_vendor_id : 16, // SoC vendor ID + is_vendor_scheme : 1, // Assigned by industry enumeration scheme (not = Intel) + : 15; // Reserved + // ecx + u32 soc_proj_id : 32; // SoC project ID, assigned by vendor + // edx + u32 soc_stepping_id : 32; // Soc project stepping ID, assigned by vendor +}; + +struct leaf_0x17_n { + // eax + u32 vendor_brand_a : 32; // Vendor Brand ID string, bytes subleaf_nr * = (0 -> 3) + // ebx + u32 vendor_brand_b : 32; // Vendor Brand ID string, bytes subleaf_nr * = (4 -> 7) + // ecx + u32 vendor_brand_c : 32; // Vendor Brand ID string, bytes subleaf_nr * = (8 -> 11) + // edx + u32 vendor_brand_d : 32; // Vendor Brand ID string, bytes subleaf_nr * = (12 -> 15) +}; + +#define LEAF_0x17_SUBLEAF_N_FIRST 1 +#define LEAF_0x17_SUBLEAF_N_LAST 3 + +/* + * Leaf 0x18 + * Intel deterministic address translation (TLB) parameters + */ + +struct leaf_0x18_n { + // eax + u32 tlb_max_subleaf : 32; // Maximum leaf 0x18 subleaf + // ebx + u32 tlb_4k_page : 1, // TLB supports 4KB-page entries + tlb_2m_page : 1, // TLB supports 2MB-page entries + tlb_4m_page : 1, // TLB supports 4MB-page entries + tlb_1g_page : 1, // TLB supports 1GB-page entries + : 4, // Reserved + hard_partitioning : 3, // Partitioning between logical CPUs + : 5, // Reserved + n_way_associative : 16; // Ways of associativity + // ecx + u32 n_sets : 32; // Number of sets + // edx + u32 tlb_type : 5, // Translation cache type (TLB type) + tlb_cache_level : 3, // Translation cache level (1-based) + is_fully_associative : 1, // Fully-associative + : 5, // Reserved + tlb_max_addressible_ids : 12, // Max number of addressable IDs - 1 + : 6; // Reserved +}; + +#define LEAF_0x18_SUBLEAF_N_FIRST 0 +#define LEAF_0x18_SUBLEAF_N_LAST 31 + +/* + * Leaf 0x19 + * Intel key locker + */ + +struct leaf_0x19_0 { + // eax + u32 kl_cpl0_only : 1, // CPL0-only key Locker restriction + kl_no_encrypt : 1, // No-encrypt key locker restriction + kl_no_decrypt : 1, // No-decrypt key locker restriction + : 29; // Reserved + // ebx + u32 aes_keylocker : 1, // AES key locker instructions + : 1, // Reserved + aes_keylocker_wide : 1, // AES wide key locker instructions + : 1, // Reserved + kl_msr_iwkey : 1, // Key locker MSRs and IWKEY backups + : 27; // Reserved + // ecx + u32 loadiwkey_no_backup : 1, // LOADIWKEY NoBackup parameter + iwkey_rand : 1, // IWKEY randomization + : 30; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1a + * Intel hybrid CPUs identification (e.g. Atom, Core) + */ + +struct leaf_0x1a_0 { + // eax + u32 core_native_model : 24, // This core's native model ID + core_type : 8; // This core's type + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1b + * Intel PCONFIG (Platform configuration) + */ + +struct leaf_0x1b_n { + // eax + u32 pconfig_subleaf_type : 12, // CPUID 0x1b subleaf type + : 20; // Reserved + // ebx + u32 pconfig_target_id_x : 32; // A supported PCONFIG target ID + // ecx + u32 pconfig_target_id_y : 32; // A supported PCONFIG target ID + // edx + u32 pconfig_target_id_z : 32; // A supported PCONFIG target ID +}; + +#define LEAF_0x1b_SUBLEAF_N_FIRST 0 +#define LEAF_0x1b_SUBLEAF_N_LAST 31 + +/* + * Leaf 0x1c + * Intel LBR (Last Branch Record) + */ + +struct leaf_0x1c_0 { + // eax + u32 lbr_depth_mask : 8, // Max LBR stack depth bitmask + : 22, // Reserved + lbr_deep_c_reset : 1, // LBRs maybe cleared on MWAIT C-state > C1 + lbr_ip_is_lip : 1; // LBR IP contain Last IP (otherwise effective IP) + // ebx + u32 lbr_cpl : 1, // CPL filtering + lbr_branch_filter : 1, // Branch filtering + lbr_call_stack : 1, // Call-stack mode + : 29; // Reserved + // ecx + u32 lbr_mispredict : 1, // Branch misprediction bit + lbr_timed_lbr : 1, // Timed LBRs (CPU cycles since last LBR entry) + lbr_branch_type : 1, // Branch type field + : 13, // Reserved + lbr_events_gpc_bmp : 4, // PMU-events logging support + : 12; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1d + * Intel AMX (Advanced Matrix Extensions) tile information + */ + +struct leaf_0x1d_0 { + // eax + u32 amx_max_palette : 32; // Highest palette ID / subleaf ID + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x1d_1 { + // eax + u32 amx_palette_size : 16, // AMX palette total tiles size, in bytes + amx_tile_size : 16; // AMX single tile's size, in bytes + // ebx + u32 amx_tile_row_size : 16, // AMX tile single row's size, in bytes + amx_palette_nr_tiles : 16; // AMX palette number of tiles + // ecx + u32 amx_tile_nr_rows : 16, // AMX tile max number of rows + : 16; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1e + * Intel TMUL (Tile-matrix Multiply) + */ + +struct leaf_0x1e_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 tmul_maxk : 8, // TMUL unit maximum height, K (rows or columns) + tmul_maxn : 16, // TMUL unit maximum SIMD dimension, N (column bytes) + : 8; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1f + * Intel extended topology v2 + */ + +struct leaf_0x1f_n { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 27; // Reserved + // ebx + u32 domain_lcpus_count : 16, // Logical CPUs count across all instances = of this domain + : 16; // Reserved + // ecx + u32 domain_level : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +#define LEAF_0x1f_SUBLEAF_N_FIRST 0 +#define LEAF_0x1f_SUBLEAF_N_LAST 5 + +/* + * Leaf 0x20 + * Intel HRESET (History Reset) + */ + +struct leaf_0x20_0 { + // eax + u32 hreset_nr_subleaves : 32; // CPUID 0x20 max subleaf + 1 + // ebx + u32 hreset_thread_director : 1, // Intel thread director HRESET + : 31; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x21 + * Intel TD (Trust Domain) + */ + +struct leaf_0x21_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 tdx_vendorid_0 : 32; // TDX vendor ID string bytes 0 - 3 + // ecx + u32 tdx_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + // edx + u32 tdx_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x23 + * Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) + */ + +struct leaf_0x23_0 { + // eax + u32 subleaf_0 : 1, // Subleaf 0, this subleaf + counters_subleaf : 1, // Subleaf 1, PMU counter bitmaps + acr_subleaf : 1, // Subleaf 2, Auto Counter Reload bitmaps + events_subleaf : 1, // Subleaf 3, PMU event bitmaps + pebs_caps_subleaf : 1, // Subleaf 4, PEBS capabilities + pebs_subleaf : 1, // Subleaf 5, Arch PEBS bitmaps + : 26; // Reserved + // ebx + u32 unitmask2 : 1, // IA32_PERFEVTSELx MSRs UnitMask2 bit + eq : 1, // IA32_PERFEVTSELx MSRs EQ bit + rdpmc_user_disable : 1, // RDPMC userspace disable + : 29; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_1 { + // eax + u32 gp_counters : 32; // Bitmap of general-purpose PMU counters + // ebx + u32 fixed_counters : 32; // Bitmap of fixed PMU counters + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_2 { + // eax + u32 acr_gp_reload : 32; // Bitmap of general-purpose counters that can = be reloaded + // ebx + u32 acr_fixed_reload : 32; // Bitmap of fixed counters that can be reloa= ded + // ecx + u32 acr_gp_trigger : 32; // Bitmap of general-purpose counters that can= trigger reloads + // edx + u32 acr_fixed_trigger : 32; // Bitmap of fixed counters that can trigger= reloads +}; + +struct leaf_0x23_3 { + // eax + u32 core_cycles_evt : 1, // Core cycles event + insn_retired_evt : 1, // Instructions retired event + ref_cycles_evt : 1, // Reference cycles event + llc_refs_evt : 1, // Last-level cache references event + llc_misses_evt : 1, // Last-level cache misses event + br_insn_ret_evt : 1, // Branch instruction retired event + br_mispr_evt : 1, // Branch mispredict retired event + td_slots_evt : 1, // Topdown slots event + td_backend_bound_evt : 1, // Topdown backend bound event + td_bad_spec_evt : 1, // Topdown bad speculation event + td_frontend_bound_evt : 1, // Topdown frontend bound event + td_retiring_evt : 1, // Topdown retiring event + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_4 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 3, // Reserved + allow_in_record : 1, // ALLOW_IN_RECORD bit in MSRs + counters_gp : 1, // Counters group sub-group general-purpose counters + counters_fixed : 1, // Counters group sub-group fixed-function counte= rs + counters_metrics : 1, // Counters group sub-group performance metrics + : 1, // Reserved + lbr : 2, // LBR group + : 6, // Reserved + xer : 8, // XER group + : 5, // Reserved + gpr : 1, // GPR group + aux : 1, // AUX group + : 1; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_5 { + // eax + u32 pebs_gp : 32; // Architectural PEBS general-purpose counters + // ebx + u32 pebs_pdist_gp : 32; // Architectural PEBS PDIST general-purpose cou= nters + // ecx + u32 pebs_fixed : 32; // Architectural PEBS fixed counters + // edx + u32 pebs_pdist_fixed : 32; // Architectural PEBS PDIST fixed counters +}; + +/* + * Leaf 0x40000000 + * Maximum hypervisor leaf + hypervisor vendor string + */ + +struct leaf_0x40000000_0 { + // eax + u32 max_hyp_leaf : 32; // Maximum hypervisor leaf + // ebx + u32 hypervisor_id_0 : 32; // Hypervisor ID string bytes 0 - 3 + // ecx + u32 hypervisor_id_1 : 32; // Hypervisor ID string bytes 4 - 7 + // edx + u32 hypervisor_id_2 : 32; // Hypervisor ID string bytes 8 - 11 +}; + +/* + * Leaf 0x4c780001 + * Linux-defined synthetic feature flags + */ + +struct leaf_0x4c780001_0 { + // eax + u32 cxmmx : 1, // Cyrix MMX extensions + k6_mtrr : 1, // AMD K6 nonstandard MTRRs + cyrix_arr : 1, // Cyrix ARRs (=3D MTRRs) + centaur_mcr : 1, // Centaur MCRs (=3D MTRRs) + k8 : 1, // Opteron, Athlon64 + zen5 : 1, // CPU based on Zen5 micro-architecture + zen6 : 1, // CPU based on Zen6 micro-architecture + : 1, // Reserved + constant_tsc : 1, // TSC ticks at a constant rate + up : 1, // SMP kernel running on UP + art : 1, // Always running timer (ART) + arch_perfmon : 1, // Intel Architectural PerfMon + pebs : 1, // Precise-Event Based Sampling + bts : 1, // Branch Trace Store + syscall32 : 1, // SYSCALL in IA32 userspace + sysenter32 : 1, // SYSENTER in IA32 userspace + rep_good : 1, // REP microcode works well + amd_lbr_v2 : 1, // AMD Last Branch Record Extension version 2 + clear_cpu_buf : 1, // Clear CPU buffers using VERW + acc_power : 1, // AMD Accumulated Power Mechanism + nopl : 1, // The NOPL instructions + always : 1, // Always-present feature + xtopology : 1, // CPU topology enumeration extensions + tsc_reliable : 1, // TSC is known to be reliable + nonstop_tsc : 1, // TSC does not stop in C states + cpuid : 1, // CPU has the CPUID instruction + extd_apicid : 1, // Extended APIC ID (8 bits) + amd_dcm : 1, // AMD multi-node processor + aperfmperf : 1, // APERF/MPERF MSRs: P-State hardware coordination fe= edback + rapl : 1, // AMD/Hygon RAPL interface + nonstop_tsc_s3 : 1, // TSC does not stop in S3 state + tsc_known_freq : 1; // TSC has known frequency + // ebx + u32 ring3mwait : 1, // Ring 3 MONITOR/MWAIT instructions + cpuid_fault : 1, // Intel CPUID faulting + cpb : 1, // AMD Core Performance Boost + epb : 1, // IA32_ENERGY_PERF_BIAS support + cat_l3 : 1, // Cache Allocation Technology L3 + cat_l2 : 1, // Cache Allocation Technology L2 + cdp_l3 : 1, // Code and Data Prioritization L3 + tdx_host_platform : 1, // Platform supports being a TDX host + hw_pstate : 1, // AMD Hardware P-state control + proc_feedback : 1, // AMD Processor Feedback Interface + xcompacted : 1, // Use compacted XSTATE (XSAVES or XSAVEC) + pti : 1, // Kernel Page Table Isolation enabled + kernel_ibrs : 1, // Set/clear IBRS on kernel entry/exit + rsb_vmexit : 1, // Fill RSB on VM-Exit + intel_ppin : 1, // Intel Processor Inventory Number + cdp_l2 : 1, // Code and Data Prioritization L2 + msr_spec_ctrl : 1, // MSR SPEC_CTRL is implemented + ssbd : 1, // Speculative Store Bypass Disable + mba : 1, // Memory Bandwidth Allocation + rsb_ctxsw : 1, // Fill RSB on context switches + perfmon_v2 : 1, // AMD Performance Monitoring Version 2 + : 1, // Reserved + use_ibrs_fw : 1, // Use IBRS during runtime firmware calls + ss_bypass_disable : 1, // Disable Speculative Store Bypass + ls_cfg_ssbd : 1, // AMD SSBD implementation via LS_CFG MSR + ibrs : 1, // Indirect Branch Restricted Speculation + ibpb : 1, // Indirect Branch Prediction Barrier (without RSB flush g= uarantee) + stibp : 1, // Single Thread Indirect Branch Predictors + zen : 1, // Generic flag for all Zen and newer + l1tf_pteinv : 1, // L1TF workaround PTE inversion + ibrs_enhanced : 1, // Enhanced IBRS + msr_ia32_feat_ctl : 1; // MSR IA32_FEAT_CTL configured + // ecx + u32 tpr_shadow : 1, // Intel TPR Shadow + flexpriority : 1, // Intel FlexPriority + ept : 1, // Intel Extended Page Table + vpid : 1, // Intel Virtual Processor ID + coherency_sfw_no : 1, // SNP cache coherency software work around not = needed + : 10, // Reserved + vmmcall : 1, // Prefer VMMCALL to VMCALL + xenpv : 1, // Xen paravirtual guest + ept_ad : 1, // Intel Extended Page Table access-dirty bit + VMCALL : 1, // Hypervisor supports the VMCALL instruction + vmw_vmmcall : 1, // VMware prefers the VMMCALL instruction + pvunlock : 1, // PV unlock function + vcpupreempt : 1, // PV vcpu_is_preempted function + tdx_guest : 1, // Intel Trust Domain Extensions Guest + : 9; // Reserved + // edx + u32 cqm_llc : 1, // LLC QoS + cqm_occup_llc : 1, // LLC occupancy monitoring + cqm_mbm_total : 1, // LLC Total MBM monitoring + cqm_mbm_local : 1, // LLC Local MBM monitoring + fence_swapgs_user : 1, // LFENCE in user entry SWAPGS path + fence_swapgs_kernel : 1, // LFENCE in kernel entry SWAPGS path + split_lock_detect : 1, // #AC for split lock + per_thread_mba : 1, // Per-thread Memory Bandwidth Allocation + sgx1 : 1, // SGX Basic + sgx2 : 1, // SGX Enclave Dynamic Memory Management (EDMM) + entry_ibpb : 1, // Issue an IBPB on kernel entry + rrsba_ctrl : 1, // RET prediction control + retpoline : 1, // Generic Retpoline mitigation for Spectre variant 2 + retpoline_lfence : 1, // Use LFENCE for Spectre variant 2 + rethunk : 1, // Use Return THUNK + unret : 1, // AMD BTB untrain return + use_ibpb_fw : 1, // Use IBPB during runtime firmware calls + rsb_vmexit_lite : 1, // Fill RSB on VM exit when EIBRS is enabled + sgx_edeccssa : 1, // SGX EDECCSSA user leaf function + call_depth : 1, // Call depth tracking for RSB stuffing + msr_tsx_ctrl : 1, // MSR IA32_TSX_CTRL (Intel) implemented + smba : 1, // Slow Memory Bandwidth Allocation + bmec : 1, // Bandwidth Monitoring Event Configuration + user_shstk : 1, // Shadow stack support for user mode applications + srso : 1, // AMD BTB untrain RETs + srso_alias : 1, // AMD BTB untrain RETs through aliasing + ibpb_on_vmexit : 1, // Issue an IBPB only on VMEXIT + apic_msrs_fence : 1, // IA32_TSC_DEADLINE and X2APIC MSRs need fencing + zen2 : 1, // CPU based on Zen2 microarchitecture + zen3 : 1, // CPU based on Zen3 microarchitecture + zen4 : 1, // CPU based on Zen4 microarchitecture + zen1 : 1; // CPU based on Zen1 microarchitecture +}; + +struct leaf_0x4c780001_1 { + // eax + u32 overflow_recov : 1, // MCA overflow recovery support + succor : 1, // Uncorrectable error containment and recovery + : 1, // Reserved + smca : 1, // Scalable MCA + : 28; // Reserved + // ebx + u32 amd_lbr_pmc_freeze : 1, // AMD LBR and PMC Freeze + clear_bhb_loop : 1, // Clear branch history at SYSCALL entry using SW= loop + bhi_ctrl : 1, // BHI_DIS_S HW control available + clear_bhb_hw : 1, // BHI_DIS_S HW control enabled + clear_bhb_vmexit : 1, // Clear branch history at VMEXIT using SW loop + amd_fast_cppc : 1, // AMD fast Collaborative Processor Performance Co= ntrol + amd_htr_cores : 1, // Heterogeneous Core Topology + amd_workload_class : 1, // Workload Classification + prefer_ymm : 1, // Avoid ZMM registers due to downclocking + apx : 1, // Advanced Performance Extensions + indirect_thunk_its : 1, // Use thunk for indirect branches in lower ha= lf of cache line + tsa_sq_no : 1, // AMD CPU not vulnerable to TSA-SQ + tsa_l1_no : 1, // AMD CPU not vulnerable to TSA-L1 + clear_cpu_buf_vm : 1, // Clear CPU buffers using VERW before VMRUN + ibpb_exit_to_user : 1, // Use IBPB on exit-to-userspace, see VMSCAPE b= ug + : 17; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x4c780002 + * Linux-defined synthetic CPU bug flags + */ + +struct leaf_0x4c780002_0 { + // eax + u32 f00f : 1, // Intel F00F + fdiv : 1, // FPU FDIV + coma : 1, // Cyrix 6x86 coma + amd_tlb_mmatch : 1, // AMD Erratum 383 + amd_apic_c1e : 1, // AMD Erratum 400 + bug_11ap : 1, // Bad local APIC aka 11AP + fxsave_leak : 1, // FXSAVE leaks FOP/FIP/FOP + clflush_monitor : 1, // AAI65, CLFLUSH required before MONITOR + sysret_ss_attrs : 1, // SYSRET does not fix up SS attributes + espfix : 1, // IRET to 16-bit SS corrupts ESP/RSP high bits (x86-32) + null_seg : 1, // Setting a selector to NULL preserves the base + swapgs_fence : 1, // SWAPGS without input dep on GS + monitor : 1, // IPI required to wake up remote CPU + amd_e400 : 1, // CPU is among the affected by Erratum 400 + cpu_meltdown : 1, // CPU affected by meltdown; needs kernel page tabl= e isolation + spectre_v1 : 1, // CPU affected by Spectre variant 1 with conditional= branches + specture_v2 : 1, // CPU affected by Spectre variant 2 with indirect b= ranches + spec_store_bypass : 1, // CPU affected by speculative store bypass att= ack + l1tf : 1, // CPU affected by L1 Terminal Fault + mds : 1, // CPU affected by Microarchitectural data sampling + msbds_only : 1, // Microarchitectural data sampling: CPU only affecte= d by the MSDBS variant + swapgs : 1, // CPU affected by speculation through SWAPGS + taa : 1, // CPU is affected by TSX Async Abort (TAA) + itlb_multihit : 1, // CPU may incur MCE during certain page attribute= changes + srbds : 1, // CPU may leak RNG bits if not mitigated + mmio_stale_data : 1, // CPU affected by Processor MMIO Stale Data vul= nerabilities + : 1, // Reserved + retbleed : 1, // CPU affected by Retbleed + eibrs_pbrsb : 1, // EIBRS is vulnerable to Post Barrier RSB Predictio= ns + smt_rsb : 1, // CPU vulnerable to Cross-Thread Return Address Predic= tions + gds : 1, // CPU affected by Gather Data Sampling + tdx_pw_mce : 1; // CPU may incur #MC if non-TD software does partial = write to TDX private memory + // ebx + u32 srso : 1, // AMD SRSO bug + div0 : 1, // AMD DIV0 speculation bug + rfds : 1, // CPU vulnerable to Register File Data Sampling + bhi : 1, // CPU affected by Branch History Injection + ibpb_no_ret : 1, // IBPB omits return target predictions + spectre_v2_user : 1, // CPU affected by Spectre variant 2 between use= r processes + old_microcode : 1, // CPU has old microcode; it must be vulnerable to= something + its : 1, // CPU affected by Indirect Target Selection + its_native_only : 1, // CPU affected by ITS; VMX is not affected + tsa : 1, // CPU affected by Transient Scheduler Attacks + vmscape : 1, // CPU affected by VMSCAPE attacks from guests + : 21; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000000 + * Maximum extended leaf + CPU vendor string + */ + +struct leaf_0x80000000_0 { + // eax + u32 max_ext_leaf : 32; // Maximum extended CPUID leaf + // ebx + u32 cpu_vendorid_0 : 32; // Vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // Vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // Vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x80000001 + * Extended CPU features + */ + +struct leaf_0x80000001_0 { + // eax + u32 e_stepping_id : 4, // Stepping ID + e_base_model : 4, // Base processor model + e_base_family : 4, // Base processor family + e_base_type : 2, // Base processor type (Transmeta) + : 2, // Reserved + e_ext_model : 4, // Extended processor model + e_ext_family : 8, // Extended processor family + : 4; // Reserved + // ebx + u32 brand_id : 16, // Brand ID + : 12, // Reserved + pkg_type : 4; // Package type + // ecx + u32 lahf_lm : 1, // LAHF and SAHF in 64-bit mode + cmp_legacy : 1, // Multi-processing legacy mode (No HT) + svm : 1, // Secure Virtual Machine + extapic : 1, // Extended APIC space + cr8_legacy : 1, // LOCK MOV CR0 means MOV CR8 + lzcnt_abm : 1, // LZCNT advanced bit manipulation + sse4a : 1, // SSE4A support + misaligned_sse : 1, // Misaligned SSE mode + _3dnow_prefetch : 1, // 3DNow PREFETCH/PREFETCHW support + osvw : 1, // OS visible workaround + ibs : 1, // Instruction based sampling + xop : 1, // XOP: extended operation (AVX instructions) + skinit : 1, // SKINIT/STGI support + wdt : 1, // Watchdog timer support + : 1, // Reserved + lwp : 1, // Lightweight profiling + fma4 : 1, // 4-operand FMA instruction + tce : 1, // Translation cache extension + : 1, // Reserved + nodeid_msr : 1, // NodeId MSR (0xc001100c) + : 1, // Reserved + tbm : 1, // Trailing bit manipulations + topoext : 1, // Topology Extensions (leaf 0x8000001d) + perfctr_core : 1, // Core performance counter extensions + perfctr_nb : 1, // NB/DF performance counter extensions + : 1, // Reserved + data_bp_ext : 1, // Data access breakpoint extension + perf_tsc : 1, // Performance time-stamp counter + perfctr_llc : 1, // LLC (L3) performance counter extensions + mwaitx : 1, // MWAITX/MONITORX support + addr_mask_ext : 1, // Breakpoint address mask extension (to bit 31) + : 1; // Reserved + // edx + u32 e_fpu : 1, // Floating-Point Unit on-chip (x87) + e_vme : 1, // Virtual-8086 Mode Extensions + e_de : 1, // Debugging Extensions + e_pse : 1, // Page Size Extension + e_tsc : 1, // Time Stamp Counter + e_msr : 1, // Model-Specific Registers (RDMSR and WRMSR support) + pae : 1, // Physical Address Extensions + mce : 1, // Machine Check Exception + cx8 : 1, // CMPXCHG8B instruction + apic : 1, // APIC on-chip + : 1, // Reserved + syscall : 1, // SYSCALL and SYSRET instructions + mtrr : 1, // Memory Type Range Registers + pge : 1, // Page Global Extensions + mca : 1, // Machine Check Architecture + cmov : 1, // Conditional Move Instruction + pat : 1, // Page Attribute Table + pse36 : 1, // Page Size Extension (36-bit) + : 1, // Reserved + obsolete_mp_bit : 1, // Out-of-spec AMD Multiprocessing bit + nx : 1, // No-execute page protection + : 1, // Reserved + mmxext : 1, // AMD MMX extensions + e_mmx : 1, // MMX instructions + e_fxsr : 1, // FXSAVE and FXRSTOR instructions + fxsr_opt : 1, // FXSAVE and FXRSTOR optimizations + page1gb : 1, // 1-GB large page support + rdtscp : 1, // RDTSCP instruction + : 1, // Reserved + lm : 1, // Long mode (x86-64, 64-bit support) + _3dnowext : 1, // AMD 3DNow extensions + _3dnow : 1; // 3DNow instructions +}; + +/* + * Leaf 0x80000002 + * CPU brand ID string, bytes 0 - 15 + */ + +struct leaf_0x80000002_0 { + // eax + u32 cpu_brandid_0 : 32; // CPU brand ID string, bytes 0 - 3 + // ebx + u32 cpu_brandid_1 : 32; // CPU brand ID string, bytes 4 - 7 + // ecx + u32 cpu_brandid_2 : 32; // CPU brand ID string, bytes 8 - 11 + // edx + u32 cpu_brandid_3 : 32; // CPU brand ID string, bytes 12 - 15 +}; + +/* + * Leaf 0x80000003 + * CPU brand ID string, bytes 16 - 31 + */ + +struct leaf_0x80000003_0 { + // eax + u32 cpu_brandid_4 : 32; // CPU brand ID string bytes, 16 - 19 + // ebx + u32 cpu_brandid_5 : 32; // CPU brand ID string bytes, 20 - 23 + // ecx + u32 cpu_brandid_6 : 32; // CPU brand ID string bytes, 24 - 27 + // edx + u32 cpu_brandid_7 : 32; // CPU brand ID string bytes, 28 - 31 +}; + +/* + * Leaf 0x80000004 + * CPU brand ID string, bytes 32 - 47 + */ + +struct leaf_0x80000004_0 { + // eax + u32 cpu_brandid_8 : 32; // CPU brand ID string, bytes 32 - 35 + // ebx + u32 cpu_brandid_9 : 32; // CPU brand ID string, bytes 36 - 39 + // ecx + u32 cpu_brandid_10 : 32; // CPU brand ID string, bytes 40 - 43 + // edx + u32 cpu_brandid_11 : 32; // CPU brand ID string, bytes 44 - 47 +}; + +/* + * Leaf 0x80000005 + * AMD/Transmeta L1 cache and TLB + */ + +struct leaf_0x80000005_0 { + // eax + u32 l1_itlb_2m_4m_nentries : 8, // L1 ITLB #entries, 2M and 4M pages + l1_itlb_2m_4m_assoc : 8, // L1 ITLB associativity, 2M and 4M pages + l1_dtlb_2m_4m_nentries : 8, // L1 DTLB #entries, 2M and 4M pages + l1_dtlb_2m_4m_assoc : 8; // L1 DTLB associativity, 2M and 4M pages + // ebx + u32 l1_itlb_4k_nentries : 8, // L1 ITLB #entries, 4K pages + l1_itlb_4k_assoc : 8, // L1 ITLB associativity, 4K pages + l1_dtlb_4k_nentries : 8, // L1 DTLB #entries, 4K pages + l1_dtlb_4k_assoc : 8; // L1 DTLB associativity, 4K pages + // ecx + u32 l1_dcache_line_size : 8, // L1 dcache line size, in bytes + l1_dcache_nlines : 8, // L1 dcache lines per tag + l1_dcache_assoc : 8, // L1 dcache associativity + l1_dcache_size_kb : 8; // L1 dcache size, in KB + // edx + u32 l1_icache_line_size : 8, // L1 icache line size, in bytes + l1_icache_nlines : 8, // L1 icache lines per tag + l1_icache_assoc : 8, // L1 icache associativity + l1_icache_size_kb : 8; // L1 icache size, in KB +}; + +/* + * Leaf 0x80000006 + * (Mostly AMD) L2/L3 cache and TLB + */ + +struct leaf_0x80000006_0 { + // eax + u32 l2_itlb_2m_4m_nentries : 12, // L2 iTLB #entries, 2M and 4M pages + l2_itlb_2m_4m_assoc : 4, // L2 iTLB associativity, 2M and 4M pages + l2_dtlb_2m_4m_nentries : 12, // L2 dTLB #entries, 2M and 4M pages + l2_dtlb_2m_4m_assoc : 4; // L2 dTLB associativity, 2M and 4M pages + // ebx + u32 l2_itlb_4k_nentries : 12, // L2 iTLB #entries, 4K pages + l2_itlb_4k_assoc : 4, // L2 iTLB associativity, 4K pages + l2_dtlb_4k_nentries : 12, // L2 dTLB #entries, 4K pages + l2_dtlb_4k_assoc : 4; // L2 dTLB associativity, 4K pages + // ecx + u32 l2_line_size : 8, // L2 cache line size, in bytes + l2_nlines : 4, // L2 cache number of lines per tag + l2_assoc : 4, // L2 cache associativity + l2_size_kb : 16; // L2 cache size, in KB + // edx + u32 l3_line_size : 8, // L3 cache line size, in bytes + l3_nlines : 4, // L3 cache number of lines per tag + l3_assoc : 4, // L3 cache associativity + : 2, // Reserved + l3_size_range : 14; // L3 cache size range +}; + +/* + * Leaf 0x80000007 + * CPU power management (mostly AMD) and AMD RAS + */ + +struct leaf_0x80000007_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 mca_overflow_recovery : 1, // MCA overflow conditions not fatal + succor : 1, // Software containment of uncorrectable errors + hw_assert : 1, // Hardware assert MSRs + scalable_mca : 1, // Scalable MCA (MCAX MSRs) + : 28; // Reserved + // ecx + u32 cpu_pwr_sample_ratio : 32; // CPU power sample time ratio + // edx + u32 digital_temp : 1, // Digital temperature sensor + powernow_freq_id : 1, // PowerNOW! frequency scaling + powernow_volt_id : 1, // PowerNOW! voltage scaling + thermal_trip : 1, // THERMTRIP (Thermal Trip) + hw_thermal_control : 1, // Hardware thermal control + sw_thermal_control : 1, // Software thermal control + _100mhz_steps : 1, // 100 MHz multiplier control + hw_pstate : 1, // Hardware P-state control + constant_tsc : 1, // TSC ticks at constant rate across all P and C st= ates + core_perf_boost : 1, // Core performance boost + eff_freq_ro : 1, // Read-only effective frequency interface + proc_feedback : 1, // Processor feedback interface (deprecated) + proc_power_reporting : 1, // Processor power reporting interface + connected_standby : 1, // CPU Connected Standby support + rapl_interface : 1, // Runtime Average Power Limit interface + : 17; // Reserved +}; + +/* + * Leaf 0x80000008 + * CPU capacity parameters and extended feature flags (mostly AMD) + */ + +struct leaf_0x80000008_0 { + // eax + u32 phys_addr_bits : 8, // Max physical address bits + virt_addr_bits : 8, // Max virtual address bits + guest_phys_addr_bits : 8, // Max nested-paging guest physical address = bits + : 8; // Reserved + // ebx + u32 clzero : 1, // CLZERO instruction + insn_retired_perf : 1, // Instruction retired counter MSR + xsave_err_ptr : 1, // XSAVE/XRSTOR always saves/restores FPU error po= inters + invlpgb : 1, // INVLPGB broadcasts a TLB invalidate + rdpru : 1, // RDPRU (Read Processor Register at User level) + : 1, // Reserved + mba : 1, // Memory Bandwidth Allocation (AMD bit) + : 1, // Reserved + mcommit : 1, // MCOMMIT instruction + wbnoinvd : 1, // WBNOINVD instruction + : 2, // Reserved + ibpb : 1, // Indirect Branch Prediction Barrier + wbinvd_int : 1, // Interruptible WBINVD/WBNOINVD + ibrs : 1, // Indirect Branch Restricted Speculation + stibp : 1, // Single Thread Indirect Branch Prediction mode + ibrs_always_on : 1, // IBRS always-on preferred + stibp_always_on : 1, // STIBP always-on preferred + ibrs_fast : 1, // IBRS is preferred over software solution + ibrs_same_mode : 1, // IBRS provides same mode protection + no_efer_lmsle : 1, // Long-Mode Segment Limit Enable unsupported + tlb_flush_nested : 1, // INVLPGB RAX[5] bit can be set + : 1, // Reserved + amd_ppin : 1, // Protected Processor Inventory Number + amd_ssbd : 1, // Speculative Store Bypass Disable + virt_ssbd : 1, // virtualized SSBD (Speculative Store Bypass Disable) + amd_ssb_no : 1, // SSBD is not needed (fixed in hardware) + cppc : 1, // Collaborative Processor Performance Control + amd_psfd : 1, // Predictive Store Forward Disable + btc_no : 1, // CPU not affected by Branch Type Confusion + ibpb_ret : 1, // IBPB clears RSB/RAS too + branch_sampling : 1; // Branch Sampling + // ecx + u32 cpu_nthreads : 8, // Number of physical threads - 1 + : 4, // Reserved + apicid_coreid_len : 4, // Number of thread core ID bits (shift) in API= C ID + perf_tsc_len : 2, // Performance time-stamp counter size + : 14; // Reserved + // edx + u32 invlpgb_max_pages : 16, // INVLPGB maximum page count + rdpru_max_reg_id : 16; // RDPRU max register ID (ECX input) +}; + +/* + * Leaf 0x8000000a + * AMD SVM (Secure Virtual Machine) + */ + +struct leaf_0x8000000a_0 { + // eax + u32 svm_version : 8, // SVM revision number + : 24; // Reserved + // ebx + u32 svm_nasid : 32; // Number of address space identifiers (ASID) + // ecx + u32 : 4, // Reserved + pml : 1, // Page Modification Logging (PML) + : 27; // Reserved + // edx + u32 nested_pt : 1, // Nested paging + lbr_virt : 1, // LBR virtualization + svm_lock : 1, // SVM lock + nrip_save : 1, // NRIP save support on #VMEXIT + tsc_rate_msr : 1, // MSR based TSC rate control + vmcb_clean : 1, // VMCB clean bits support + flush_by_asid : 1, // Flush by ASID + Extended VMCB TLB_Control + decode_assists : 1, // Decode Assists support + : 2, // Reserved + pause_filter : 1, // Pause intercept filter + : 1, // Reserved + pf_threshold : 1, // Pause filter threshold + avic : 1, // Advanced virtual interrupt controller + : 1, // Reserved + v_vmsave_vmload : 1, // Virtual VMSAVE/VMLOAD (nested virtualization) + v_gif : 1, // Virtualize the Global Interrupt Flag + gmet : 1, // Guest mode execution trap + x2avic : 1, // Virtual x2APIC + sss_check : 1, // Supervisor Shadow Stack restrictions + v_spec_ctrl : 1, // Virtual SPEC_CTRL + ro_gpt : 1, // Read-Only guest page table support + : 1, // Reserved + h_mce_override : 1, // Host MCE override + tlbsync_int : 1, // TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB + nmi_virt : 1, // NMI virtualization + ibs_virt : 1, // IBS Virtualization + ext_lvt_off_chg : 1, // Extended LVT offset fault change + svme_addr_chk : 1, // Guest SVME address check + : 3; // Reserved +}; + +/* + * Leaf 0x80000019 + * AMD TLB characteristics for 1GB pages + */ + +struct leaf_0x80000019_0 { + // eax + u32 l1_itlb_1g_nentries : 12, // L1 iTLB #entries, 1G pages + l1_itlb_1g_assoc : 4, // L1 iTLB associativity, 1G pages + l1_dtlb_1g_nentries : 12, // L1 dTLB #entries, 1G pages + l1_dtlb_1g_assoc : 4; // L1 dTLB associativity, 1G pages + // ebx + u32 l2_itlb_1g_nentries : 12, // L2 iTLB #entries, 1G pages + l2_itlb_1g_assoc : 4, // L2 iTLB associativity, 1G pages + l2_dtlb_1g_nentries : 12, // L2 dTLB #entries, 1G pages + l2_dtlb_1g_assoc : 4; // L2 dTLB associativity, 1G pages + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001a + * AMD instruction optimizations + */ + +struct leaf_0x8000001a_0 { + // eax + u32 fp_128 : 1, // Internal FP/SIMD exec data path is 128-bits wide + movu_preferred : 1, // SSE: MOVU* better than MOVL*/MOVH* + fp_256 : 1, // internal FP/SSE exec data path is 256-bits wide + : 29; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001b + * AMD IBS (Instruction-Based Sampling) + */ + +struct leaf_0x8000001b_0 { + // eax + u32 ibs_flags : 1, // IBS feature flags + ibs_fetch_sampling : 1, // IBS fetch sampling + ibs_op_sampling : 1, // IBS execution sampling + ibs_rdwr_op_counter : 1, // IBS read/write of op counter + ibs_op_count : 1, // IBS OP counting mode + ibs_branch_target : 1, // IBS branch target address reporting + ibs_op_counters_ext : 1, // IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bi= ts + ibs_rip_invalid_chk : 1, // IBS invalid RIP indication + ibs_op_branch_fuse : 1, // IBS fused branch micro-op indication + ibs_fetch_ctl_ext : 1, // IBS Fetch Control Extended MSR + ibs_op_data_4 : 1, // IBS op data 4 MSR + ibs_l3_miss_filter : 1, // IBS L3-miss filtering (Zen4+) + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001c + * AMD LWP (Lightweight Profiling) + */ + +struct leaf_0x8000001c_0 { + // eax + u32 os_lwp_avail : 1, // OS: LWP is available to application programs + os_lpwval : 1, // OS: LWPVAL instruction + os_lwp_ire : 1, // OS: Instructions Retired Event + os_lwp_bre : 1, // OS: Branch Retired Event + os_lwp_dme : 1, // OS: Dcache Miss Event + os_lwp_cnh : 1, // OS: CPU Clocks Not Halted event + os_lwp_rnh : 1, // OS: CPU Reference clocks Not Halted event + : 22, // Reserved + os_lwp_cont : 1, // OS: LWP sampling in continuous mode + os_lwp_ptsc : 1, // OS: Performance Time Stamp Counter in event recor= ds + os_lwp_int : 1; // OS: Interrupt on threshold overflow + // ebx + u32 lwp_lwpcb_sz : 8, // Control Block size, in quadwords + lwp_event_sz : 8, // Event record size, in bytes + lwp_max_events : 8, // Max EventID supported + lwp_event_offset : 8; // Control Block events area offset + // ecx + u32 lwp_latency_max : 5, // Cache latency counters number of bits + lwp_data_addr : 1, // Cache miss events report data cache address + lwp_latency_rnd : 3, // Cache latency rounding amount + lwp_version : 7, // LWP version + lwp_buf_min_sz : 8, // LWP event ring buffer min size, 32 event recor= ds units + : 4, // Reserved + lwp_branch_predict : 1, // Branches Retired events can be filtered + lwp_ip_filtering : 1, // IP filtering (IPI, IPF, BaseIP, and LimitIP @= LWPCP) + lwp_cache_levels : 1, // Cache-related events: filter by cache level + lwp_cache_latency : 1; // Cache-related events: filter by latency + // edx + u32 hw_lwp_avail : 1, // HW: LWP available + hw_lpwval : 1, // HW: LWPVAL available + hw_lwp_ire : 1, // HW: Instructions Retired Event + hw_lwp_bre : 1, // HW: Branch Retired Event + hw_lwp_dme : 1, // HW: Dcache Miss Event + hw_lwp_cnh : 1, // HW: Clocks Not Halted event + hw_lwp_rnh : 1, // HW: Reference clocks Not Halted event + : 22, // Reserved + hw_lwp_cont : 1, // HW: LWP sampling in continuous mode + hw_lwp_ptsc : 1, // HW: Performance Time Stamp Counter in event recor= ds + hw_lwp_int : 1; // HW: Interrupt on threshold overflow +}; + +/* + * Leaf 0x8000001d + * AMD deterministic cache parameters + */ + +struct leaf_0x8000001d_n { + // eax + u32 cache_type : 5, // Cache type field + cache_level : 3, // Cache level (1-based) + cache_self_init : 1, // Self-initializing cache level + fully_associative : 1, // Fully-associative cache + : 4, // Reserved + num_threads_sharing : 12, // Number of logical CPUs sharing cache + : 6; // Reserved + // ebx + u32 cache_linesize : 12, // System coherency line size (0-based) + cache_npartitions : 10, // Physical line partitions (0-based) + cache_nways : 10; // Ways of associativity (0-based) + // ecx + u32 cache_nsets : 31, // Cache number of sets (0-based) + : 1; // Reserved + // edx + u32 wbinvd_rll_no_guarantee : 1, // WBINVD/INVD not guaranteed for Remo= te Lower-Level caches + ll_inclusive : 1, // Cache is inclusive of Lower-Level caches + : 30; // Reserved +}; + +#define LEAF_0x8000001d_SUBLEAF_N_FIRST 0 +#define LEAF_0x8000001d_SUBLEAF_N_LAST 31 + +/* + * Leaf 0x8000001e + * AMD CPU topology + */ + +struct leaf_0x8000001e_0 { + // eax + u32 ext_apic_id : 32; // Extended APIC ID + // ebx + u32 core_id : 8, // Unique per-socket logical core unit ID + core_nthreads : 8, // #Threads per core (zero-based) + : 16; // Reserved + // ecx + u32 node_id : 8, // Node (die) ID of invoking logical CPU + nnodes_per_socket : 3, // #nodes in invoking logical CPU's package/soc= ket + : 21; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001f + * AMD encrypted memory capabilities (SME/SEV) + */ + +struct leaf_0x8000001f_0 { + // eax + u32 sme : 1, // Secure Memory Encryption + sev : 1, // Secure Encrypted Virtualization + vm_page_flush : 1, // VM Page Flush MSR + sev_encrypted_state : 1, // SEV Encrypted State + sev_nested_paging : 1, // SEV secure nested paging + vm_permission_levels : 1, // VMPL + rpmquery : 1, // RPMQUERY instruction + vmpl_sss : 1, // VMPL supervisor shadow stack + secure_tsc : 1, // Secure TSC + virt_tsc_aux : 1, // Hardware virtualizes TSC_AUX + sme_coherent : 1, // Cache coherency enforcement across encryption do= mains + req_64bit_hypervisor : 1, // SEV guest mandates 64-bit hypervisor + restricted_injection : 1, // Restricted Injection supported + alternate_injection : 1, // Alternate Injection supported + debug_swap : 1, // SEV-ES: Full debug state swap + disallow_host_ibs : 1, // SEV-ES: Disallowing IBS use by the host + virt_transparent_enc : 1, // Virtual Transparent Encryption + vmgexit_parameter : 1, // SEV_FEATURES: VmgexitParameter + virt_tom_msr : 1, // Virtual TOM MSR + virt_ibs : 1, // SEV-ES guests: IBS state virtualization + : 4, // Reserved + vmsa_reg_protection : 1, // VMSA register protection + smt_protection : 1, // SMT protection + : 2, // Reserved + svsm_page_msr : 1, // SVSM communication page MSR + nested_virt_snp_msr : 1, // VIRT_RMPUPDATE/VIRT_PSMASH MSRs + : 2; // Reserved + // ebx + u32 pte_cbit_pos : 6, // PTE bit number to enable memory encryption + phys_addr_reduction_nbits : 6, // Reduction of phys address space in bi= ts + vmpl_count : 4, // Number of VM permission levels (VMPL) + : 16; // Reserved + // ecx + u32 enc_guests_max : 32; // Max number of simultaneous encrypted guests + // edx + u32 min_sev_asid_no_sev_es : 32; // Minimum ASID for SEV-enabled SEV-ES-= disabled guest +}; + +/* + * Leaf 0x80000020 + * AMD PQoS (Platform QoS) extended features + */ + +struct leaf_0x80000020_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 1, // Reserved + mba : 1, // Memory Bandwidth Allocation support + smba : 1, // Slow Memory Bandwidth Allocation support + bmec : 1, // Bandwidth Monitoring Event Configuration support + l3rr : 1, // L3 Range Reservation support + abmc : 1, // Assignable Bandwidth Monitoring Counters + sdciae : 1, // Smart Data Cache Injection (SDCI) Allocation Enforcem= ent + : 25; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x80000020_1 { + // eax + u32 mba_limit_len : 32; // MBA enforcement limit size + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 mba_cos_max : 32; // MBA max Class of Service number (zero-based) +}; + +struct leaf_0x80000020_2 { + // eax + u32 smba_limit_len : 32; // SMBA enforcement limit size + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 smba_cos_max : 32; // SMBA max Class of Service number (zero-based) +}; + +struct leaf_0x80000020_3 { + // eax + u32 : 32; // Reserved + // ebx + u32 bmec_num_events : 8, // BMEC number of bandwidth events available + : 24; // Reserved + // ecx + u32 bmec_local_reads : 1, // Local NUMA reads can be tracked + bmec_remote_reads : 1, // Remote NUMA reads can be tracked + bmec_local_nontemp_wr : 1, // Local NUMA non-temporal writes can be tr= acked + bmec_remote_nontemp_wr : 1, // Remote NUMA non-temporal writes can be = tracked + bmec_local_slow_mem_rd : 1, // Local NUMA slow-memory reads can be tra= cked + bmec_remote_slow_mem_rd : 1, // Remote NUMA slow-memory reads can be t= racked + bmec_all_dirty_victims : 1, // Dirty QoS victims to all types of memor= y can be tracked + : 25; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000021 + * AMD extended CPU features 2 + */ + +struct leaf_0x80000021_0 { + // eax + u32 no_nested_data_bp : 1, // No nested data breakpoints + fsgs_non_serializing : 1, // WRMSR to {FS,GS,KERNEL_GS}_BASE is non-se= rializing + lfence_serializing : 1, // LFENCE always serializing / synchronizes RD= TSC + smm_page_cfg_lock : 1, // SMM paging configuration lock + : 2, // Reserved + null_sel_clr_base : 1, // Null selector clears base + upper_addr_ignore : 1, // EFER MSR Upper Address Ignore + auto_ibrs : 1, // EFER MSR Automatic IBRS + no_smm_ctl_msr : 1, // SMM_CTL MSR not available + fsrs : 1, // Fast Short Rep STOSB + fsrc : 1, // Fast Short Rep CMPSB + : 1, // Reserved + prefetch_ctl_msr : 1, // Prefetch control MSR + : 2, // Reserved + opcode_reclaim : 1, // Reserves opcode space + user_cpuid_disable : 1, // #GP when executing CPUID at CPL > 0 + epsf : 1, // Enhanced Predictive Store Forwarding + : 3, // Reserved + wl_feedback : 1, // Workload-based heuristic feedback to OS + : 1, // Reserved + eraps : 1, // Enhanced Return Address Predictor Security + : 2, // Reserved + sbpb : 1, // Selective Branch Predictor Barrier + ibpb_brtype : 1, // Branch predictions flushed from CPU branch predic= tor + srso_no : 1, // No SRSO vulnerability + srso_uk_no : 1, // No SRSO at user-kernel boundary + srso_msr_fix : 1; // MSR BP_CFG[BpSpecReduce] SRSO mitigation + // ebx + u32 microcode_patch_size : 16, // Microcode patch size, in 16-byte units + rap_size : 8, // Return Address Predictor size + : 8; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000022 + * AMD extended performance monitoring + */ + +struct leaf_0x80000022_0 { + // eax + u32 perfmon_v2 : 1, // Performance monitoring v2 + lbr_v2 : 1, // Last Branch Record v2 extensions (LBR Stack) + lbr_pmc_freeze : 1, // Freezing core performance counters / LBR Stack + : 29; // Reserved + // ebx + u32 n_pmc_core : 4, // Number of core performance counters + lbr_v2_stack_size : 6, // Number of LBR stack entries + n_pmc_northbridge : 6, // Number of northbridge performance counters + n_pmc_umc : 6, // Number of UMC performance counters + : 10; // Reserved + // ecx + u32 active_umc_bitmask : 32; // Active UMCs bitmask + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000023 + * AMD multi-key encrypted memory + */ + +struct leaf_0x80000023_0 { + // eax + u32 mem_hmk_mode : 1, // MEM-HMK encryption mode + : 31; // Reserved + // ebx + u32 mem_hmk_avail_keys : 16, // Total number of available encryption keys + : 16; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000026 + * AMD extended CPU topology + */ + +struct leaf_0x80000026_n { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 24, // Reserved + core_has_pwreff_ranking : 1, // This core has a power efficiency ranki= ng + domain_has_hybrid_cores : 1, // This domain level has hybrid (E, P) co= res + domain_core_count_asymm : 1; // The 'Core' domain has asymmetric cores= count + // ebx + u32 domain_lcpus_count : 16, // Number of logical CPUs at this domain in= stance + core_pwreff_ranking : 8, // This core's static power efficiency ranking + core_native_model_id : 4, // This core's native model ID + core_type : 4; // This core's type + // ecx + u32 domain_level : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +#define LEAF_0x80000026_SUBLEAF_N_FIRST 0 +#define LEAF_0x80000026_SUBLEAF_N_LAST 3 + +/* + * Leaf 0x80860000 + * Maximum Transmeta leaf + CPU vendor string + */ + +struct leaf_0x80860000_0 { + // eax + u32 max_tra_leaf : 32; // Maximum Transmeta leaf + // ebx + u32 cpu_vendorid_0 : 32; // Transmeta Vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // Transmeta Vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // Transmeta Vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x80860001 + * Transmeta extended CPU features + */ + +struct leaf_0x80860001_0 { + // eax + u32 stepping : 4, // Stepping ID + base_model : 4, // Base CPU model ID + base_family_id : 4, // Base CPU family ID + cpu_type : 2, // CPU type + : 18; // Reserved + // ebx + u32 cpu_rev_mask_minor : 8, // CPU revision ID, mask minor + cpu_rev_mask_major : 8, // CPU revision ID, mask major + cpu_rev_minor : 8, // CPU revision ID, minor + cpu_rev_major : 8; // CPU revision ID, major + // ecx + u32 cpu_base_mhz : 32; // CPU nominal frequency, in MHz + // edx + u32 recovery : 1, // Recovery CMS is active (after bad flush) + longrun : 1, // LongRun power management capabilities + : 1, // Reserved + lrti : 1, // LongRun Table Interface + : 28; // Reserved +}; + +/* + * Leaf 0x80860002 + * Transmeta CMS (Code Morphing Software) + */ + +struct leaf_0x80860002_0 { + // eax + u32 cpu_rev_id : 32; // CPU revision ID + // ebx + u32 cms_rev_mask_2 : 8, // CMS revision ID, mask component 2 + cms_rev_mask_1 : 8, // CMS revision ID, mask component 1 + cms_rev_minor : 8, // CMS revision ID, minor + cms_rev_major : 8; // CMS revision ID, major + // ecx + u32 cms_rev_mask_3 : 32; // CMS revision ID, mask component 3 + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80860003 + * Transmeta CPU information string, bytes 0 - 15 + */ + +struct leaf_0x80860003_0 { + // eax + u32 cpu_info_0 : 32; // CPU info string bytes 0 - 3 + // ebx + u32 cpu_info_1 : 32; // CPU info string bytes 4 - 7 + // ecx + u32 cpu_info_2 : 32; // CPU info string bytes 8 - 11 + // edx + u32 cpu_info_3 : 32; // CPU info string bytes 12 - 15 +}; + +/* + * Leaf 0x80860004 + * Transmeta CPU information string, bytes 16 - 31 + */ + +struct leaf_0x80860004_0 { + // eax + u32 cpu_info_4 : 32; // CPU info string bytes 16 - 19 + // ebx + u32 cpu_info_5 : 32; // CPU info string bytes 20 - 23 + // ecx + u32 cpu_info_6 : 32; // CPU info string bytes 24 - 27 + // edx + u32 cpu_info_7 : 32; // CPU info string bytes 28 - 31 +}; + +/* + * Leaf 0x80860005 + * Transmeta CPU information string, bytes 32 - 47 + */ + +struct leaf_0x80860005_0 { + // eax + u32 cpu_info_8 : 32; // CPU info string bytes 32 - 35 + // ebx + u32 cpu_info_9 : 32; // CPU info string bytes 36 - 39 + // ecx + u32 cpu_info_10 : 32; // CPU info string bytes 40 - 43 + // edx + u32 cpu_info_11 : 32; // CPU info string bytes 44 - 47 +}; + +/* + * Leaf 0x80860006 + * Transmeta CPU information string, bytes 48 - 63 + */ + +struct leaf_0x80860006_0 { + // eax + u32 cpu_info_12 : 32; // CPU info string bytes 48 - 51 + // ebx + u32 cpu_info_13 : 32; // CPU info string bytes 52 - 55 + // ecx + u32 cpu_info_14 : 32; // CPU info string bytes 56 - 59 + // edx + u32 cpu_info_15 : 32; // CPU info string bytes 60 - 63 +}; + +/* + * Leaf 0x80860007 + * Transmeta live CPU information + */ + +struct leaf_0x80860007_0 { + // eax + u32 cpu_cur_mhz : 32; // Current CPU frequency, in MHz + // ebx + u32 cpu_cur_voltage : 32; // Current CPU voltage, in millivolts + // ecx + u32 cpu_cur_perf_pctg : 32; // Current CPU performance percentage, 0 - 1= 00 + // edx + u32 cpu_cur_gate_delay : 32; // Current CPU gate delay, in femtoseconds +}; + +/* + * Leaf 0xc0000000 + * Maximum Centaur/Zhaoxin leaf + */ + +struct leaf_0xc0000000_0 { + // eax + u32 max_cntr_leaf : 32; // Maximum Centaur/Zhaoxin leaf + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xc0000001 + * Centaur/Zhaoxin extended CPU features + */ + +struct leaf_0xc0000001_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 ccs_sm2 : 1, // CCS SM2 instructions + ccs_sm2_en : 1, // CCS SM2 enabled + rng : 1, // Random Number Generator + rng_en : 1, // RNG enabled + ccs_sm3_sm4 : 1, // CCS SM3 and SM4 instructions + ccs_sm3_sm4_en : 1, // CCS SM3/SM4 enabled + ace : 1, // Advanced Cryptography Engine + ace_en : 1, // ACE enabled + ace2 : 1, // Advanced Cryptography Engine v2 + ace2_en : 1, // ACE v2 enabled + phe : 1, // PadLock Hash Engine + phe_en : 1, // PHE enabled + pmm : 1, // PadLock Montgomery Multiplier + pmm_en : 1, // PMM enabled + : 2, // Reserved + parallax : 1, // Parallax auto adjust processor voltage + parallax_en : 1, // Parallax enabled + : 2, // Reserved + tm3 : 1, // Thermal Monitor v3 + tm3_en : 1, // TM v3 enabled + : 3, // Reserved + phe2 : 1, // PadLock Hash Engine v2 (SHA384/SHA512) + phe2_en : 1, // PHE v2 enabled + rsa : 1, // RSA instructions (XMODEXP/MONTMUL2) + rsa_en : 1, // RSA instructions enabled + : 3; // Reserved +}; + +#endif /* _ASM_X86_CPUID_LEAF_TYPES */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB04232A3F3 for ; Fri, 27 Mar 2026 02:17:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577875; cv=none; b=OOfzAFNoXyHr0umzYPYf1M1Y0pXHBJwzEk8DFJUtZ7fmaK0M9C57+VokTWJFVaWrlegUy/XoSYt6ohb4BvuDNC/nF2/I+U7zlYEbkPYhVfvuVZUUVp7NABhLUwPwQqm1prwhAiHsgNFGoUDdSYEHXiawyt00HeFCvJYRAEIMfVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577875; c=relaxed/simple; bh=rVkTMr5R6Wxj0UbHISjGJ5upTuaHwrJVub/XbqoRaPE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 08/90] x86: Introduce a centralized CPUID data model Date: Fri, 27 Mar 2026 03:15:22 +0100 Message-ID: <20260327021645.555257-9-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable ** Context The x86-cpuid-db project generates a C header file with full C99 bitfield listings for all known CPUID leaf/subleaf query outputs. That header is now merged by parent commits at , and is in the form: struct leaf_0x0_0 { /* CPUID(0x0).0 C99 bitfields */ }; ... struct leaf_0x4_n { /* CPUID(0x4).n C99 bitfields */ }; ... struct leaf_0xd_0 { /* CPUID(0xd).0 C99 bitfields */ }; struct leaf_0xd_1 { /* CPUID(0xd).1 C99 bitfields */ }; struct leaf_0xd_n { /* CPUID(0xd).n C99 bitfields */ }; ... ** Goal Introduce a structured, size-efficient, per-CPU, CPUID data repository. Use the x86-cpuid-db auto-generated data types, and custom CPUID leaf parsers, to build that repository. Given a leaf, subleaf, and index, provide direct memory access to the parsed and cached per-CPU CPUID output. ** Long-term goal Remove the need for drivers and other areas in the kernel to invoke direct CPUID queries. Only one place in the kernel should be allowed to use the CPUID instruction: the CPUID parser code. ** Implementation Introduce CPUID_LEAF()/CPUID_LEAF_N() to build a compact CPUID storage layout in the form: struct leaf_0x0_0 leaf_0x0_0[1]; struct leaf_parse_info leaf_0x0_0_info; struct leaf_0x1_0 leaf_0x1_0[1]; struct leaf_parse_info leaf_0x0_0_info; struct leaf_0x4_n leaf_0x4_n[8]; struct leaf_parse_info leaf_0x4_n_info; ... where each CPUID query stores its output at the designated leaf/subleaf array and has an associated "CPUID query info" structure. Embed the CPUID tables inside "struct cpuinfo_x86" to ensure early-boot and per-CPU access through the CPUs capability structures. Use an array of CPUID output storage entries for each leaf/subleaf combination to accommodate leaves which produce the same output format for a large subleaf range. This is typical for CPUID leaves enumerating hierarchical objects; e.g. CPUID(0x4) cache topology enumeration, CPUID(0xd) XSAVE enumeration, and CPUID(0x12) SGX Enclave Page Cache enumeration. ** New CPUID APIs Assuming a CPU capability structure 'c', provide macros to access the parsed and cached CPUID leaf/subleaf output. These macros resolve to a compile-time tokenization that ensures type-safety: const struct leaf_0x7_0 *l7_0; l7_0 =3D cpuid_subleaf(c, 0x7, 0); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * * &c.cpuid.leaf_0x7_0[0] For CPUID leaves with multiple subleaves having the same output format, provide the APIs: const struct leaf_0x4_n *l4_0, *l4_1; l4_0 =3D cpuid_subleaf_n(c, 0x4, 0); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_n[0] l4_1 =3D cpuid_subleaf_n(c, 0x4, 1); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_n[1] where the indices 0, 1, n above can be passed dynamically; e.g., in an enumeration for loop. Add a clear rationale on why call sites should use the these new APIs instead of directly invoking CPUID. ** Next steps For now, define cached parse entries for CPUID(0x0) and CPUID(0x1). Generic parser logic to fill the CPUID tables, along with more CPUID leaves support, will be added next. Suggested-by: Thomas Gleixner # CPUID data model Suggested-by: Andrew Cooper # x86-cpuid-db sche= ma Suggested-by: Borislav Petkov # Early CPUID centralization = drafts Suggested-by: Ingo Molnar # CPUID headers restructuring Suggested-by: Sean Christopherson # cpuid_subleaf_n() A= PIs Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/874ixernra.ffs@tglx Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db Link: https://lore.kernel.org/lkml/aBnSgu_JyEi8fvog@gmail.com Link: https://lore.kernel.org/lkml/aJ9TbaNMgaplKSbH@google.com --- arch/x86/include/asm/cpuid/api.h | 238 +++++++++++++++++++++++++++++ arch/x86/include/asm/cpuid/types.h | 98 ++++++++++++ arch/x86/include/asm/processor.h | 2 + 3 files changed, 338 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 2b9750cc8a75..b868902dbf5f 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -289,4 +289,242 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) return cpuid_edx(0x80000006); } =20 +/* + * 'struct cpuid_leaves' accessors (without sanity checks): + * + * For internal use by the CPUID parser. + */ + +/* Return constified pointers for all call-site APIs */ +#define __const_ptr(_ptr) \ + ((const __typeof__(*(_ptr)) *)(_ptr)) + +#define __cpuid_leaves_subleaf(_leaves, _leaf, _subleaf) \ + __const_ptr(&((_leaves)->leaf_ ## _leaf ## _ ## _subleaf)[0]) + +#define __cpuid_leaves_subleaf_n(_leaves, _leaf, _index) \ + __const_ptr(&((_leaves)->leaf_ ## _leaf ## _ ## n)[_index]) + +#define __cpuid_leaves_subleaf_info(_leaves, _leaf, _subleaf) \ + __const_ptr(&((_leaves)->leaf_ ## _leaf ## _ ## _subleaf ## _ ## info)) + +/* + * 'struct cpuid_table' accessors (with sanity checks): + * + * For internal use by the CPUID parser. + */ + +#define __cpuid_table_nr_filled_subleaves(_table, _leaf, _subleaf) \ + __cpuid_leaves_subleaf_info(&((_table)->leaves), _leaf, _subleaf)->nr_ent= ries + +#define __cpuid_table_subleaf_range_size(_table, _leaf) \ + ARRAY_SIZE((_table)->leaves.leaf_ ## _leaf ## _n) + +#define __cpuid_table_invalid_subleaf(_table, _leaf, _subleaf) \ + (((_subleaf) < (__cpuid_leaf_first_subleaf(_leaf))) || \ + ((_subleaf) > (__cpuid_leaf_first_subleaf(_leaf) + \ + __cpuid_table_subleaf_range_size(_table, _leaf) - 1))) + +/* Return NULL if the parser did not fill that leaf. Check cpuid_subleaf(= ). */ +#define __cpuid_table_subleaf(_table, _leaf, _subleaf) \ +({ \ + unsigned int ____f =3D __cpuid_table_nr_filled_subleaves(_table, _leaf, _= subleaf); \ + \ + (____f !=3D 1) ? NULL : __cpuid_leaves_subleaf(&((_table)->leaves), _leaf= , _subleaf); \ +}) + +/* + * Return NULL if the CPUID parser did not fill this leaf, or if the given + * dynamic subleaf value is out of range. Check cpuid_subleaf_n(). + */ +#define __cpuid_table_subleaf_n(_table, _leaf, _subleaf) \ +({ \ + unsigned int ____i =3D (_subleaf) - __cpuid_leaf_first_subleaf(_leaf); \ + unsigned int ____f =3D __cpuid_table_nr_filled_subleaves(_table, _leaf, n= ); \ + \ + /* CPUID parser might not have filled the entire subleaf range */ \ + ((____i >=3D ____f) || __cpuid_table_invalid_subleaf(_table, _leaf, _subl= eaf)) ? \ + NULL : __cpuid_leaves_subleaf_n(&((_table)->leaves), _leaf, ____i); \ +}) + +/* + * Compile-time checks for leaves with a subleaf range: + */ + +#define __cpuid_assert_subleaf_range(_cpuinfo, _leaf) \ + static_assert(__cpuid_table_subleaf_range_size(&(_cpuinfo)->cpuid, _leaf)= > 1) + +#define __cpuid_assert_subleaf_within_range(_cpuinfo, _leaf, _subleaf) \ + BUILD_BUG_ON(__builtin_constant_p(_subleaf) && \ + __cpuid_table_invalid_subleaf(&(_cpuinfo)->cpuid, _leaf, _subleaf)) + +/* + * CPUID Parser Call-site APIs + * + * Call sites should use below APIs instead of invoking direct CPUID queri= es. + * + * Benefits include: + * + * - Return CPUID output as typed C structures that are auto-generated fro= m a + * centralized database (see data type: 'struct leaf_0xM_N', wh= ere + * 0xM is the token provided at @_leaf, and N is the token provided at + * @_subleaf; e.g. struct leaf_0x7_0. + * + * Returns NULL if the requested CPUID @_leaf/@_subleaf query output is not + * present at the parsed CPUID table inside @_cpuinfo. This can happen if: + * + * - The CPUID table inside @_cpuinfo has not yet been populated. + * - The CPUID table inside @_cpuinfo was populated, but the CPU does not + * implement the requested CPUID @_leaf/@_subleaf combination. + * - The CPUID table inside @_cpuinfo was populated, but the kernel's CPUID + * parser has predetermined that the requested CPUID @_leaf/@_subleaf + * hardware output is invalid or unsupported. + * + * Example usage:: + * + * const struct leaf_0x7_0 *l7_0 =3D cpuid_subleaf(c, 0x7, 0); + * if (!l7_0) { + * // Handle error + * } + * + * const struct leaf_0x7_1 *l7_1 =3D cpuid_subleaf(c, 0x7, 1); + * if (!l7_1) { + * // Handle error + * } + */ +#define cpuid_subleaf(_cpuinfo, _leaf, _subleaf) \ + __cpuid_table_subleaf(&(_cpuinfo)->cpuid, _leaf, _subleaf) \ + +/** + * cpuid_leaf() - Access parsed CPUID data + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x0, 0x2, 0x800000= 00 + * + * Similar to cpuid_subleaf(), but with a CPUID subleaf =3D 0. + * + * Example usage:: + * + * const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + * if (!l0) { + * // Handle error + * } + * + * const struct leaf_0x80000000_0 *el0 =3D cpuid_leaf(c, 0x80000000); + * if (!el0) { + * // Handle error + * } + */ +#define cpuid_leaf(_cpuinfo, _leaf) \ + cpuid_subleaf(_cpuinfo, _leaf, 0) + +/** + * cpuid_leaf_raw() - Access parsed CPUID data in raw format + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format + * + * Similar to cpuid_leaf(), but returns a raw 'struct cpuid_regs' pointer = to + * the parsed CPUID data instead of a "typed" poi= nter. + */ +#define cpuid_leaf_raw(_cpuinfo, _leaf) \ + ((const struct cpuid_regs *)(cpuid_leaf(_cpuinfo, _leaf))) + +/* + * Call-site APIs for CPUID leaves with a subleaf range: + */ + +/** + * cpuid_subleaf_n() - Access parsed CPUID data for leaf with a subleaf ra= nge + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * @_subleaf: Subleaf number, which can be passed dynamically. It must be= smaller + * than cpuid_subleaf_count(@_cpuinfo, @_leaf). + * + * Build-time errors will be emitted in the following cases: + * + * - @_leaf has no subleaf range. Leaves with a subleaf range have an '_n= ' type + * suffix and are listed at using the CPUID_LEAF_N()= macro. + * + * - @_subleaf is known at compile-time but is out of range. + * + * Example usage:: + * + * const struct leaf_0x4_n *l4; + * + * for (int i =3D 0; i < cpuid_subleaf_count(c, 0x4); i++) { + * l4 =3D cpuid_subleaf_n(c, 0x4, i); + * if (!l4) { + * // Handle error + * } + * ... + * } + * + * Beside the standard error situations detailed at cpuid_subleaf(), this + * macro will also return NULL if @_subleaf is out of the leaf's subleaf r= ange. + */ +#define cpuid_subleaf_n(_cpuinfo, _leaf, _subleaf) \ +({ \ + __cpuid_assert_subleaf_range(_cpuinfo, _leaf); \ + __cpuid_assert_subleaf_within_range(_cpuinfo, _leaf, _subleaf); \ + __cpuid_table_subleaf_n(&(_cpuinfo)->cpuid, _leaf, _subleaf); \ +}) + +/** + * cpuid_subleaf_n_raw() - Access parsed CPUID data for leaf with subleaf = range + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * @_subleaf: Subleaf number, which can be passed dynamically. It must be= smaller + * than cpuid_subleaf_count(@_cpuinfo, @_leaf). + * + * Similar to cpuid_subleaf_n(), but returns a raw 'struct cpuid_regs' poi= nter to + * the parsed CPUID data instead of a "typed" poi= nter. + */ +#define cpuid_subleaf_n_raw(_cpuinfo, _leaf, _subleaf) \ + ((const struct cpuid_regs *)cpuid_subleaf_n(_cpuinfo, _leaf, _subleaf)) + +/** + * cpuid_subleaf_count() - Number of filled subleaves for @_leaf + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * + * Return the number of subleaves filled by the CPUID parser for @_leaf. + * + * @_leaf must have subleaf range. Leaves with a subleaf range have an '_= n' type + * suffix and are listed at using the CPUID_LEAF_N() m= acro. + */ +#define cpuid_subleaf_count(_cpuinfo, _leaf) \ +({ \ + __cpuid_assert_subleaf_range(_cpuinfo, _leaf); \ + __cpuid_table_nr_filled_subleaves(&(_cpuinfo)->cpuid, _leaf, n); \ +}) + #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 8a00364b79de..3d0e611c97ba 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -5,6 +5,8 @@ #include #include =20 +#include + /* * Types for raw CPUID access: */ @@ -30,6 +32,12 @@ enum cpuid_regs_idx { #define CPUID_LEAF_FREQ 0x16 #define CPUID_LEAF_TILE 0x1d =20 +#define CPUID_RANGE(idx) ((idx) & 0xffff0000) +#define CPUID_RANGE_MAX(idx) (CPUID_RANGE(idx) + 0xffff) + +#define CPUID_BASE_START 0x00000000 +#define CPUID_BASE_END CPUID_RANGE_MAX(CPUID_BASE_START) + /* * Types for CPUID(0x2) parsing: */ @@ -124,4 +132,94 @@ extern const struct leaf_0x2_table cpuid_0x2_table[256= ]; */ #define TLB_0x63_2M_4M_ENTRIES 32 =20 +/* + * Types for centralized CPUID tables: + * + * For internal use by the CPUID parser. + */ + +/** + * struct leaf_parse_info - CPUID query parse info + * @nr_entries: Number of valid entries filled by the CPUID parser + */ +struct leaf_parse_info { + unsigned int nr_entries; +}; + +/** + * __CPUID_LEAF() - Define a CPUID output and parse info entry + * @_name: Struct type name of the CPUID leaf/subleaf (e.g. 'leaf_0x7_0').= Such + * types are defined at and follow the leaf_0xM_N + * format, where 0xM is the leaf and N is the subleaf. + * @_count: Number of storage entries to allocate for this leaf/subleaf. + * + * For a given leaf/subleaf, define an array of CPUID storage entries and = an associated + * query info structure. + * + * Use an array of storage entries to accommodate CPUID leaves with multip= le subleaves + * having the same output format. This is common for hierarchical enumera= tion; e.g., + * CPUID(0x4), CPUID(0x12), and CPUID(0x8000001d). + */ +#define __CPUID_LEAF(_name, _count) \ + struct _name _name[_count]; \ + struct leaf_parse_info _name##_info + +/** + * CPUID_LEAF() - Define a 'struct cpuid_leaves' storage entry + * @_leaf: Leaf number, in compile-time 0xN format + * @_subleaf: Subleaf number, in compile-time decimal format + * + * Convenience wrapper around __CPUID_LEAF(). + */ +#define CPUID_LEAF(_leaf, _subleaf) \ + __CPUID_LEAF(leaf_ ## _leaf ## _ ## _subleaf, 1) + +#define __cpuid_leaf_first_subleaf(_l) \ + LEAF_ ## _l ## _ ## SUBLEAF_N_FIRST +#define __cpuid_leaf_last_subleaf(_l) \ + LEAF_ ## _l ## _ ## SUBLEAF_N_LAST + +#define __cpuid_leaf_subleaf_count_min(_l) 2 +#define __cpuid_leaf_subleaf_count_max(_l) \ + (__cpuid_leaf_last_subleaf(_l) - __cpuid_leaf_first_subleaf(_l) + 1) + +/** + * CPUID_LEAF_N() - Define a 'struct cpuid_leaves' storage entry + * @_leaf: Leaf number, in compile-time 0xN format + * @_count: Number of storage entries to allocate for that leaf. It must n= ot exceed + * the limits defined at . + * + * Convenience wrapper around __CPUID_LEAF(). + */ +#define CPUID_LEAF_N(_leaf, _count) \ + static_assert(_count >=3D __cpuid_leaf_subleaf_count_min(_leaf)); \ + static_assert(_count <=3D __cpuid_leaf_subleaf_count_max(_leaf)); \ + __CPUID_LEAF(leaf_ ## _leaf ## _ ## n, _count) + +/* + * struct cpuid_leaves - Parsed CPUID data + */ +struct cpuid_leaves { + /* Leaf Subleaf number (or max number of subleaves) */ + CPUID_LEAF ( 0x0, 0 ); + CPUID_LEAF ( 0x1, 0 ); +}; + +/* + * Types for centralized CPUID tables: + * + * For external use. + */ + +/** + * struct cpuid_table - Per-CPU CPUID data repository + * @leaves: Parsed CPUID queries output and their metadata + * + * This is to be embedded inside 'struct cpuinfo_x86' to provide parsed and + * sanitized CPUID data per CPU. + */ +struct cpuid_table { + struct cpuid_leaves leaves; +}; + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index bea05fea5729..5ee0dcbd548c 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -16,6 +16,7 @@ struct vm86; #include #include #include +#include #include #include #include @@ -164,6 +165,7 @@ struct cpuinfo_x86 { char x86_vendor_id[16]; char x86_model_id[64]; struct cpuinfo_topology topo; + struct cpuid_table cpuid; /* in KB - valid for CPUS which support this call: */ unsigned int x86_cache_size; int x86_cache_alignment; /* In bytes */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3C443328E3 for ; Fri, 27 Mar 2026 02:17:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577879; cv=none; b=ThD19psfzBi71ikKpJ6AiIGU92x9MU49vmg1+E/nBSh0YichkPfQyAEcZN0LWfO13IeGWVQ9j1nl1GcdQe4Z4h5LXcJPF6Uzf2bjhlfgShlKZj3JMUpbHzgKONKcBOjF37DwvHONTgKv0PUewSIQ8UWf3xZ9k66dnARwUDN4KlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577879; c=relaxed/simple; bh=3DHM/LBZ8RbQDdmgFQWbIXYODtS/hSJWe0Fgzks1ZX0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VRgozAw753IJlvezzjkU66M/N1EvRBPPekjZrvQoQRc5Tzv3uj19YQqNfOxjW8KWZ6ARksq5liC4YvnkwTucfqjzMaQITB/CjlBndJlpk2S1tnfzoyjx5EX1rXNG8xOckRO4DPGYyrpCrgBfk39G43yDCApSURIX7aCT8nlS9WI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XIfeeMeU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hrpZNfZN; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XIfeeMeU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hrpZNfZN" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 09/90] x86/cpuid: Introduce a centralized CPUID parser Date: Fri, 27 Mar 2026 03:15:23 +0100 Message-ID: <20260327021645.555257-10-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a CPUID parser for populating the system's CPUID tables. Since accessing a leaf within the CPUID table requires compile time tokenization, split the parser into two stages: (a) Compile-time macros for tokenizing the leaf/subleaf offsets within the CPUID table. (b) Generic runtime code to fill the CPUID data, using a parsing table which collects these compile-time offsets. For actual CPUID output parsing, support both generic and leaf-specific read functions. To ensure CPUID data early availability, invoke the parser during early boot, early Xen boot, and at early secondary CPUs bring up. Provide call site APIs to refresh a single leaf, or a leaf range, within the CPUID tables. This is for sites issuing MSR writes that partially changes the CPU's CPUID layout. Doing full CPUID table rescans in such cases will be destructive since the CPUID tables will host all of the kernel's X86_FEATURE flags at a later stage. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 9 ++ arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/common.c | 5 +- arch/x86/kernel/cpu/cpuid_parser.c | 182 +++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 120 +++++++++++++++++++ arch/x86/xen/enlighten.c | 3 +- arch/x86/xen/enlighten_pv.c | 1 + 7 files changed, 319 insertions(+), 2 deletions(-) create mode 100644 arch/x86/kernel/cpu/cpuid_parser.c create mode 100644 arch/x86/kernel/cpu/cpuid_parser.h diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index b868902dbf5f..82eddfa2347b 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -7,6 +7,7 @@ #include #include =20 +#include #include =20 /* @@ -527,4 +528,12 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) __cpuid_table_nr_filled_subleaves(&(_cpuinfo)->cpuid, _leaf, n); \ }) =20 +/* + * CPUID parser exported APIs: + */ + +void cpuid_scan_cpu(struct cpuinfo_x86 *c); +void cpuid_refresh_leaf(struct cpuinfo_x86 *c, u32 leaf); +void cpuid_refresh_range(struct cpuinfo_x86 *c, u32 start, u32 end); + #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 2f8a58ef690e..d2e8a849f180 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -19,6 +19,7 @@ KCSAN_SANITIZE_common.o :=3D n =20 obj-y :=3D cacheinfo.o scattered.o obj-y +=3D topology_common.o topology_ext.o topology_amd.o +obj-y +=3D cpuid_parser.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a8ff4376c286..303faa612a6c 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1775,6 +1775,7 @@ static void __init cpu_parse_early_param(void) static void __init early_identify_cpu(struct cpuinfo_x86 *c) { memset(&c->x86_capability, 0, sizeof(c->x86_capability)); + memset(&c->cpuid, 0, sizeof(c->cpuid)); c->extended_cpuid_level =3D 0; =20 if (!cpuid_feature()) @@ -1782,6 +1783,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) =20 /* cyrix could have cpuid enabled via c_identify()*/ if (cpuid_feature()) { + cpuid_scan_cpu(c); cpu_detect(c); get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); @@ -1954,8 +1956,8 @@ static void generic_identify(struct cpuinfo_x86 *c) if (!cpuid_feature()) return; =20 + cpuid_scan_cpu(c); cpu_detect(c); - get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); get_cpu_cap(c); @@ -2007,6 +2009,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) #endif c->x86_cache_alignment =3D c->x86_clflush_size; memset(&c->x86_capability, 0, sizeof(c->x86_capability)); + memset(&c->cpuid, 0, sizeof(c->cpuid)); #ifdef CONFIG_X86_VMX_FEATURE_NAMES memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); #endif diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c new file mode 100644 index 000000000000..898b0c441431 --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * CPUID parser; for populating the system's CPUID tables. + */ + +#include + +#include +#include + +#include "cpuid_parser.h" + +/* Clear a single CPUID table entry */ +static void cpuid_clear(const struct cpuid_parse_entry *e, const struct cp= uid_read_output *output) +{ + struct cpuid_regs *regs =3D output->regs; + + for (int i =3D 0; i < e->maxcnt; i++, regs++) + memset(regs, 0, sizeof(*regs)); + + memset(output->info, 0, sizeof(*output->info)); +} + +/* + * Leaf read functions: + */ + +/* + * Default CPUID read function + * Satisfies the requirements stated at 'struct cpuid_parse_entry'->read(). + */ +static void +cpuid_read_generic(const struct cpuid_parse_entry *e, const struct cpuid_r= ead_output *output) +{ + struct cpuid_regs *regs =3D output->regs; + + for (int i =3D 0; i < e->maxcnt; i++, regs++, output->info->nr_entries++) + cpuid_read_subleaf(e->leaf, e->subleaf + i, regs); +} + +/* + * CPUID parser table: + */ + +static const struct cpuid_parse_entry cpuid_parse_entries[] =3D { + CPUID_PARSE_ENTRIES +}; + +/* + * Leaf-independent parser code: + */ + +static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsi= gned int range) +{ + const struct leaf_0x0_0 *l0 =3D __cpuid_table_subleaf(t, 0x0, 0); + + switch (range) { + case CPUID_BASE_START: return l0 ? l0->max_std_leaf : 0; + default: return 0; + } +} + +static void +__cpuid_reset_table(struct cpuid_table *t, const struct cpuid_parse_entry = entries[], + unsigned int nr_entries, unsigned int start, unsigned int end, bool = fill) +{ + const struct cpuid_parse_entry *entry =3D entries; + unsigned int range =3D CPUID_RANGE(start); + + for (unsigned int i =3D 0; i < nr_entries; i++, entry++) { + struct cpuid_read_output output =3D { + .regs =3D cpuid_table_regs_p(t, entry->regs_offs), + .info =3D cpuid_table_info_p(t, entry->info_offs), + }; + + if (entry->leaf < start || entry->leaf > end) + continue; + + cpuid_clear(entry, &output); + + /* + * Read the range's anchor leaf unconditionally so that the cached + * maximum valid leaf value is available for the remaining entries. + */ + if (fill && (entry->leaf =3D=3D range || entry->leaf <=3D cpuid_range_ma= x_leaf(t, range))) + entry->read(entry, &output); + } +} + +/* + * Zero all cached CPUID entries within [@start-@end] range. This is need= ed when + * certain operations like MSR writes induce changes to the CPU's CPUID la= yout. + */ +static void +__cpuid_zero_table(struct cpuid_table *t, const struct cpuid_parse_entry e= ntries[], + unsigned int nr_entries, unsigned int start, unsigned int end) +{ + __cpuid_reset_table(t, entries, nr_entries, start, end, false); +} + +static void +__cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry e= ntries[], + unsigned int nr_entries, unsigned int start, unsigned int end) +{ + __cpuid_reset_table(t, entries, nr_entries, start, end, true); +} + +static void +cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry ent= ries[], unsigned int nr_entries) +{ + static const struct { + unsigned int start; + unsigned int end; + } ranges[] =3D { + { CPUID_BASE_START, CPUID_BASE_END }, + }; + + for (unsigned int i =3D 0; i < ARRAY_SIZE(ranges); i++) + __cpuid_fill_table(t, entries, nr_entries, ranges[i].start, ranges[i].en= d); +} + +static void __cpuid_scan_cpu_full(struct cpuinfo_x86 *c) +{ + unsigned int nr_entries =3D ARRAY_SIZE(cpuid_parse_entries); + struct cpuid_table *table =3D &c->cpuid; + + cpuid_fill_table(table, cpuid_parse_entries, nr_entries); +} + +static void +__cpuid_scan_cpu_partial(struct cpuinfo_x86 *c, unsigned int start_leaf, u= nsigned int end_leaf) +{ + unsigned int nr_entries =3D ARRAY_SIZE(cpuid_parse_entries); + struct cpuid_table *table =3D &c->cpuid; + + __cpuid_zero_table(table, cpuid_parse_entries, nr_entries, start_leaf, en= d_leaf); + __cpuid_fill_table(table, cpuid_parse_entries, nr_entries, start_leaf, en= d_leaf); +} + +/* + * Call-site APIs: + */ + +/** + * cpuid_scan_cpu() - Populate current CPU's CPUID table + * @c: CPU capability structure associated with the current CPU + * + * Populate the CPUID table embedded within @c with parsed CPUID data. Al= l CPUID + * instructions are invoked locally, so this must be called on the CPU ass= ociated + * with @c. + */ +void cpuid_scan_cpu(struct cpuinfo_x86 *c) +{ + __cpuid_scan_cpu_full(c); +} + +/** + * cpuid_refresh_range() - Rescan a CPUID table's leaf range + * @c: CPU capability structure associated with the current CPU + * @start: Start of leaf range to be re-scanned + * @end: End of leaf range + */ +void cpuid_refresh_range(struct cpuinfo_x86 *c, u32 start, u32 end) +{ + if (WARN_ON_ONCE(start > end)) + return; + + if (WARN_ON_ONCE(CPUID_RANGE(start) !=3D CPUID_RANGE(end))) + return; + + __cpuid_scan_cpu_partial(c, start, end); +} + +/** + * cpuid_refresh_leaf() - Rescan a CPUID table's leaf + * @c: CPU capability structure associated with the current CPU + * @leaf: Leaf to be re-scanned + */ +void cpuid_refresh_leaf(struct cpuinfo_x86 *c, u32 leaf) +{ + cpuid_refresh_range(c, leaf, leaf); +} diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h new file mode 100644 index 000000000000..df627306cc8c --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ARCH_X86_CPUID_PARSER_H +#define _ARCH_X86_CPUID_PARSER_H + +#include + +/* + * Since accessing the CPUID leaves at 'struct cpuid_leaves' require compi= le time + * tokenization, split the CPUID parser into two stages: compile time macr= os for + * tokenizing the leaf/subleaf output offsets within the table, and generi= c runtime + * code to write to the relevant CPUID leaves using such offsets. + * + * The output of the compile time macros is cached by a compile time "pars= e entry" + * table (see 'struct cpuid_parse_entry'). The runtime parser code will u= tilize + * such offsets by passing them to the cpuid_table_*_p() functions. + */ + +/* + * Compile time CPUID table offset calculations: + * + * @_leaf: CPUID leaf, in 0xN format + * @_subleaf: CPUID subleaf, in decimal format + */ + +#define __cpuid_leaves_regs_offset(_leaf, _subleaf) \ + offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf) + +#define __cpuid_leaves_info_offset(_leaf, _subleaf) \ + offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf ## _ ## inf= o) + +#define __cpuid_leaves_regs_maxcnt(_leaf, _subleaf) \ + ARRAY_SIZE(((struct cpuid_leaves *)NULL)->leaf_ ## _leaf ## _ ## _subleaf) + +/* + * Translation of compile time offsets to generic runtime pointers: + */ + +static inline struct cpuid_regs * +cpuid_table_regs_p(const struct cpuid_table *t, unsigned long regs_offset) +{ + return (struct cpuid_regs *)((unsigned long)(&t->leaves) + regs_offset); +} + +static inline struct leaf_parse_info * +cpuid_table_info_p(const struct cpuid_table *t, unsigned long info_offset) +{ + return (struct leaf_parse_info *)((unsigned long)(&t->leaves) + info_offs= et); +} + +/** + * struct cpuid_read_output - Output of a CPUID read operation + * @regs: Pointer to an array of CPUID outputs, where each array element c= overs the + * full EAX->EDX output range. + * @info: Pointer to query info; for saving the number of filled elements = at @regs. + * + * A CPUID parser read function like cpuid_read_generic() or cpuid_read_0x= N() uses this + * structure to save the CPUID query outputs. Actual storage for @regs an= d @info is + * provided by the read function caller, and is typically within the CPU's= CPUID table. + * + * See struct cpuid_parse_entry.read(). + */ +struct cpuid_read_output { + struct cpuid_regs *regs; + struct leaf_parse_info *info; +}; + +/** + * struct cpuid_parse_entry - CPUID parse table entry + * @leaf: Leaf number to be parsed + * @subleaf: Subleaf number to be parsed + * @regs_offs: Offset within 'struct cpuid_leaves' for saving the CPUID qu= ery output; to be + * passed to cpuid_table_regs_p(). + * @info_offs: Offset within 'struct cpuid_leaves' for saving the CPUID qu= ery parse info; to be + * passed to cpuid_table_info_p(). + * @maxcnt: Maximum number of output storage entries available for the CPU= ID query. + * @read: Read function for this entry. It must save the parsed CPUID out= put to the passed + * 'struct cpuid_read_output'->regs array of size >=3D @maxcnt. It must = set + * 'struct cpuid_read_output'->info.nr_entries to the number of CPUID out= put entries + * parsed and filled. A generic implementation is provided at cpuid_read= _generic(). + */ +struct cpuid_parse_entry { + unsigned int leaf; + unsigned int subleaf; + unsigned int regs_offs; + unsigned int info_offs; + unsigned int maxcnt; + void (*read)(const struct cpuid_parse_entry *e, const struct cpuid_read_= output *o); +}; + +#define __CPUID_PARSE_ENTRY(_leaf, _subleaf, _suffix, _reader_fn) \ + { \ + .leaf =3D _leaf, \ + .subleaf =3D _subleaf, \ + .regs_offs =3D __cpuid_leaves_regs_offset(_leaf, _suffix), \ + .info_offs =3D __cpuid_leaves_info_offset(_leaf, _suffix), \ + .maxcnt =3D __cpuid_leaves_regs_maxcnt(_leaf, _suffix), \ + .read =3D cpuid_read_ ## _reader_fn, \ + } + +/* + * CPUID_PARSE_ENTRY_N() is for parsing CPUID leaves with a subleaf range. + * Check __CPUID_LEAF() vs. CPUID_LEAF_N(). + */ + +#define CPUID_PARSE_ENTRY(_leaf, _subleaf, _reader_fn) \ + __CPUID_PARSE_ENTRY(_leaf, _subleaf, _subleaf, _reader_fn) + +#define CPUID_PARSE_ENTRY_N(_leaf, _reader_fn) \ + __CPUID_PARSE_ENTRY(_leaf, __cpuid_leaf_first_subleaf(_leaf), n, _reader_= fn) + +/* + * CPUID parser table: + */ + +#define CPUID_PARSE_ENTRIES \ + /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY ( 0x0, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x1, 0, generic ), \ + +#endif /* _ARCH_X86_CPUID_PARSER_H */ diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index 23b91bf9b663..cf061ed45ce8 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -17,7 +17,7 @@ #include #include #include -#include =20 +#include #include =20 #include "xen-ops.h" @@ -76,6 +76,7 @@ unsigned long xen_released_pages; static __ref void xen_get_vendor(void) { init_cpu_devs(); + cpuid_scan_cpu(&boot_cpu_data); cpu_detect(&boot_cpu_data); get_cpu_vendor(&boot_cpu_data); } diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index eaad22b47206..033b09714d48 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1433,6 +1433,7 @@ asmlinkage __visible void __init xen_start_kernel(str= uct start_info *si) xen_build_dynamic_phys_to_machine(); =20 /* Work out if we support NX */ + cpuid_scan_cpu(&boot_cpu_data); get_cpu_cap(&boot_cpu_data); x86_configure_nx(); =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0977832F748 for ; Fri, 27 Mar 2026 02:18:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577881; cv=none; b=qbysjqCt/2FfJjui7O40tBRFHqigkA3V9Sc+USObYLmEz+yV77TSZfJURpyjfhR5JvElQnzWYVPJ6a1ibyjn2pdiuh1xX4cVUA45Syosa/oW38d96LEZHaEvhnGjpMyl8SMiQTv2yV/FiXKJMxD1O7DCO3H/HiRf2OpgrJMnpbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577881; c=relaxed/simple; bh=jHpSDCkzZ+YS/XwpSke6UM5tl7cnzN3YqQW6FkxZ7Kg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QosmvieFqyzQmYY27PULUPyoIWE1cqdMfgKc3J1IezS7QWJ54KUMRhoFsu54tcNIw6mCVDyAhKSOpNoWg5KgfvF9zmjdbwM4aE7A0q2Z44y/+owaamxod4Suw4v5ORU84cIvoMnpdUPU7M7mOplPHt7zMjumHvCv404POmUcRI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EH5+RYpI; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=t4wjpd9W; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EH5+RYpI"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="t4wjpd9W" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577878; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+LbBgZnLJZy22gGEEaQmFxt6EbKenQxGFTaae9eknmU=; b=EH5+RYpICMl+V/4yDLzXSPdmvKqwO3gKy5eCZYKmjsFl3JSwvNA04aUHRNjnyWT7V/qfAA dL9kmz6nTEwh8KLE5xTMkBVnyBnPbligU2tpvcY5hIVCTiHgU5vf2KBCaiRtihAGIG9Yqn 6OjDI9SlUkUK0agJtFnU2mrIrUuv1VWj86EDB2ADo0MkT+zfzX+hlNgy+2qakE1VlrsMfA VH5fuFgemb95ZhCHC4O46xgxc+/P7NonkC1ohJ0oHz06Lem+FC+qtoRB5cDEuC7hiGYZOv kqaHENdLNYaXV4o4VyZ/AXALfHtURxwZcZ9I1jnq1zPspywRL/hJVf5pLXLR4g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577878; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+LbBgZnLJZy22gGEEaQmFxt6EbKenQxGFTaae9eknmU=; b=t4wjpd9WJNTBkJyaniI3a+22ZZG1HCA4MfMH0RIvWzigN+pmkR/r8ZFodCztZFEvMOK6HB ZNfl909DjOnXx1DQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 10/90] x86/cpu: Rescan CPUID table after disabling PSN Date: Fri, 27 Mar 2026 03:15:24 +0100 Message-ID: <20260327021645.555257-11-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Pentium-III and Transmeta CPUs, disabling the CPUID(0x3) Processor Serial Number (PSN) can affect the maximum valid CPUID standard leaf. Rescan the CPU's CPUID table in that case not to have stale cached data. Rescan only the changed CPUID leaves, not to override any of the kernel's previously force-set or unset cached CPUID bits. Rename squash_the_stupid_serial_number() to disable_cpu_serial_number() and explain the rationale behind disabling the CPU's PSN. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 303faa612a6c..8fd7d2f480bf 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -336,15 +336,19 @@ bool cpuid_feature(void) return flag_is_changeable_p(X86_EFLAGS_ID); } =20 -static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) +/* + * For privacy concerns, disable legacy Intel and Transmeta CPUID(0x3) + * feature, Processor Serial Number, by default. + */ +static void disable_cpu_serial_number(struct cpuinfo_x86 *c) { + const struct leaf_0x0_0 *l0; + unsigned int rescan_from; unsigned long lo, hi; =20 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) return; =20 - /* Disable processor serial number: */ - rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); lo |=3D 0x200000; wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); @@ -352,8 +356,18 @@ static void squash_the_stupid_serial_number(struct cpu= info_x86 *c) pr_notice("CPU serial number disabled.\n"); clear_cpu_cap(c, X86_FEATURE_PN); =20 - /* Disabling the serial number may affect the cpuid level */ - c->cpuid_level =3D cpuid_eax(0); + /* + * Disabling CPUID(0x3) can change the maximum standard CPUID level + */ + + cpuid_refresh_leaf(c, 0x0); + l0 =3D cpuid_leaf(c, 0x0); + if (!l0) + return; + + rescan_from =3D min_t(int, l0->max_std_leaf, c->cpuid_level) + 1; + cpuid_refresh_range(c, rescan_from, CPUID_BASE_END); + c->cpuid_level =3D l0->max_std_leaf; } =20 static int __init x86_serial_nr_setup(char *s) @@ -363,7 +377,7 @@ static int __init x86_serial_nr_setup(char *s) } __setup("serialnumber", x86_serial_nr_setup); #else -static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) +static inline void disable_cpu_serial_number(struct cpuinfo_x86 *c) { } #endif @@ -2046,7 +2060,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) bus_lock_init(); =20 /* Disable the PN if appropriate */ - squash_the_stupid_serial_number(c); + disable_cpu_serial_number(c); =20 setup_smep(c); setup_smap(c); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84AC633B6E3 for ; Fri, 27 Mar 2026 02:18:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577884; cv=none; b=Py8UqUnXqMN5fw5MwfQW7ICAhofxgTp8L90wCvokHO0gQ+Bb2NK8Bb1CE79qSygYcXd0yT0BS50tFY5UQspYz8FEzMSF6VVKenoNn+dasrfbWgxQppmJaZyHp/ew2fdm49rmPJzsLYZFCukLeJ8toy6uqJqf/lI2oukLHgMBosY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577884; c=relaxed/simple; bh=RoP2lKI84iP9j0jV0ffR/MG7Quj+LKMigM9fxgmDHAM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uv0jmxPGkcA8OGCN2UzQZWWm96gFEVxZDVV7GuzAvZMD//rQhYBYt66uH/IiK+VhjoOSEsXPYNBRJEjAVp0hGIzsIljCnleF5OJTb4E2irBQbhr1507hN4YAHhyIEc9ouGwFcCEu5BbNrjT3LNEuex0vNd+XIuOWWrrUAvI53vk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wRiLpzNB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XIdVUW1l; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wRiLpzNB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XIdVUW1l" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577881; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sml/7Y54i5S3ALNBOmu5um8G3+0GTHqkR9Tkf95GOBA=; b=wRiLpzNBpDKR4ZmA1hjGdV978BTnZargKD51BilK/ocjhuZiYkbKlmc4tpjW3w4HJiMRoa V8eYlI312N4nG0R4XWhNJ+TsvOUNLn8lderAldcYq5UIDK63Y9A5TCyTqirYASFFW5hCcm YVzxer8Css48JP1qerI6GWap5f8cnzfqrfV7GlrrnRlVyVNRfgPi+1yqZkyclg/Y7m+7x2 +Gh/wrZS3XFHfI9DmeyA2cpsWyvpHD8VcdzbeY6aWQFAHR7NFrTxY0Xk573CP7JUHJUURp NknGHgBBXzJ0nhY/Mo9IFAi3cmF4tSD/JNJg7ZnDmR7eerUj+iJTVRPZ1I63DQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577881; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sml/7Y54i5S3ALNBOmu5um8G3+0GTHqkR9Tkf95GOBA=; b=XIdVUW1lJgyZl4ZaJeB093rl7gS0tckXKob42smyRsK2Z72sIPwrgLqt8k65WH667MydCS i5tq0QGUqf20A1DA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 11/90] x86/cpu: centaur/zhaoxin: Rescan CPUID(0xc0000001) after MSR writes Date: Fri, 27 Mar 2026 03:15:25 +0100 Message-ID: <20260327021645.555257-12-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Force-enabling Centaur/Zhaoxin CPU features through MSR writes leads to the CPUID(0xc0000001) EDX feature flags getting changed. Rescan CPUID(0xc0000001) in that case. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 6 ++++-- arch/x86/kernel/cpu/zhaoxin.c | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 681d2da49341..a97e38fa6a9f 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -44,9 +44,11 @@ static void init_c3(struct cpuinfo_x86 *c) pr_info("CPU: Enabled h/w RNG\n"); } =20 - /* store Centaur Extended Feature Flags as - * word 5 of the CPU capability bit array + /* + * Force-enabling CPU features affects the CPUID(0xc0000001) + * EDX feature bits. Refresh the leaf. */ + cpuid_refresh_leaf(c, 0xc0000001); c->x86_capability[CPUID_C000_0001_EDX] =3D cpuid_edx(0xC0000001); } #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 761aef5590ac..55bc656aaa95 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -46,9 +46,10 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c) } =20 /* - * Store Extended Feature Flags as word 5 of the CPU - * capability bit array + * Force-enabling CPU features affects the CPUID(0xc0000001) + * EDX feature bits. Refresh the leaf. */ + cpuid_refresh_leaf(c, 0xc0000001); c->x86_capability[CPUID_C000_0001_EDX] =3D cpuid_edx(0xC0000001); } =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B10233D4E1 for ; Fri, 27 Mar 2026 02:18:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577888; cv=none; b=hcJ741JmPfvKstjbDYSCsnFN96n1fgQ8UDwRm3bYI+H1LHsMSjgXW+hhJQep4/ONjSUGajrzsznqQFREDMvobCxxTl9pt2BRzz2RoUsQXRkmX4HiEMAsedFaOy1vR2kp837z9dNy2Dn5iVk+qJ64PwaBe6IHVFAXPXKasprM68Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577888; c=relaxed/simple; bh=vS1LWMmypAy8nihrfer1FMBqTVZgK2kYFbyeCeGwTSo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jtLamWGi/xO8qCScHTOn3kchBCcf8PFx2O6a/qlcBvCY+GdLKxEGOR+kHzO2dJCneJ8oG49EpgsY2ZCCSJK/TWYVx5iJjzcFL87V42Zp0BEc6k/9k1hzxYlnH/WUHTU29jdmF39SX6ksnsh+nJaTxYk0TWp6/E4N41oJ1EMAInQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Xb8Ppheh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=1Ka4FE2g; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Xb8Ppheh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="1Ka4FE2g" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IAp+kfoshU4h8p4hqAmtOn1a7SUaBK7HvvMUmE8dfwc=; b=Xb8PphehIJ1qyZe/4TxIu4pqR5UHIzSlFT366NmPYVRLGVMW6fzxxkCsfl+t2paOQY1kW+ N2ooCkDRH47fB46A+ZysmpRsNuUy6M0xDtE5+dT+bGf1uoZhMf0+fUmurexcm2AvyLGyNr 7cUcispYTBesZ6C+sLkfJ2W5iZLB3wVOizAYHKxUc4dOGyLNX+6KWsbUsLUs1QRMk3SZiS i1jyJI8sTYExOCqar7bKBp5/XLBECFqiC1a+4kmlFu0AHjAROFTZFeQ08CDf8KUvXrX0+Y wKSV2jC86LtTTAaVFN78fabjOA62d5D9NsMIF8L5TuZhzY4LlF8cr8tfp2eKAQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IAp+kfoshU4h8p4hqAmtOn1a7SUaBK7HvvMUmE8dfwc=; b=1Ka4FE2gxsrtjKWvhBsCl2T+T2TMyrLvdNDpcnRBEQUShk/VGeqgl+WNFiISWff3/24O5d MtqBN75c8RXcLLBA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 12/90] x86/cpu/transmeta: Rescan CPUID(0x1) after capability unhide Date: Fri, 27 Mar 2026 03:15:26 +0100 Message-ID: <20260327021645.555257-13-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Transmeta CPUs allow masking CPUID(0x1).EDX feature flags via MSR writes. If a bit is cleared in the 0x80860004 MSR, its corresponding feature flag is not reported by CPUID. Refresh the CPUID parser's CPUID(0x1) cache while all of that MSR bits are unmasked. Note, the MSR 0x80860004 semantics are documented at the "BIOS Programmer's Guide: Transmeta Crusoe Processor", dated June 14, 2002. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/transmeta.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmet= a.c index 1fdcd69c625c..d9e0edb379b8 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -88,6 +88,7 @@ static void init_transmeta(struct cpuinfo_x86 *c) /* Unhide possibly hidden capability flags */ rdmsr(0x80860004, cap_mask, uk); wrmsr(0x80860004, ~0, uk); + cpuid_refresh_leaf(c, 0x1); c->x86_capability[CPUID_1_EDX] =3D cpuid_edx(0x00000001); wrmsr(0x80860004, cap_mask, uk); =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D33F433E348 for ; Fri, 27 Mar 2026 02:18:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577891; cv=none; b=A3w947S3X9KMQ28YUSRzXPHYjYzZSFyUxp/GWbaMwwJijWHDs3RZQ2BdF9fPVWp9UenTPMb9L84mfiTH/Qk5K56/q7aqJsdZGlJT3ujm2VG/3+GzjksykG50XKvFJuY7wpv61grsKEHYLheG0ZD+ggY2c0R51EWHyfnOFpTv2Nc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577891; c=relaxed/simple; bh=0anUBszkYETNsFvKFDaZ+ZJMseXEuUeoVKu2SapGjRw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZJHllrs9Zrjq4FssX/W7vxtXiJ3Ai/Y3duTR9nDEreZU+33aTbCIJR/+fmqEZZONAgZOpegkgOidl2YCQLrO5ZhCidw9ulu5ucG0vasNMbJJz5Q3q/JXUbzWuKYjAX9IXPpMWHUcLsicx5u9A1AH0VvSGd9pz5FvMuKN3HltZBU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fFG4l1zt; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sAV2BtPY; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fFG4l1zt"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sAV2BtPY" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577888; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Xt9zZ2ej2EvKo8A2ksnwwKEosXOT196FBGDnWfw8evA=; b=fFG4l1ztdpJGFj6wUPMMpjO2Ml+fnGpN81u7AqxWNmk/xtTlqCL3cyHP5et3L6WY7fkDO9 nwuGjHhnhOINS6U5/tQJ/952dXIDBi3F1+vnx1510znYkffdQA8a5M27tyW7WXjiqPQNia WWXCnIG1tR7BL8jgxDQAjgzCOBgAI+Se3KR03wAQPr//vTTpFrMR0S75ECwqnEfvRzrfDQ VTnwTgvswD4/UUsC0NhrvWMj0v88k4dj9RfUXneRiFhQJkp6Zb5pPUKaCRdNcS3WIuetE6 wuGkRxpSLviDkQfnda+CPOHBn4sro7ccw5AY3coO4L1JD0v/2XZme8EQonSvcg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577888; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Xt9zZ2ej2EvKo8A2ksnwwKEosXOT196FBGDnWfw8evA=; b=sAV2BtPYMRe1z57EwsMK92TNGudYPfHNviuOFYSwvbLL/dP0lhNfKo4U/BGS62+vrfp4+F Qq4Fmch5FinqakDw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 13/90] x86/cpu/intel: Rescan CPUID table after leaf unlock Date: Fri, 27 Mar 2026 03:15:27 +0100 Message-ID: <20260327021645.555257-14-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel CPUs have a "limit CPUID" MSR bit to limit CPUID enumeration only up to CPUID(0x2). This can be set by old BIOSen before booting Linux. If that MSR bit was set, refresh the cached CPUID table after clearing it. Scan only the newly-found CPUID leaves, not to override any of the kernel's previously force-set or unset CPUID bits. References: 066941bd4eeb ("x86: unmask CPUID levels on Intel CPUs") References: 0c2f6d04619e ("x86/topology/intel: Unlock CPUID before evaluati= ng anything") Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 646ff33c4651..08869fecdf30 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -183,20 +183,34 @@ static void detect_tme_early(struct cpuinfo_x86 *c) keyid_bits); } =20 +/* + * Intel CPUs have an MSR bit to limit CPUID enumeration to CPUID(0x2), wh= ich + * can be set by old BIOSes before booting Linux. Clear that bit. + * + * Scan any newly-found CPUID leaves afterwards. + */ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) { + const struct leaf_0x0_0 *l0; + unsigned int rescan_from; + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) return; =20 if (c->x86_vfm < INTEL_PENTIUM_M_DOTHAN) return; =20 - /* - * The BIOS can have limited CPUID to leaf 2, which breaks feature - * enumeration. Unlock it and update the maximum leaf info. - */ - if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_= BIT) > 0) - c->cpuid_level =3D cpuid_eax(0); + if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_= BIT) <=3D 0) + return; + + cpuid_refresh_leaf(c, 0x0); + l0 =3D cpuid_leaf(c, 0x0); + if (!l0) + return; + + rescan_from =3D min_t(int, l0->max_std_leaf, c->cpuid_level) + 1; + cpuid_refresh_range(c, rescan_from, CPUID_BASE_END); + c->cpuid_level =3D l0->max_std_leaf; } =20 static void early_init_intel(struct cpuinfo_x86 *c) --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3170E33F8C5 for ; Fri, 27 Mar 2026 02:18:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577894; cv=none; b=ZWYppSCPH+6P3AkkkB3bG8ELOpBsbecFxpm8qNT76XrxnW4YoSw7Rf4Ba49lUVzfyyWqTFYcG2+I+DLOtbz+Hp4oUwyWOx1EMk0RXxJQEWDVMYoRssWL75lDR0WUgmOiyZ/DplbgpPs85KAmkME3UuZaRgTJZBdd2SrbQiN6UgM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577894; c=relaxed/simple; bh=cvI/MiB5I4vaZ7Y5jMJUfTnoFoGb0fqpJmh5SJm+dY4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CFE2JODtb8d3W2AMj1HCXFQ45Kxvz7UqMRh779uSz05+m/HhyoprbAYQvoW19iEURYXyM6UL9CpMH/vu6+e1J844avXEma/9BGjzzDELAQZnnfWpaUWOF6UyUVneWbRhcRvugvUYtU9PpeQdaok1eOjqxZvsf3V0YJt98SSDA+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Sv+bRiez; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=aoWbLnj3; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Sv+bRiez"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="aoWbLnj3" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577891; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zasYLAaFKS+By0nyxOXjlHUg5dfdQZlPvH4qmGNbh7Q=; b=Sv+bRiezArVqBDMLpYLi0nfwSvDjM146T2waK0IAFiLukgm6Pgk2DhmrSjklZxZFq5+IzL AqmhN+4QxH5d7Kmx+ubezZUh2ORJzUIla0VbCglMSRkkSPbo5GE3Ggtq4yharzkKPvtmiH ZBNqmdyMRFql4A9SpPiztwcDE3EEAg+BUK3yEKV9+5KgoclIFBCqsiLSbYSfyuHQbvmYv6 wYO42+5yML0IYvZVLz/8+08aesoC2MlugdkONKPrtq0wPKv5cLbwkQUTAtH8REvKLJFIL2 FKDyfMskbJsoLUpA/NTHj5P2K/KH4zjlCcRActnkJRFTYF06Hxn+OSFBciVLhg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577891; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zasYLAaFKS+By0nyxOXjlHUg5dfdQZlPvH4qmGNbh7Q=; b=aoWbLnj3IumoIljAUis77pBzXf8Sb4VDbnTCFGDr3qBTrG5YkoYMqq6FLg6bkz1tANOiJp bf4doaq5j5iM96Dg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 14/90] x86/cpu: Use parsed CPUID(0x0) Date: Fri, 27 Mar 2026 03:15:28 +0100 Message-ID: <20260327021645.555257-15-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x0) instead of a direct CPUID query. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8fd7d2f480bf..882754f10a4f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -940,11 +940,15 @@ void get_cpu_vendor(struct cpuinfo_x86 *c) =20 void cpu_detect(struct cpuinfo_x86 *c) { - /* Get vendor name */ - cpuid(0x00000000, (unsigned int *)&c->cpuid_level, - (unsigned int *)&c->x86_vendor_id[0], - (unsigned int *)&c->x86_vendor_id[8], - (unsigned int *)&c->x86_vendor_id[4]); + const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + + if (!l0) + return; + + c->cpuid_level =3D l0->max_std_leaf; + *(u32 *)&c->x86_vendor_id[0] =3D l0->cpu_vendorid_0; + *(u32 *)&c->x86_vendor_id[4] =3D l0->cpu_vendorid_1; + *(u32 *)&c->x86_vendor_id[8] =3D l0->cpu_vendorid_2; =20 c->x86 =3D 4; /* Intel-defined flags: level 0x00000001 */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49955342C92 for ; Fri, 27 Mar 2026 02:18:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577898; cv=none; b=hBY7Shk3V4NqcarLgm+I7C7ESMS6BbOhGffrIbuSSd4wwbnn97Jpdon1JW+1FyoWjh4jVycHWJSAqNAQ17xNnnWh4z0vnlAY13uESSz2kCJ6Z2C1ZLzRoO2K6aaOLekdk6XQWSKOevBue5I4nR5vUCP9N14SvojXSdbtPXqctwM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577898; c=relaxed/simple; bh=P9YAUtYdj5urdN9dPUySA2hAuE79JDJMW2NoYiUCg9w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MPHq31TYyjcG7OeAFJMChn5QoxAegXxDSeiGxe35rrjn3tuq7lTpW5rr1Yq5p86SOjRBPQjgFB2jqlrhQGe53muGCzUOqqy+yMjq5WLwOoZlHwu1KJV+/4WIM1WQXLQcsDI22s3OOMqeOeMLd0jES6mATGryoQ3E+Z6Q9zPCvN8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CP2XDUOg; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mti8DVLv; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CP2XDUOg"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mti8DVLv" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577895; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7roSgOj05IZXWacocQOMFvbLhRshT9TcVnmRsVuI+UY=; b=CP2XDUOg9MXmzne8JX8ORCLPUN3K651F07txE7VM3nWQizSNraO461CbBvNGDoi6WexFTQ ZZkkZgiYRA4dG+9srbbSUnrzwoYZBx+kbCuK3PZMaybNMYwEWX4WIeg0SGUPyV081/y2eV HgfEm+FS06JHg/hKBQtX4ZmyrubCK0pRvzIKLDKrnh3ulQd7b3WODvev9Dzl8/pBzfRod9 HuURtj0kzt+80ZON37t3VFrAHf496mrihCY7RClpN/mZywdodXFWe8ARD9MfIapuluw57j Bj6T3CBEsoJKRVGa1RIQPpgPAnyZpbSqiUyUX166zUVy/W+om/JBL84ReGgw0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577895; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7roSgOj05IZXWacocQOMFvbLhRshT9TcVnmRsVuI+UY=; b=mti8DVLvj6Crzl75nkJExY8qjFeBGXcWuNw5FbKmUZtYlSR1tMwQqGR1UybUpGX/HrNQJM uQ0AeVSp7drFKcBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 15/90] x86/lib: Add CPUID(0x1) family and model calculation Date: Fri, 27 Mar 2026 03:15:29 +0100 Message-ID: <20260327021645.555257-16-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The x86 library provides x86_family() and x86_model(). They take raw CPUID(0x1) register output and calculate the CPU family and model from it. In follow-up work, the x86 subsystem will use parsed CPUID APIs instead of invoking direct CPUID queries. These new APIs force using the auto generated leaf data types at . Introduce x86 family and model calculation functions that take these auto-generated data types. Refactor the original code so that no logic is duplicated. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpu.h | 6 +++++ arch/x86/lib/cpu.c | 45 ++++++++++++++++++++++++-------------- 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index ad235dda1ded..90902cd91335 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -7,7 +7,9 @@ #include #include #include + #include +#include =20 #ifndef CONFIG_SMP #define cpu_physical_id(cpu) boot_cpu_physical_apicid @@ -25,6 +27,10 @@ int mwait_usable(const struct cpuinfo_x86 *); unsigned int x86_family(unsigned int sig); unsigned int x86_model(unsigned int sig); unsigned int x86_stepping(unsigned int sig); + +unsigned int cpuid_family(const struct leaf_0x1_0 *l); +unsigned int cpuid_model(const struct leaf_0x1_0 *l); + #ifdef CONFIG_X86_BUS_LOCK_DETECT extern void __init sld_setup(struct cpuinfo_x86 *c); extern bool handle_user_split_lock(struct pt_regs *regs, long error_code); diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c index 7ad68917a51e..4d0beeeb4885 100644 --- a/arch/x86/lib/cpu.c +++ b/arch/x86/lib/cpu.c @@ -1,33 +1,36 @@ // SPDX-License-Identifier: GPL-2.0-only #include #include + #include +#include =20 -unsigned int x86_family(unsigned int sig) +static unsigned int __x86_family(unsigned int base_fam, unsigned int ext_f= am) { - unsigned int x86; + if (base_fam =3D=3D 0xf) + base_fam +=3D ext_fam; =20 - x86 =3D (sig >> 8) & 0xf; + return base_fam; +} =20 - if (x86 =3D=3D 0xf) - x86 +=3D (sig >> 20) & 0xff; +static unsigned int +__x86_model(unsigned int family, unsigned int base_model, unsigned int ext= _model) +{ + if (family >=3D 0x6) + base_model |=3D ext_model << 4; =20 - return x86; + return base_model; +} + +unsigned int x86_family(unsigned int sig) +{ + return __x86_family((sig >> 8) & 0xf, (sig >> 20) & 0xff); } EXPORT_SYMBOL_GPL(x86_family); =20 unsigned int x86_model(unsigned int sig) { - unsigned int fam, model; - - fam =3D x86_family(sig); - - model =3D (sig >> 4) & 0xf; - - if (fam >=3D 0x6) - model +=3D ((sig >> 16) & 0xf) << 4; - - return model; + return __x86_model(x86_family(sig), (sig >> 4) & 0xf, (sig >> 16) & 0xf); } EXPORT_SYMBOL_GPL(x86_model); =20 @@ -36,3 +39,13 @@ unsigned int x86_stepping(unsigned int sig) return sig & 0xf; } EXPORT_SYMBOL_GPL(x86_stepping); + +unsigned int cpuid_family(const struct leaf_0x1_0 *l) +{ + return __x86_family(l->base_family_id, l->ext_family); +} + +unsigned int cpuid_model(const struct leaf_0x1_0 *l) +{ + return __x86_model(cpuid_family(l), l->base_model, l->ext_model); +} --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDE4733688C for ; Fri, 27 Mar 2026 02:18:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577902; cv=none; b=pLFdgZ5q7RtI6NrkSK1539qz++Gq+bZAhRQvq87hazIz7MnomZSnKm6HCmsz6mQDftN94Q/kQImLcWUCmjP2Fr48HhjxcOLDhug5jIJpd3/YzNicprF7Y8ltYYZZut7PunjAv/arFOBj5vKi7YJ0zla8tHtaXmYzsBjO0ranqNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577902; c=relaxed/simple; bh=yZO3oyNgwkBjST8DL5nHJzVtgcaS/J5bZ4XGO4xatOg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dQuhzztWVs/EfVHCWwZKnJFCc1QrtfM/NEuOJVjfjwfqitM0R5iKKhAXjemCStKqvf0XV4xmSk/AUULgc6it/W/cE3L8rR3lNYZWPtWnJSJ75kHfzsWXMFOqIMqt756lzbGSN3wW/bVuwWU/Fg2CVyFPQPeYVpO5RNdU3bacfms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=d67wuFpk; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oXOjZiRp; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="d67wuFpk"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oXOjZiRp" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577898; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ooFMpDZikzJTmqCKLxnHYNVV/Cyv2iG4aFci2pBjaQw=; b=d67wuFpk7rKNa+dlvkILauEcsc5nIUcqheqe/0TILFUy5FRji3+w8w8Urhv6FGSOEE7kw/ V1QQkNSzQ0zdiG4RNEWdcWqwcuvaO7uZIFp113INDtGncvKLMca16i7RuChoM2E7ZIWnm4 livzXpULmyxurFIYgBZRX6f4BnbCcOIvEXDXZz6cuwMqXvbxNcM12/OAMG/XycC0AaO1eW j/3A0B7xrjw/mFZz/fu3tQ69ePHH1LVUlZhpBy7MMdF9yRg0qTWOoNn6WBEnkJPkWc1D0G 2YrXejVFtbOCooOC+ED2ejoBAF7hkG+60xXmHcBWnfLVXxxz1yWNDa2TCI9cjw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577898; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ooFMpDZikzJTmqCKLxnHYNVV/Cyv2iG4aFci2pBjaQw=; b=oXOjZiRpK+hxE/hmGgcy5O+LincDm1wmpauY9ZxGa86zWBbe+c0QGohCpv5EihnJRdTIZV 6Q/bki5NlE+aqiAw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 16/90] x86/cpu: Use parsed CPUID(0x1) Date: Fri, 27 Mar 2026 03:15:30 +0100 Message-ID: <20260327021645.555257-17-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On early boot CPU detection, use parsed CPUID(0x1) instead of a direct CPUID query. Beside the parser's centralization benefits, this allows using the auto generated CPUID data types, and their C99 bitfields, instead of doing ugly bitwise operations. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 882754f10a4f..f31746c216c9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -941,6 +941,7 @@ void get_cpu_vendor(struct cpuinfo_x86 *c) void cpu_detect(struct cpuinfo_x86 *c) { const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + const struct leaf_0x1_0 *l1 =3D cpuid_leaf(c, 0x1); =20 if (!l0) return; @@ -951,17 +952,13 @@ void cpu_detect(struct cpuinfo_x86 *c) *(u32 *)&c->x86_vendor_id[8] =3D l0->cpu_vendorid_2; =20 c->x86 =3D 4; - /* Intel-defined flags: level 0x00000001 */ - if (c->cpuid_level >=3D 0x00000001) { - u32 junk, tfms, cap0, misc; - - cpuid(0x00000001, &tfms, &misc, &junk, &cap0); - c->x86 =3D x86_family(tfms); - c->x86_model =3D x86_model(tfms); - c->x86_stepping =3D x86_stepping(tfms); + if (l1) { + c->x86 =3D cpuid_family(l1); + c->x86_model =3D cpuid_model(l1); + c->x86_stepping =3D l1->stepping; =20 - if (cap0 & (1<<19)) { - c->x86_clflush_size =3D ((misc >> 8) & 0xff) * 8; + if (l1->clflush) { + c->x86_clflush_size =3D l1->clflush_size * 8; c->x86_cache_alignment =3D c->x86_clflush_size; } } --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4AD3446C6 for ; Fri, 27 Mar 2026 02:18:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577904; cv=none; b=dvCMmtWTnHzHBwxHeH98yNRIhBUypNXnlZPw3Gc75pKTC0+dA/uTBChl3rCbfAVRRoioe7DiKhcncI+phTxnIJ+MKuAknwlFwjC4ctw9NQbYpYxI7kGIaCvN/rx0ijX9d54hrwbaAMYiBp1LJKdp6+xkBmkRMcZHv97o+Wj2320= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577904; c=relaxed/simple; bh=hs6DWzYq0vuxf/OJMOzgS7IHasakP2q7EwK1oSbwNPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FZhTM2HDrA/4cTB0rroF05Zv1lQ5ed8BAKTWpmPKSzjZoQkehQaW0W6/P4sOP+Skzdi7cxfBMQXU9FLpZOJmkShVl2lQjEMuRwPB5Cglv1vZH8gYXssu4i2MVnPB4201dysTDgKjdE0W65nosaCbV1D8xB6S/7PgTycvTh6Zj+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=N1I99Iov; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PTvOjC8C; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="N1I99Iov"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PTvOjC8C" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577901; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9W6CxfYeWEq7i0brXuF1X4uav/K4JgSIoykZ/Zj/DHQ=; b=N1I99Iov9cydsOrujFSgf1h4RysmaVtK8nDgc6y9Dq14A7tLpqZpIwp6B3UShtsMu5QM9Q 2WO0GBjnkTrqtUzPaJD/iqyXxfzoaHLK+W9X33mDEVxgoyjudMvtOpsE5rt2DIM63L77uZ /s60wUjcU59r1XYP7sSjWwzXhF0Nr2YkOMTQpUUr0pW2+aYxLGAys/JdaeMUNbubZVh9dc 1GGRwxefUn+6U5Oua/kZ7kLWtA6OPGV3U9kzttChlbg38m6Sn8rdf4VMWKlcJ7JH4YDXg6 kZQSEFo+8NDcRhQdHQcb1leleP44ba286nUT+Psb5LhpzIsIfo6Q4/lhnB9yiw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577901; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9W6CxfYeWEq7i0brXuF1X4uav/K4JgSIoykZ/Zj/DHQ=; b=PTvOjC8C+v6uH2AVJhpoyWMIc0Z1Q090lVdGmXLLhl3JqOG5wK4Vbqid+iYmCZH7hAkIaD Tx3M63TMaJ0QwVDA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 17/90] x86/cpuid: Parse CPUID(0x80000000) Date: Fri, 27 Mar 2026 03:15:31 +0100 Message-ID: <20260327021645.555257-18-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID parser logic for CPUID(0x80000000). Verify the CPUID output since legacy Intel machines without an extended range will repeat the highest standard CPUID leaf output instead. This verification is similar to what is done at arch/x86/kernel/head_32.S and arch/x86/kernel/cpu/common.c. References: 8a50e5135af0 ("x86-32: Use symbolic constants, safer CPUID when= enabling EFER.NX") References: 67ad24e6d39c ("- pre5: - Rasmus Andersen: add proper...") #= Historical git Signed-off-by: Ahmed S. Darwish Cc: "H. Peter Anvin" Link: https://lore.kernel.org/r/d4fcfd91-cc92-4b3c-9dd2-56ecd754cecc@citrix= .com --- arch/x86/include/asm/cpuid/types.h | 4 ++++ arch/x86/kernel/cpu/cpuid_parser.c | 21 +++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 1 + 3 files changed, 26 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 3d0e611c97ba..c020fb8fed59 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -36,7 +36,10 @@ enum cpuid_regs_idx { #define CPUID_RANGE_MAX(idx) (CPUID_RANGE(idx) + 0xffff) =20 #define CPUID_BASE_START 0x00000000 +#define CPUID_EXT_START 0x80000000 + #define CPUID_BASE_END CPUID_RANGE_MAX(CPUID_BASE_START) +#define CPUID_EXT_END CPUID_RANGE_MAX(CPUID_EXT_START) =20 /* * Types for CPUID(0x2) parsing: @@ -203,6 +206,7 @@ struct cpuid_leaves { /* Leaf Subleaf number (or max number of subleaves) */ CPUID_LEAF ( 0x0, 0 ); CPUID_LEAF ( 0x1, 0 ); + CPUID_LEAF ( 0x80000000, 0 ); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 898b0c441431..2cebe15f75d4 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -38,6 +38,24 @@ cpuid_read_generic(const struct cpuid_parse_entry *e, co= nst struct cpuid_read_ou cpuid_read_subleaf(e->leaf, e->subleaf + i, regs); } =20 +static void +cpuid_read_0x80000000(const struct cpuid_parse_entry *e, const struct cpui= d_read_output *output) +{ + struct leaf_0x80000000_0 *el0 =3D (struct leaf_0x80000000_0 *)output->reg= s; + + cpuid_read_subleaf(e->leaf, e->subleaf, el0); + + /* + * Protect against Intel 32-bit CPUs lacking an extended CPUID range. A + * CPUID(0x80000000) query on such machines will repeat the output of the + * highest standard CPUID leaf instead. + */ + if (CPUID_RANGE(el0->max_ext_leaf) !=3D CPUID_EXT_START) + return; + + output->info->nr_entries =3D 1; +} + /* * CPUID parser table: */ @@ -53,9 +71,11 @@ static const struct cpuid_parse_entry cpuid_parse_entrie= s[] =3D { static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsi= gned int range) { const struct leaf_0x0_0 *l0 =3D __cpuid_table_subleaf(t, 0x0, 0); + const struct leaf_0x80000000_0 *el0 =3D __cpuid_table_subleaf(t, 0x800000= 00, 0); =20 switch (range) { case CPUID_BASE_START: return l0 ? l0->max_std_leaf : 0; + case CPUID_EXT_START: return el0 ? el0->max_ext_leaf : 0; default: return 0; } } @@ -113,6 +133,7 @@ cpuid_fill_table(struct cpuid_table *t, const struct cp= uid_parse_entry entries[] unsigned int end; } ranges[] =3D { { CPUID_BASE_START, CPUID_BASE_END }, + { CPUID_EXT_START, CPUID_EXT_END }, }; =20 for (unsigned int i =3D 0; i < ARRAY_SIZE(ranges); i++) diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index df627306cc8c..7d41bde0c0ec 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -116,5 +116,6 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY ( 0x0, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x1, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27CBC346A02 for ; Fri, 27 Mar 2026 02:18:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577908; cv=none; b=jnXhbgaxva27yxPfKBrlfI8qNo7aRECa7X3InY+9Ta1izC8E/SvEtmE/UmB+Q/Zlbi7hCfc51QR64KuBcHC/8mx5qK8hg8mfYgd47owxpS4JANHZMyvZrftIEsly7919ztD5WrE7jIhBCoTnYwBjz7eaGWvbSzfvKbVz5RrbvLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577908; c=relaxed/simple; bh=2M0077shx+cp5E/0UitoS25jemq15VlJuQh2C/Iu43A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T2l7KQgaLIGYqtNOu65N15+AZT/pqzP+WFelXPy5d2AJgA/ae8GgfeAhTS3gCe8L+/ORy5YwEztMAOGiH3fE8tsziRKbHgQmQ95OnNfJU1t+5b46/of/TSuFV5rAzQoE/4U75F+DzFDto/yvYzzCo0s/D/X4rzyuWND35p+pfLs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=F4uQx+XK; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ATFG84Jf; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="F4uQx+XK"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ATFG84Jf" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577904; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ySK0vbw5fQQ1k3iTzALbXciUAXQFVLXE+FR8sQuweNg=; b=F4uQx+XKLCCY7oRL3+Zn7m7BNw6lpIo2cmYfhnUWqjfWIizsy5ILbsrwHKgIfjavd3WoMd VI/8HcybDifI6bfSFzthj5CPOLnI6DJB+aCDKIIHG4RD/F8YM2PjYJvwXRNFGXLKrBM1bk hgYo8uuIdiWrI8p6nYO10STGRvupd8B5czwbr3jR13LLa+2x1N07U50m1YWULXlsSb2NAf nk9aLSnApt1mkfDly3fzInaMemOwCenoLf/nPLwZP9uvtdeh8sUlXcE3+mvgpETQ9Eh+pG XVMpQigj2IfB3I5lMLqYeNddGzUQbn/Yw5bwV33Fh9ZHmPEy4KkC+pK9nm2X0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577904; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ySK0vbw5fQQ1k3iTzALbXciUAXQFVLXE+FR8sQuweNg=; b=ATFG84Jf4/5hYS1q/bjLm2kqTx20p15lQxDC5sc2tASPccXO48qLXTN1EPBiJ//LrnU5/I S+3Ot5v9AccmAsCQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 18/90] x86/cpu: Use parsed CPUID(0x80000000) Date: Fri, 27 Mar 2026 03:15:32 +0100 Message-ID: <20260327021645.555257-19-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At early boot code, use parsed CPUID(0x80000000) instead of invoking a direct CPUID query. The original code has the check: extended_cpuid_level =3D ((eax & 0xffff0000) =3D=3D 0x80000000) ? eax := 0; to protect against Intel 32-bit machines without an extended range, where a CPUID(0x80000000) query will repeat the output of the max-valid standard CPUID leaf output. A similar check is already done at the CPUID parser's own CPUID(0x80000000) read function: if (CPUID_RANGE(el0->max_ext_leaf) !=3D CPUID_EXT_START) { // Handle error } Thus, for the call-site, the parsed CPUID NULL check below: el0 =3D cpuid_leaf(c, 0x80000000); extended_cpuid_level =3D el0 ? el0->max_ext_leaf : 0; is sufficient. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f31746c216c9..204c1f65f265 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1017,6 +1017,7 @@ static void init_speculation_control(struct cpuinfo_x= 86 *c) =20 void get_cpu_cap(struct cpuinfo_x86 *c) { + const struct leaf_0x80000000_0 *el0 =3D cpuid_leaf(c, 0x80000000); u32 eax, ebx, ecx, edx; =20 /* Intel-defined flags: level 0x00000001 */ @@ -1052,12 +1053,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_capability[CPUID_D_1_EAX] =3D eax; } =20 - /* - * Check if extended CPUID leaves are implemented: Max extended - * CPUID leaf must be in the 0x80000001-0x8000ffff range. - */ - eax =3D cpuid_eax(0x80000000); - c->extended_cpuid_level =3D ((eax & 0xffff0000) =3D=3D 0x80000000) ? eax = : 0; + c->extended_cpuid_level =3D el0 ? el0->max_ext_leaf : 0; =20 if (c->extended_cpuid_level >=3D 0x80000001) { cpuid(0x80000001, &eax, &ebx, &ecx, &edx); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04CF9346FC4 for ; Fri, 27 Mar 2026 02:18:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577910; cv=none; b=aWCeeYkuEjPJyFruBxJU+yhLfukypgVmzg7oCROkxRkWttP/2UXtovcHgn2MvJfOsC5M2qMajN4LcNFjLxCnVqCg7A+i3Jc7ANNr4BPpLxQ+OWqkYDWsEEn0TAk+o2+3hSTMoEFjvgi8yguTBVyXpIMd/0n1sRzFAyEBXJXanoE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577910; c=relaxed/simple; bh=ID92Knkf/wN2SnLzgspp/Cdht8W8Llqc2r1TF1tHcDc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CTT+r+tHa457vO6VZzRo3yqXHgpW60ZTkP0NpKVCvyC3SKhzHi/eY03VjITNCJ9tTVDSwYYp8mq7QPCThzT6+gJJFho2hc1zxBDXH/1F6lC92rH5+EvQ3OGN+4WCz3Vz79ziqVq30N0+NT0yfpVk+GKYrUQp2Zx4Zdl6CZCf59Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=LR28O06L; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=8GCcw8D8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="LR28O06L"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="8GCcw8D8" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=esKyGB1szws7rUQF8I59OLe+1fzvbCvnBNUO1TVbrzo=; b=LR28O06LdeQaGwr2AIZF0sT+hUjWEAPv/QTiewXz4z32Huxhr7NocEGCSbwaCS3kLGXtHZ v0dGCyuWaN6cYJTBqVO1Qu80Q9+K5M1JDcJ1PkHq4y/Zqf758i+RIlUOR8bTY89Jd6/eUm FLDD0qr2GZ8wKZ8xPmSEnNeRoxYm6VpDrAhqhTk+B3TkbXJNP/9FgEur/hjecyZUICwReZ rKuAjje5Jcp7i4aNsY+E8EgWk4SUI17VUS6b9ZFIDPnl3KJXQqybhIZe6iPplfd9Dxnr54 OaAoe5c5dL/cGGI80kEc7gVLuoYcTu54uburiv/IK4Vn5LWl8DEN2ubhlBwjkA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577907; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=esKyGB1szws7rUQF8I59OLe+1fzvbCvnBNUO1TVbrzo=; b=8GCcw8D8AFP5XvfIs3opYx0q9GGCuY+EnSH1KaZDXdzh0euT/mmMFReFy3cViMQbzRED9u tEEP+V0MpXuZt2Aw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 19/90] x86/cpuid: Parse CPUID(0x80000002) to CPUID(0x80000004) Date: Fri, 27 Mar 2026 03:15:33 +0100 Message-ID: <20260327021645.555257-20-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID(0x80000002) =3D> CPUID(0x80000004) support to the CPUID parser. This allows converting their call sites to the CPUID API next. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 3 +++ arch/x86/kernel/cpu/cpuid_parser.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index c020fb8fed59..8be2c2ba874a 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -207,6 +207,9 @@ struct cpuid_leaves { CPUID_LEAF ( 0x0, 0 ); CPUID_LEAF ( 0x1, 0 ); CPUID_LEAF ( 0x80000000, 0 ); + CPUID_LEAF ( 0x80000002, 0 ); + CPUID_LEAF ( 0x80000003, 0 ); + CPUID_LEAF ( 0x80000004, 0 ); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 7d41bde0c0ec..3e11e13fa76c 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -117,5 +117,8 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x0, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x1, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ + CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FBB834A3C9 for ; Fri, 27 Mar 2026 02:18:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577913; cv=none; b=LahqPdFSb8VqZf5s7P4nCNO8n6F/o/2kxNk73xmdNtPUVWfh90ocGnXr4I1YIz/C70eaJzOqfv1vIha2Ylpt/hn7hHqZL0n37aHcSpByeh9W1oyWBfFLMqv3ydHc8kldjzzBPKnyzJ0mgmRBRzVYVAKcJClXBH9LirAY+mDw1N4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577913; c=relaxed/simple; bh=OV4pfzqO9+fpQt7J+eXW03IAfiZ39Un3jA1qCHSPi+0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GjJNOuGvxBOSM02RDfM2+gaNSc+4iu8JCe5j0a7FV6X7sOw5NIPn5U3/6yTB1vYUemBQugRYtEDv5Dm+ACorC7dL1mZVL+GoHWq9X0ZZvJRIfF9osk0+gIUuq1s0QZj8brC0fIEdgyNgWRWpEKyl6f9WPi9hBlj6A2waq5U3LNk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BonxuzFP; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Xvo2vK2j; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BonxuzFP"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Xvo2vK2j" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577910; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GLLP2mpYmnTic7kZE+aFg8O9kaD4OqkN1SAEQ6Iq528=; b=BonxuzFP4vOgI7GUZuaucPPYpa9aKA/fqdA92CXZLPgoy7olLNGAbvnGbv07pQ6wucUbYH YrTsmdSYpGeukG3UDKA/9b2RdWrTd20P0NPliMkE1zwStqf6ir0IZJ3Sz/pvTJjPwsgAw6 x9Y5q3//d4517BCxynyK0lv7VWcOszlgikMlLkeDwnhBDtHD4DSP3vYxkg0pwQwKC6y5a/ g0iRnTsqTiKahVCV/J0psi6P+AS7DwfLg8HeLbGB+fFgp1Gd7kKZpHJ9vElXVrFifbkYCx HQl6SVYEzSZr2oA70XMkCjq5A/cbe2Y+OWEOoMQ0mjc6PdB9cC3fWK0MyHElLQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577910; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GLLP2mpYmnTic7kZE+aFg8O9kaD4OqkN1SAEQ6Iq528=; b=Xvo2vK2jyUroFovXm4S0kwUuOFi+AzfTN/gZlSeobl3JwDTcNfSabr0cHe8ZElTJvLsZPH nCjgyr8ddTJC1CAw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 20/90] x86/cpu: Use parsed CPUID(0x80000002) to CPUID(0x80000004) Date: Fri, 27 Mar 2026 03:15:34 +0100 Message-ID: <20260327021645.555257-21-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For CPU brand string enumeration, use parsed CPUID(0x80000002) to CPUID(0x80000004) instead of invoking direct CPUID queries. This centralizes CPUID invocation to the system's CPUID parser. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 204c1f65f265..060f69ab3739 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -824,16 +824,18 @@ static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM]= =3D {}; =20 static void get_model_name(struct cpuinfo_x86 *c) { - unsigned int *v; + const struct leaf_0x80000002_0 *l2 =3D cpuid_leaf(c, 0x80000002); + const struct leaf_0x80000003_0 *l3 =3D cpuid_leaf(c, 0x80000003); + const struct leaf_0x80000004_0 *l4 =3D cpuid_leaf(c, 0x80000004); char *p, *q, *s; =20 - if (c->extended_cpuid_level < 0x80000004) + if (!l2 || !l3 || !l4) return; =20 - v =3D (unsigned int *)c->x86_model_id; - cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); - cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); - cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); + *(struct leaf_0x80000002_0 *)&c->x86_model_id[0] =3D *l2; + *(struct leaf_0x80000003_0 *)&c->x86_model_id[16] =3D *l3; + *(struct leaf_0x80000004_0 *)&c->x86_model_id[32] =3D *l4; + c->x86_model_id[48] =3D 0; =20 /* Trim whitespace */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43BE534A79A for ; Fri, 27 Mar 2026 02:18:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577917; cv=none; b=G/617NjvqVIi5m/AuhB88Y59pEGUeYTrXb4awcK4mBBGLO3ZKSpbjaklpfi3Pwk6tJ3+OYH/PZXr1DreAVZS1d1/ZMvU2x4kBpdOGosKKcxEKZcpgSwUAGfVtNTYWVTACW6GceWDzwAZoSwwfs/rikKltNPpkKardR9iJlBNOho= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577917; c=relaxed/simple; bh=qdI/2fsEm+5+Qjwu/BRetMrox5XiBtoFOVEFvGvEG44=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bLQLrDAZIduPamVLbbMlbINsQIgSuSewXD1CqKIkNDJMDzYoKyyzwOCe/xie5iolzZ3cGwsihZeCCwGtGvehOI2owuN+jOwINLgW/Gc+KEA13o/izj+Mbb6ulqj9F+1qb1tdBpMxAJAcE6R57cqO2sYJ+8XEAujdfJ6aA98m8XA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=RltFqby1; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=d/Lc4KNP; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="RltFqby1"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="d/Lc4KNP" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577914; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DpJMNQoVd5GAesFaI0X69w3FDmB4uuSq3MGQ20oJHwM=; b=RltFqby1Mk1aldlYXNfEhnzEj8qO/FPZZQTkUkX10sGWnl+j1exh/GVukB1VATRSEU8G0e neHJ+20nMLYsxuN2Dh/Xm1yyX1Vumsfc/bYqJwZQeybvwQfYu9wRoFgNIIblrc9U9mr5aj 88cthm2KPxJQH51QfUNDByD/A15LQUZEbMR/Yhr6SmxNWX+2AM9M02Qzgw1lLp9zOJh0jU W4VTZAPZbW/YKwzcTc/7z10KE487KVCpoDMLW59iiKBsmkJGBEUsBBYaYBE+GyDZiBIMw1 adZYTTUovmdXWhm4cxeC7aTbxdRseZo4uTIu53iq3kNu551/zXxfhpCBCoNh9A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577914; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DpJMNQoVd5GAesFaI0X69w3FDmB4uuSq3MGQ20oJHwM=; b=d/Lc4KNPUST0TiMTb45sl1zmmPU8ul8Umx0kVTbldaAxqyIohZY5/PXtCCPe9POIENvhX2 1Cix0m9ZTCOcc+Cw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 21/90] x86/cpuid: Split parser tables and add vendor-qualified parsing Date: Fri, 27 Mar 2026 03:15:35 +0100 Message-ID: <20260327021645.555257-22-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the CPUID parser, introduce a table listing vendor-specific CPUID leaves. Not all CPUID leaves should be queried on all x86 vendors, so the parser will enumerate such leaves only if the boot machine's x86 vendor is listed as supported. This provides the following benefits: (a) Even when a CPUID leaf falls within the CPU's standard or extended maximum leaf range, querying architecturally unsupported and reserved CPUID leaves may trigger new kernel boot behaviors or subtle bugs; especially on legacy machines. (b) Associating x86 vendor information with CPUID leaves will enable the CPUID parser to emit (lightweight) error messages when malformed CPUID leaf output is detected. This is due to the parser now being more certain that the queried leaf is valid on the machine. (c) Attaching x86 vendor information to CPUID leaves will relieve call sites, especially drivers, from ugly x86 vendor checks before querying a CPUID leaf. Just checking if the CPUID APIs did not return NULL will be sufficient. Split the CPUID parsing table into an "early boot" table and a standard one. The early boot phase parses only CPUID(0x0) and CPUID(0x1) since they are needed to identify the CPU's x86 vendor. Once the x86 vendor info is saved to the CPU's capability structure, invoke the CPUID parser again to parse the rest of the CPUID table. In that second phase, the parser assumes that "boot_cpu_data.x86_vendor" is valid and uses it for the CPUID leaves x86 vendor validity checks. For each vendor-specific CPUID leaf, build its list of matching x86 vendors using CPP varargs. Encoding this as bitflags was not doable, since the x86 vendor IDs are just raw monotonic numbers from 0 (Intel) to 11 (Vortex). Keep the CPUID parser's leaf vendors table empty for now. Leaves like CPUID(0x2), CPUID(0x4), CPUID(0x16), and CPUID(0x8000001d) will be added to the parser vendor table once their support is actually implemented. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 1 + arch/x86/kernel/cpu/common.c | 9 ++- arch/x86/kernel/cpu/cpuid_parser.c | 100 +++++++++++++++++++++++++---- arch/x86/kernel/cpu/cpuid_parser.h | 52 ++++++++++++++- arch/x86/xen/enlighten.c | 2 +- 5 files changed, 146 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 82eddfa2347b..3d5a0d4918cc 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -532,6 +532,7 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) * CPUID parser exported APIs: */ =20 +void cpuid_scan_cpu_early(struct cpuinfo_x86 *c); void cpuid_scan_cpu(struct cpuinfo_x86 *c); void cpuid_refresh_leaf(struct cpuinfo_x86 *c, u32 leaf); void cpuid_refresh_range(struct cpuinfo_x86 *c, u32 start, u32 end); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 060f69ab3739..f7372833dd50 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1019,9 +1019,11 @@ static void init_speculation_control(struct cpuinfo_= x86 *c) =20 void get_cpu_cap(struct cpuinfo_x86 *c) { - const struct leaf_0x80000000_0 *el0 =3D cpuid_leaf(c, 0x80000000); + const struct leaf_0x80000000_0 *el0; u32 eax, ebx, ecx, edx; =20 + cpuid_scan_cpu(c); + /* Intel-defined flags: level 0x00000001 */ if (c->cpuid_level >=3D 0x00000001) { cpuid(0x00000001, &eax, &ebx, &ecx, &edx); @@ -1055,6 +1057,7 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_capability[CPUID_D_1_EAX] =3D eax; } =20 + el0 =3D cpuid_leaf(c, 0x80000000); c->extended_cpuid_level =3D el0 ? el0->max_ext_leaf : 0; =20 if (c->extended_cpuid_level >=3D 0x80000001) { @@ -1796,7 +1799,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) =20 /* cyrix could have cpuid enabled via c_identify()*/ if (cpuid_feature()) { - cpuid_scan_cpu(c); + cpuid_scan_cpu_early(c); cpu_detect(c); get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); @@ -1969,7 +1972,7 @@ static void generic_identify(struct cpuinfo_x86 *c) if (!cpuid_feature()) return; =20 - cpuid_scan_cpu(c); + cpuid_scan_cpu_early(c); cpu_detect(c); get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 2cebe15f75d4..97b7f296df03 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -21,6 +21,10 @@ static void cpuid_clear(const struct cpuid_parse_entry *= e, const struct cpuid_re memset(output->info, 0, sizeof(*output->info)); } =20 +static const struct cpuid_vendor_entry cpuid_vendor_entries[] =3D { + CPUID_VENDOR_ENTRIES +}; + /* * Leaf read functions: */ @@ -57,17 +61,57 @@ cpuid_read_0x80000000(const struct cpuid_parse_entry *e= , const struct cpuid_read } =20 /* - * CPUID parser table: + * CPUID parser tables: + * + * At early boot, only leaves at cpuid_early_entries[] should be parsed. */ =20 -static const struct cpuid_parse_entry cpuid_parse_entries[] =3D { - CPUID_PARSE_ENTRIES +static const struct cpuid_parse_entry cpuid_early_entries[] =3D { + CPUID_EARLY_ENTRIES +}; + +static const struct cpuid_parse_entry cpuid_common_entries[] =3D { + CPUID_COMMON_ENTRIES +}; + +static const struct { + const struct cpuid_parse_entry *table; + int nr_entries; +} cpuid_phases[] =3D { + { cpuid_early_entries, ARRAY_SIZE(cpuid_early_entries) }, + { cpuid_common_entries, ARRAY_SIZE(cpuid_common_entries) }, }; =20 /* * Leaf-independent parser code: */ =20 +static bool cpuid_leaf_matches_vendor(unsigned int leaf, u8 cpu_vendor) +{ + const struct cpuid_parse_entry *p =3D cpuid_early_entries; + const struct cpuid_vendor_entry *v =3D cpuid_vendor_entries; + + /* Leaves in the early boot parser table are vendor agnostic */ + for (int i =3D 0; i < ARRAY_SIZE(cpuid_early_entries); i++, p++) + if (p->leaf =3D=3D leaf) + return true; + + /* Leaves in the vendor table must pass a CPU vendor check */ + for (int i =3D 0; i < ARRAY_SIZE(cpuid_vendor_entries); i++, v++) { + if (v->leaf !=3D leaf) + continue; + + for (unsigned int j =3D 0; j < v->nvendors; j++) + if (cpu_vendor =3D=3D v->vendors[j]) + return true; + + return false; + } + + /* Remaining leaves are vendor agnostic */ + return true; +} + static unsigned int cpuid_range_max_leaf(const struct cpuid_table *t, unsi= gned int range) { const struct leaf_0x0_0 *l0 =3D __cpuid_table_subleaf(t, 0x0, 0); @@ -96,6 +140,9 @@ __cpuid_reset_table(struct cpuid_table *t, const struct = cpuid_parse_entry entrie if (entry->leaf < start || entry->leaf > end) continue; =20 + if (!cpuid_leaf_matches_vendor(entry->leaf, boot_cpu_data.x86_vendor)) + continue; + cpuid_clear(entry, &output); =20 /* @@ -140,28 +187,51 @@ cpuid_fill_table(struct cpuid_table *t, const struct = cpuid_parse_entry entries[] __cpuid_fill_table(t, entries, nr_entries, ranges[i].start, ranges[i].en= d); } =20 -static void __cpuid_scan_cpu_full(struct cpuinfo_x86 *c) +static void __cpuid_scan_cpu_full(struct cpuinfo_x86 *c, bool early_boot) { - unsigned int nr_entries =3D ARRAY_SIZE(cpuid_parse_entries); + int nphases =3D early_boot ? 1 : ARRAY_SIZE(cpuid_phases); struct cpuid_table *table =3D &c->cpuid; =20 - cpuid_fill_table(table, cpuid_parse_entries, nr_entries); + for (int i =3D 0; i < nphases; i++) + cpuid_fill_table(table, cpuid_phases[i].table, cpuid_phases[i].nr_entrie= s); } =20 static void -__cpuid_scan_cpu_partial(struct cpuinfo_x86 *c, unsigned int start_leaf, u= nsigned int end_leaf) +__cpuid_scan_cpu_partial(struct cpuinfo_x86 *c, bool early_boot, unsigned = int start_leaf, unsigned int end_leaf) { - unsigned int nr_entries =3D ARRAY_SIZE(cpuid_parse_entries); + int nphases =3D early_boot ? 1 : ARRAY_SIZE(cpuid_phases); struct cpuid_table *table =3D &c->cpuid; =20 - __cpuid_zero_table(table, cpuid_parse_entries, nr_entries, start_leaf, en= d_leaf); - __cpuid_fill_table(table, cpuid_parse_entries, nr_entries, start_leaf, en= d_leaf); + for (int i =3D 0; i < nphases; i++) { + const struct cpuid_parse_entry *entries =3D cpuid_phases[i].table; + unsigned int nr_entries =3D cpuid_phases[i].nr_entries; + + __cpuid_zero_table(table, entries, nr_entries, start_leaf, end_leaf); + __cpuid_fill_table(table, entries, nr_entries, start_leaf, end_leaf); + } } =20 /* * Call-site APIs: */ =20 +/** + * cpuid_scan_cpu_early() - Populate CPUID table on early boot + * @c: CPU capability structure associated with the current CPU + * + * Populate the CPUID table embedded within @c with parsed CPUID data. + * + * This must be called at early boot, so that early boot code can identify= the + * CPU's x86 vendor. Only CPUID(0x0) and CPUID(0x1) are parsed. + * + * cpuid_scan_cpu() must be called later to complete the CPUID table. Tha= t is, + * after saving the x86 vendor info to the CPU capability structure @c. + */ +void cpuid_scan_cpu_early(struct cpuinfo_x86 *c) +{ + __cpuid_scan_cpu_full(c, true); +} + /** * cpuid_scan_cpu() - Populate current CPU's CPUID table * @c: CPU capability structure associated with the current CPU @@ -169,10 +239,12 @@ __cpuid_scan_cpu_partial(struct cpuinfo_x86 *c, unsig= ned int start_leaf, unsigne * Populate the CPUID table embedded within @c with parsed CPUID data. Al= l CPUID * instructions are invoked locally, so this must be called on the CPU ass= ociated * with @c. + * + * cpuid_scan_cpu_early() must have been called earlier on @c. */ void cpuid_scan_cpu(struct cpuinfo_x86 *c) { - __cpuid_scan_cpu_full(c); + __cpuid_scan_cpu_full(c, false); } =20 /** @@ -180,6 +252,8 @@ void cpuid_scan_cpu(struct cpuinfo_x86 *c) * @c: CPU capability structure associated with the current CPU * @start: Start of leaf range to be re-scanned * @end: End of leaf range + * + * cpuid_scan_cpu_early() must have been called earlier on @c. */ void cpuid_refresh_range(struct cpuinfo_x86 *c, u32 start, u32 end) { @@ -189,13 +263,15 @@ void cpuid_refresh_range(struct cpuinfo_x86 *c, u32 s= tart, u32 end) if (WARN_ON_ONCE(CPUID_RANGE(start) !=3D CPUID_RANGE(end))) return; =20 - __cpuid_scan_cpu_partial(c, start, end); + __cpuid_scan_cpu_partial(c, false, start, end); } =20 /** * cpuid_refresh_leaf() - Rescan a CPUID table's leaf * @c: CPU capability structure associated with the current CPU * @leaf: Leaf to be re-scanned + * + * cpuid_scan_cpu_early() must have been called earlier on @c. */ void cpuid_refresh_leaf(struct cpuinfo_x86 *c, u32 leaf) { diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 3e11e13fa76c..a3f7dcc6c03f 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -2,6 +2,7 @@ #ifndef _ARCH_X86_CPUID_PARSER_H #define _ARCH_X86_CPUID_PARSER_H =20 +#include #include =20 /* @@ -109,16 +110,63 @@ struct cpuid_parse_entry { __CPUID_PARSE_ENTRY(_leaf, __cpuid_leaf_first_subleaf(_leaf), n, _reader_= fn) =20 /* - * CPUID parser table: + * CPUID parser tables: */ =20 -#define CPUID_PARSE_ENTRIES \ +/* + * Early-boot CPUID leaves (to be parsed before x86 vendor detection) + * + * These leaves must be parsed at early boot to identify the x86 vendor. T= he + * parser treats them as universally valid across all vendors. + * + * At early boot, only leaves in this table must be parsed. For all other + * leaves, the CPUID parser will assume that "boot_cpu_data.x86_vendor" is + * properly set beforehand. + * + * Note: If these entries are to be modified, please adapt the kernel-doc = of + * cpuid_scan_cpu_early() accordingly. + */ +#define CPUID_EARLY_ENTRIES \ /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY ( 0x0, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x1, 0, generic ), \ + +/* + * Common CPUID leaves + * + * These leaves can be parsed once basic x86 vendor detection is in place. + * Further vendor-agnostic leaves, which are not needed at early boot, are= also + * listed here. + * + * For vendor-specific leaves, a matching entry must be added to the CPUID= leaf + * vendor table later defined. Leaves which are here, but without a match= ing + * vendor entry, are treated by the CPUID parser as valid for all x86 vend= ors. + */ +#define CPUID_COMMON_ENTRIES \ + /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ =20 +/* + * CPUID leaf vendor table: + */ + +struct cpuid_vendor_entry { + unsigned int leaf; + u8 vendors[X86_VENDOR_NUM]; + u8 nvendors; +}; + +#define CPUID_VENDOR_ENTRY(_leaf, ...) \ + { \ + .leaf =3D _leaf, \ + .vendors =3D { __VA_ARGS__ }, \ + .nvendors =3D (sizeof((u8[]){__VA_ARGS__})/sizeof(u8)), \ + } + +#define CPUID_VENDOR_ENTRIES \ + /* Leaf Vendor list */ \ + #endif /* _ARCH_X86_CPUID_PARSER_H */ diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c index cf061ed45ce8..b8444fdf77dc 100644 --- a/arch/x86/xen/enlighten.c +++ b/arch/x86/xen/enlighten.c @@ -76,7 +76,7 @@ unsigned long xen_released_pages; static __ref void xen_get_vendor(void) { init_cpu_devs(); - cpuid_scan_cpu(&boot_cpu_data); + cpuid_scan_cpu_early(&boot_cpu_data); cpu_detect(&boot_cpu_data); get_cpu_vendor(&boot_cpu_data); } --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 45ED233120C for ; Fri, 27 Mar 2026 02:18:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577919; cv=none; b=Rf/xPn1k6snmpOukZOgVwdmvQKqKbOQg8aNJSDAo6RDW6kvbWZshYSvI3WZOiNDiM4lD1VzIvLjQCZv7niBg3QuBI57k057nmKACXgtJ7xq3yETmrB9rq6d600uPvqYn7jVXn32Sc/dQoHP5ImUBLKXy74i2Fr0VvzNGPWTWkUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577919; c=relaxed/simple; bh=3xZcFlNNGXIxppv/7LGQ6GIY6Fg/4a2a1lNmj5YQ+Pc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WBwI+oeQ2Tw8RO+p+sbLfJaJMp0JV5MAwhoiFTisXdZRKaL6UZzNxR77YfWKtK5mLjcCVqjL0p5yROo8FT8rXL9p57rdyWAo7BgIw0pD/KUpV28em2Ppe+hoKeThPUY1HXBby70bHb5k9oX28DM753gQTyfEvNImC40E94Sb+MQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xtKlO0re; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=n5Wi17bo; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xtKlO0re"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="n5Wi17bo" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 22/90] x86/cpuid: Introduce a parser debugfs interface Date: Fri, 27 Mar 2026 03:15:36 +0100 Message-ID: <20260327021645.555257-23-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the debugfs files "x86/cpuid/[0-ncpus]" to dump each CPU's cached CPUID table. For each cached leaf/subleaf, invoke the CPUID instruction on the target CPU and compare the hardware result against its cached values. Mark any mismatched cached CPUID output value with an asterisk. This should help with tricky bug reports in the future if the cached CPUID data get unexpectedly out of sync with actual hardware state. Note, expose cpuid_phases[] via "cpuid_parser.h" to allow the debugfs code to traverse and dump parsed CPUID data. Note, this debugfs interface also simplifies the development and testing of adding new leaves to the CPUID parser. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/Makefile | 2 +- arch/x86/kernel/cpu/cpuid_debugfs.c | 108 ++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.c | 9 ++- arch/x86/kernel/cpu/cpuid_parser.h | 12 ++++ 4 files changed, 125 insertions(+), 6 deletions(-) create mode 100644 arch/x86/kernel/cpu/cpuid_debugfs.c diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index d2e8a849f180..d62e2d60a965 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -62,7 +62,7 @@ obj-$(CONFIG_HYPERVISOR_GUEST) +=3D vmware.o hypervisor.= o mshyperv.o obj-$(CONFIG_BHYVE_GUEST) +=3D bhyve.o obj-$(CONFIG_ACRN_GUEST) +=3D acrn.o =20 -obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o +obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o cpuid_debugfs.o =20 obj-$(CONFIG_X86_BUS_LOCK_DETECT) +=3D bus_lock.o =20 diff --git a/arch/x86/kernel/cpu/cpuid_debugfs.c b/arch/x86/kernel/cpu/cpui= d_debugfs.c new file mode 100644 index 000000000000..4bd874bffffc --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_debugfs.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CPUID parser debugfs entries: x86/cpuid/[0-ncpus] + * + * Dump each CPU's cached CPUID table and compare its values against curre= nt + * CPUID output on that CPU. Mark changed entries with an asterisk. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "cpuid_parser.h" + +static void cpuid_this_cpu(void *info) +{ + struct cpuid_regs *regs =3D info; + + __cpuid(®s->eax, ®s->ebx, ®s->ecx, ®s->edx); +} + +static void +cpuid_show_leaf(struct seq_file *m, uintptr_t cpu_id, const struct cpuid_p= arse_entry *entry, + const struct leaf_parse_info *info, const struct cpuid_regs *cached) +{ + for (int j =3D 0; j < info->nr_entries; j++) { + u32 subleaf =3D entry->subleaf + j; + struct cpuid_regs regs =3D { + .eax =3D entry->leaf, + .ecx =3D subleaf, + }; + int ret; + + seq_printf(m, "Leaf 0x%08x, subleaf %u:\n", entry->leaf, subleaf); + + ret =3D smp_call_function_single(cpu_id, cpuid_this_cpu, ®s, true); + if (ret) { + seq_printf(m, "Failed to invoke CPUID on CPU %lu: %d\n\n", cpu_id, ret); + continue; + } + + seq_printf(m, " cached: %cEAX=3D0x%08x %cEBX=3D0x%08x %cECX=3D0x%= 08x %cEDX=3D0x%08x\n", + cached[j].eax =3D=3D regs.eax ? ' ' : '*', cached[j].eax, + cached[j].ebx =3D=3D regs.ebx ? ' ' : '*', cached[j].ebx, + cached[j].ecx =3D=3D regs.ecx ? ' ' : '*', cached[j].ecx, + cached[j].edx =3D=3D regs.edx ? ' ' : '*', cached[j].edx); + seq_printf(m, " actual: EAX=3D0x%08x EBX=3D0x%08x ECX=3D0x%08x= EDX=3D0x%08x\n", + regs.eax, regs.ebx, regs.ecx, regs.edx); + } +} + +static void __cpuid_debug_show(struct seq_file *m, uintptr_t cpu_id, + const struct cpuid_parse_entry *entry, int nr_entries) +{ + const struct cpuinfo_x86 *c =3D per_cpu_ptr(&cpu_info, cpu_id); + const struct cpuid_table *t =3D &c->cpuid; + + for (int i =3D 0; i < nr_entries; i++, entry++) { + const struct leaf_parse_info *qi =3D cpuid_table_info_p(t, entry->info_o= ffs); + const struct cpuid_regs *qr =3D cpuid_table_regs_p(t, entry->regs_offs); + + cpuid_show_leaf(m, cpu_id, entry, qi, qr); + } +} + +static int cpuid_debug_show(struct seq_file *m, void *p) +{ + uintptr_t cpu_id =3D (uintptr_t)m->private; + + for (int i =3D 0; i < cpuid_nphases; i++) + __cpuid_debug_show(m, cpu_id, cpuid_phases[i].table, cpuid_phases[i].nr_= entries); + + return 0; +} + +static int cpuid_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cpuid_debug_show, inode->i_private); +} + +static const struct file_operations cpuid_ops =3D { + .open =3D cpuid_debug_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static __init int cpuid_init_debugfs(void) +{ + struct dentry *dir; + uintptr_t cpu_id; + char cpu_name[24]; + + dir =3D debugfs_create_dir("cpuid", arch_debugfs_dir); + + for_each_possible_cpu(cpu_id) { + scnprintf(cpu_name, sizeof(cpu_name), "%lu", cpu_id); + debugfs_create_file(cpu_name, 0444, dir, (void *)cpu_id, &cpuid_ops); + } + + return 0; +} +late_initcall(cpuid_init_debugfs); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 97b7f296df03..ab736f03051e 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -74,14 +74,13 @@ static const struct cpuid_parse_entry cpuid_common_entr= ies[] =3D { CPUID_COMMON_ENTRIES }; =20 -static const struct { - const struct cpuid_parse_entry *table; - int nr_entries; -} cpuid_phases[] =3D { +const struct cpuid_phase cpuid_phases[] =3D { { cpuid_early_entries, ARRAY_SIZE(cpuid_early_entries) }, { cpuid_common_entries, ARRAY_SIZE(cpuid_common_entries) }, }; =20 +const int cpuid_nphases =3D ARRAY_SIZE(cpuid_phases); + /* * Leaf-independent parser code: */ @@ -189,7 +188,7 @@ cpuid_fill_table(struct cpuid_table *t, const struct cp= uid_parse_entry entries[] =20 static void __cpuid_scan_cpu_full(struct cpuinfo_x86 *c, bool early_boot) { - int nphases =3D early_boot ? 1 : ARRAY_SIZE(cpuid_phases); + int nphases =3D early_boot ? 1 : cpuid_nphases; struct cpuid_table *table =3D &c->cpuid; =20 for (int i =3D 0; i < nphases; i++) diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index a3f7dcc6c03f..8b0d44b745c5 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -149,6 +149,18 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ =20 +/* + * CPUID parser phases: + */ + +struct cpuid_phase { + const struct cpuid_parse_entry *table; + int nr_entries; +}; + +extern const struct cpuid_phase cpuid_phases[]; +extern const int cpuid_nphases; + /* * CPUID leaf vendor table: */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58F1134DCE3 for ; Fri, 27 Mar 2026 02:18:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577922; cv=none; b=EqMRVmxjhMD3c7reAUsCQutgjYQNGhqX4UvRN0uGKVJvBe2BX96x8pmqmIjAdfC362SpFymFhBbwlhA+G1X685+RYeBGCMU7d5Cc0NeK7Q+A/1NTawsqcT0y0aOgQvoFhaxlfOTRz3mAIiaL7aYr1LyqAfQ/SgdK+E+iU7UwNcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577922; c=relaxed/simple; bh=Ph8E/0SqHd0svolJKtL4halF+epl6iCeDICWLxbyi6o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l1GUpz8/TRU7U+ImH38AR9WVPKBC2xhc1v6c8woth28qk/+KHXeB+1CiVi8C9humRa7GMx8nkb36VHL17JqiwJDC9duoXtpqxFCzR1+DfrabNLv0lldPj6EzsraUo1LzvtyiNVhvSZhuWmzqaRGHw+zGcFWowwLVxM/1Us642ls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yWfON21q; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/GELOVqZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yWfON21q"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/GELOVqZ" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 23/90] x86/cpuid: Parse CPUID(0x16) Date: Fri, 27 Mar 2026 03:15:37 +0100 Message-ID: <20260327021645.555257-24-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID(0x16) support to the CPUID parser. The leaf enumerates the CPU's frequency information and is only supported on Intel machines. This allows converting CPUID(0x16) call sites to the CPUID APIs next. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 8be2c2ba874a..2939ad095f6c 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -206,6 +206,7 @@ struct cpuid_leaves { /* Leaf Subleaf number (or max number of subleaves) */ CPUID_LEAF ( 0x0, 0 ); CPUID_LEAF ( 0x1, 0 ); + CPUID_LEAF ( 0x16, 0 ); CPUID_LEAF ( 0x80000000, 0 ); CPUID_LEAF ( 0x80000002, 0 ); CPUID_LEAF ( 0x80000003, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 8b0d44b745c5..ee1958f3d369 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -144,6 +144,7 @@ struct cpuid_parse_entry { */ #define CPUID_COMMON_ENTRIES \ /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY ( 0x16, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ @@ -180,5 +181,6 @@ struct cpuid_vendor_entry { =20 #define CPUID_VENDOR_ENTRIES \ /* Leaf Vendor list */ \ + CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3CE233BBC8 for ; Fri, 27 Mar 2026 02:18:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577928; cv=none; b=C/8s9HfYVWj4KXt3Zu/QrBcCGVdAgWFpbSdWXoZEwHm3wsbU3IG3UULW8dQqG2vznLSlrnORKBUmbeNfFWYf1ic+pz13qLO4GLuX00MmVuTIBI/PuwreurI9AeLAyIT/BlCTfjVzgOcFuFUg5RjG9gyH0a+dBzfHYqFra9dl/NY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577928; c=relaxed/simple; bh=zAcpzQAnyMaPTodNtCzk42xC54CY5UVyljN8ExORnZs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Sp4x4Ohx5186Ih/f/dcMZL8KzAuteZNFKjx0HR3ntBJMM1r8PtNCD9emwPmNxrnLwpXbZowIrNDYTqz7g3Cgm7qy4WCUiqLwWqXAiQyVc2AB8FBdmkLtKPRgYUkERQ8PY7H5/Oa3T5md9qxt5c+rlaHkW6Sw3d8rBhsYX9FdKPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jdM5UPZs; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=98TxSn6n; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jdM5UPZs"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="98TxSn6n" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jfYVBQoce66nz4LJfS/86I1RI8IDv/X/UZeCKN4jjTg=; b=jdM5UPZsVrYnJQPZQmlRkWO+0TL+IPHX3PLSpmGDtkhdc0SpJxm726cMLU+Na4j6Y1sEBh FZxJraEayZAMFNsakpVkcx8SacvnZM1YskJyIYSplg6/pOenQS8y+kyzgdhJNxGU5/Jkz8 QRz6QnRuUlGklcWVqXldWg0wQBRNc7/+4+tkDL5PM7/tMT3dN42Y40hZGQRTVRl6MLYict F1HjTikJ3Kwn+z335/TvmvTnDAPntBNT7q1ifljLW8dHPBLQSqopCfQMHqXFu6d6lefP0K apc6ZlKaam9rz6sf7DmmcgonPL17P+nQpqR0YKgzzBBQdX2Atz0WThxvmqEXnA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jfYVBQoce66nz4LJfS/86I1RI8IDv/X/UZeCKN4jjTg=; b=98TxSn6n8L5O9wg6GUBMfjgl5afOmS8kw1D1Aac5O+5YIhosTCWxyI0CrJt+JCBiQoZZFJ k2UvLWC/Cs/i4bCg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 24/90] x86/tsc: Use parsed CPUID(0x16) Date: Fri, 27 Mar 2026 03:15:38 +0100 Message-ID: <20260327021645.555257-25-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the x86 timestamp counter code, use parsed CPUID(0x16) access instead of a direct CPUID query. Beside the CPUID parser centralization benefits, this allows using the auto-generated data types, and their full C99 bitfields, instead of doing ugly bitwise operations on CPUID output. Remove the "max standard level >=3D CPUID_LEVEL_FREQ" check since the CPUID parser API's NULL check is equivalent. Remove the Intel vendor check since the CPUID parser does a similar check before caching CPUID(0x16) output. Thus the CPUID API's NULL check is also equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/tsc.c | 24 +++++------------------- 1 file changed, 5 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index d9aa694e43f3..bc2838d69b19 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -671,6 +671,7 @@ static unsigned long quick_pit_calibrate(void) */ unsigned long native_calibrate_tsc(void) { + const struct leaf_0x16_0 *l16 =3D cpuid_leaf(&boot_cpu_data, 0x16); unsigned int eax_denominator, ebx_numerator, ecx_hz, edx; unsigned int crystal_khz; =20 @@ -712,13 +713,8 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz =3D=3D 0 && boot_cpu_data.cpuid_level >=3D CPUID_LEAF_FRE= Q) { - unsigned int eax_base_mhz, ebx, ecx, edx; - - cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx, &ecx, &edx); - crystal_khz =3D eax_base_mhz * 1000 * - eax_denominator / ebx_numerator; - } + if (crystal_khz =3D=3D 0 && l16) + crystal_khz =3D l16->cpu_base_mhz * 1000 * eax_denominator / ebx_numerat= or; =20 if (crystal_khz =3D=3D 0) return 0; @@ -745,19 +741,9 @@ unsigned long native_calibrate_tsc(void) =20 static unsigned long cpu_khz_from_cpuid(void) { - unsigned int eax_base_mhz, ebx_max_mhz, ecx_bus_mhz, edx; - - if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL) - return 0; - - if (boot_cpu_data.cpuid_level < CPUID_LEAF_FREQ) - return 0; - - eax_base_mhz =3D ebx_max_mhz =3D ecx_bus_mhz =3D edx =3D 0; - - cpuid(CPUID_LEAF_FREQ, &eax_base_mhz, &ebx_max_mhz, &ecx_bus_mhz, &edx); + const struct leaf_0x16_0 *l16 =3D cpuid_leaf(&boot_cpu_data, 0x16); =20 - return eax_base_mhz * 1000; + return l16 ? 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577928; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9zeSjqpMxnFLIpFIOFwXGmBAkNHSVzpkdG5/3aRyXI0=; b=ZfneDHEX7LxBwNU+PNP2ZnyZ76DCbQMxPb5AJEVNl5s2jh/KrBFGRv76y4kTjdOBPprifA aoM4ef8+5B5ByNsNmAPL7pi4wZc0aio5a9iGHWoGR7ZzIzBPVF/WqdB//I2jgq7Vf3XIkE sL55xNuMcV808CT+gpmJMfEpG39q7c4kZ6BgQ+0uWmJ/DpAcLFA7d5hqZcnVYu+bPjEXke ost52XcTYtc4wCm2BckWWBrHEmkM6m3dmsxPEIIuJe5IIL1dN7sfSD5LC6JXeuamwwFb7N hT9xvEGsiizpCdjyqmYuEZA25Bwo3lCX5SMf7znR24TkRQ4Pvh09hwFTwmcg2Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577928; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9zeSjqpMxnFLIpFIOFwXGmBAkNHSVzpkdG5/3aRyXI0=; b=EfHyqYRRAVyBILIQkaIHE0zI+G6TeO3dHAts0wv1TAqMIZQnLR62WdCN+hbrfQyvG4eRKN cmjcsZ19rnE6cKDQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 25/90] x86/cpuid: Parse Transmeta and Centaur extended ranges Date: Fri, 27 Mar 2026 03:15:39 +0100 Message-ID: <20260327021645.555257-26-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse the Transmeta extended CPUID(0x80860000)->CPUID(0x80860006) range. Reuse the CPUID(0x80000000) read function and its safety guards against CPUs repeating the output of the highest standard CPUID leaf. Transmeta's code at early_init_transmeta() already carries a similar guard. Parse Centaur/Zhaoxin extended CPUID(0xc0000000) and CPUID(0xc0000001). Add x86 vendor tags for the Transmeta and Centaur/Zhaoxin CPUID leaves so that they are not parsed on other vendors. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 13 ++++++++ arch/x86/kernel/cpu/cpuid_parser.c | 48 +++++++++++++++++++----------- arch/x86/kernel/cpu/cpuid_parser.h | 18 +++++++++++ 3 files changed, 61 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 2939ad095f6c..8cc9f81e9526 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -37,9 +37,13 @@ enum cpuid_regs_idx { =20 #define CPUID_BASE_START 0x00000000 #define CPUID_EXT_START 0x80000000 +#define CPUID_TMX_START 0x80860000 +#define CPUID_CTR_START 0xc0000000 =20 #define CPUID_BASE_END CPUID_RANGE_MAX(CPUID_BASE_START) #define CPUID_EXT_END CPUID_RANGE_MAX(CPUID_EXT_START) +#define CPUID_TMX_END CPUID_RANGE_MAX(CPUID_TMX_START) +#define CPUID_CTR_END CPUID_RANGE_MAX(CPUID_CTR_START) =20 /* * Types for CPUID(0x2) parsing: @@ -211,6 +215,15 @@ struct cpuid_leaves { CPUID_LEAF ( 0x80000002, 0 ); CPUID_LEAF ( 0x80000003, 0 ); CPUID_LEAF ( 0x80000004, 0 ); + CPUID_LEAF ( 0x80860000, 0 ); + CPUID_LEAF ( 0x80860001, 0 ); + CPUID_LEAF ( 0x80860002, 0 ); + CPUID_LEAF ( 0x80860003, 0 ); + CPUID_LEAF ( 0x80860004, 0 ); + CPUID_LEAF ( 0x80860005, 0 ); + CPUID_LEAF ( 0x80860006, 0 ); + CPUID_LEAF ( 0xc0000000, 0 ); + CPUID_LEAF ( 0xc0000001, 0 ); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index ab736f03051e..a7e6692f767b 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -42,24 +42,30 @@ cpuid_read_generic(const struct cpuid_parse_entry *e, c= onst struct cpuid_read_ou cpuid_read_subleaf(e->leaf, e->subleaf + i, regs); } =20 -static void -cpuid_read_0x80000000(const struct cpuid_parse_entry *e, const struct cpui= d_read_output *output) -{ - struct leaf_0x80000000_0 *el0 =3D (struct leaf_0x80000000_0 *)output->reg= s; - - cpuid_read_subleaf(e->leaf, e->subleaf, el0); - - /* - * Protect against Intel 32-bit CPUs lacking an extended CPUID range. A - * CPUID(0x80000000) query on such machines will repeat the output of the - * highest standard CPUID leaf instead. - */ - if (CPUID_RANGE(el0->max_ext_leaf) !=3D CPUID_EXT_START) - return; - - output->info->nr_entries =3D 1; +/* + * Define an extended range CPUID read function + * + * Guard against CPUs lacking the passed range leaf; e.g. Intel 32-bit CPU= s lacking + * CPUID(0x80000000). A query on such machines will just repeat the outpu= t of the + * highest standard CPUID leaf. + */ +#define define_cpuid_range_read_function(_range, _name) \ +static void \ +cpuid_read_##_range(const struct cpuid_parse_entry *e, const struct cpuid_= read_output *output) \ +{ \ + struct leaf_##_range##_0 *l =3D (struct leaf_##_range##_0 *)output->regs;= \ + \ + cpuid_read_subleaf(e->leaf, e->subleaf, l); \ + if (CPUID_RANGE(l->max_##_name##_leaf) !=3D _range) \ + return; \ + \ + output->info->nr_entries =3D 1; \ } =20 +define_cpuid_range_read_function(0x80000000, ext); +define_cpuid_range_read_function(0x80860000, tra); +define_cpuid_range_read_function(0xc0000000, cntr); + /* * CPUID parser tables: * @@ -115,10 +121,14 @@ static unsigned int cpuid_range_max_leaf(const struct= cpuid_table *t, unsigned i { const struct leaf_0x0_0 *l0 =3D __cpuid_table_subleaf(t, 0x0, 0); const struct leaf_0x80000000_0 *el0 =3D __cpuid_table_subleaf(t, 0x800000= 00, 0); + const struct leaf_0x80860000_0 *tl0 =3D __cpuid_table_subleaf(t, 0x808600= 00, 0); + const struct leaf_0xc0000000_0 *cl0 =3D __cpuid_table_subleaf(t, 0xc00000= 00, 0); =20 switch (range) { - case CPUID_BASE_START: return l0 ? l0->max_std_leaf : 0; - case CPUID_EXT_START: return el0 ? el0->max_ext_leaf : 0; + case CPUID_BASE_START: return l0 ? l0->max_std_leaf : 0; + case CPUID_EXT_START: return el0 ? el0->max_ext_leaf : 0; + case CPUID_TMX_START: return tl0 ? tl0->max_tra_leaf : 0; + case CPUID_CTR_START: return cl0 ? cl0->max_cntr_leaf : 0; default: return 0; } } @@ -180,6 +190,8 @@ cpuid_fill_table(struct cpuid_table *t, const struct cp= uid_parse_entry entries[] } ranges[] =3D { { CPUID_BASE_START, CPUID_BASE_END }, { CPUID_EXT_START, CPUID_EXT_END }, + { CPUID_TMX_START, CPUID_TMX_END }, + { CPUID_CTR_START, CPUID_CTR_END }, }; =20 for (unsigned int i =3D 0; i < ARRAY_SIZE(ranges); i++) diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index ee1958f3d369..76a87a71b430 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -149,6 +149,15 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80860000, 0, 0x80860000 ), \ + CPUID_PARSE_ENTRY ( 0x80860001, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80860002, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80860003, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80860004, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80860005, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80860006, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0xc0000000, 0, 0xc0000000 ), \ + CPUID_PARSE_ENTRY ( 0xc0000001, 0, generic ), \ =20 /* * CPUID parser phases: @@ -182,5 +191,14 @@ struct cpuid_vendor_entry { #define CPUID_VENDOR_ENTRIES \ /* Leaf Vendor list */ \ CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ + CPUID_VENDOR_ENTRY(0x80860000, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0x80860001, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0x80860002, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0x80860003, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0x80860004, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0x80860005, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0x80860006, X86_VENDOR_TRANSMETA), \ + CPUID_VENDOR_ENTRY(0xc0000000, X86_VENDOR_CENTAUR, X86_VENDOR_ZHAOXIN), \ + CPUID_VENDOR_ENTRY(0xc0000001, X86_VENDOR_CENTAUR, X86_VENDOR_ZHAOXIN), \ =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 577B03542D8 for ; Fri, 27 Mar 2026 02:18:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577934; cv=none; b=SAVo5IO3DLJIwZDQdm5mj/Mr/QzTx4YXlpHdvxjdtzspxmKK3CAj1RzMoZb7eNoyzlamy+3Er/tqB1any9fGMWGb7odrAgLsL7K0u5i1xDc6E0WIYVxiBRRRYDoylywfv7D0aOfIX5HryQMP0o/apZfsxsszx2RT8qcb5iHp5zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577934; c=relaxed/simple; bh=wRcuftV1npV2j+2TX6o5z7QUSArBVonRJszU42XfvT8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y509fk80r+4xpwiHl1QzoM7VN7BAo34AfNf/9LZZY9a4IymF8hMdqxqzd1eEyhUdV2WqPDwGBZ2eV/2dftsJBG6IUVC2GsoCegd+rHc/wc8F+L3WMiE4QIyyK2dc8ztQ3iAFZSS4yy3l0phkOhn02H+/o3eFhC2KFrA+N+Z4HkU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cKf3bgei; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q2h7pSWy; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cKf3bgei"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q2h7pSWy" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577932; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HIvVkXscnC8hnZxvl25NcJNOn/r3wHzaILQLs0FR6Nk=; b=cKf3bgeii9+RjP58CdeteFDE8KfKwpC8oSKJQMx3zOZqTedUkyeZxxJwo50WG2JeajDLBo ZRfnxc7Dskq9fdcqDXGdKZ7EcvgRI/ceZYHvOUCn00GAdl3YCzzA4PhU5GmT1wbmxDcL2J lPVDTL/L3xJE7kolusTK02lkHAd7FFQj1fwqlzo/F16dTLqMHG+LtuFmiF0raPZjDirBsh CPMYnXHbb6dN05z8zUYkiMr2eb5cD8fY8dhxmEj4s3GzMpUr4l3AQig309LllCOxDoRAhg bZXC7QrqgQfpnD0YYIgbWuYf5k7Mbafm/obznb2UR3RaHGQZhpJVnmNr0jYnsg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577932; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HIvVkXscnC8hnZxvl25NcJNOn/r3wHzaILQLs0FR6Nk=; b=Q2h7pSWyVazmTAgFShv8LdMyZ5G45VfLsTjtomegFHqvkDRsl9CeKRxhLQHAjI2TcRIaO9 h8TvGAAbn929IHBQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 26/90] x86/cpu: transmeta: Use parsed CPUID(0x80860000)->CPUID(0x80860006) Date: Fri, 27 Mar 2026 03:15:40 +0100 Message-ID: <20260327021645.555257-27-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80860000) to CPUID(0x80860006). Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their full C99 bitfields, instead of doing ugly bitwise operations on the CPUID output. Keep the x86_capability[] CPUID(0x80860001).EDX assignment. It will be removed when X86_FEATURE translation is integrated into the CPUID table. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/transmeta.c | 102 ++++++++++++++------------------ 1 file changed, 44 insertions(+), 58 deletions(-) diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmet= a.c index d9e0edb379b8..4b77dc1a7d9e 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -12,77 +12,63 @@ =20 static void early_init_transmeta(struct cpuinfo_x86 *c) { - u32 xlvl; + const struct leaf_0x80860000_0 *l =3D cpuid_leaf(c, 0x80860000); =20 - /* Transmeta-defined flags: level 0x80860001 */ - xlvl =3D cpuid_eax(0x80860000); - if ((xlvl & 0xffff0000) =3D=3D 0x80860000) { - if (xlvl >=3D 0x80860001) - c->x86_capability[CPUID_8086_0001_EDX] =3D cpuid_edx(0x80860001); - } + if (l && l->max_tra_leaf >=3D 0x80860001) + c->x86_capability[CPUID_8086_0001_EDX] =3D cpuid_edx(0x80860001); +} + +/* + * If CPU revision is 0x02000000, then CPUID(0x80860002) should be used in= stead. + */ +static bool is_legacy_revision(const struct leaf_0x80860001_0 *l1) +{ + return !(l1->cpu_rev_major =3D=3D 2 && l1->cpu_rev_minor =3D=3D 0 && + l1->cpu_rev_mask_major =3D=3D 0 && l1->cpu_rev_mask_minor =3D=3D 0); } =20 static void init_transmeta(struct cpuinfo_x86 *c) { - unsigned int cap_mask, uk, max, dummy; - unsigned int cms_rev1, cms_rev2; - unsigned int cpu_rev, cpu_freq =3D 0, cpu_flags, new_cpu_rev; - char cpu_info[65]; + const struct leaf_0x80860001_0 *l1 =3D cpuid_leaf(c, 0x80860001); + const struct leaf_0x80860002_0 *l2 =3D cpuid_leaf(c, 0x80860002); + const struct leaf_0x80860003_0 *l3 =3D cpuid_leaf(c, 0x80860003); + const struct leaf_0x80860004_0 *l4 =3D cpuid_leaf(c, 0x80860004); + const struct leaf_0x80860005_0 *l5 =3D cpuid_leaf(c, 0x80860005); + const struct leaf_0x80860006_0 *l6 =3D cpuid_leaf(c, 0x80860006); + unsigned int cap_mask, uk; =20 early_init_transmeta(c); =20 cpu_detect_cache_sizes(c); =20 - /* Print CMS and CPU revision */ - max =3D cpuid_eax(0x80860000); - cpu_rev =3D 0; - if (max >=3D 0x80860001) { - cpuid(0x80860001, &dummy, &cpu_rev, &cpu_freq, &cpu_flags); - if (cpu_rev !=3D 0x02000000) { - pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", - (cpu_rev >> 24) & 0xff, - (cpu_rev >> 16) & 0xff, - (cpu_rev >> 8) & 0xff, - cpu_rev & 0xff, - cpu_freq); - } + if (l1 && is_legacy_revision(l1)) { + pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", + l1->cpu_rev_major, l1->cpu_rev_minor, + l1->cpu_rev_mask_major, l1->cpu_rev_mask_minor, + l1->cpu_base_mhz); } - if (max >=3D 0x80860002) { - cpuid(0x80860002, &new_cpu_rev, &cms_rev1, &cms_rev2, &dummy); - if (cpu_rev =3D=3D 0x02000000) { - pr_info("CPU: Processor revision %08X, %u MHz\n", - new_cpu_rev, cpu_freq); - } + + if (l1 && l2 && !is_legacy_revision(l1)) { + pr_info("CPU: Processor revision %08X, %u MHz\n", + l2->cpu_rev_id, l1->cpu_base_mhz); + } + + if (l2) { pr_info("CPU: Code Morphing Software revision %u.%u.%u-%u-%u\n", - (cms_rev1 >> 24) & 0xff, - (cms_rev1 >> 16) & 0xff, - (cms_rev1 >> 8) & 0xff, - cms_rev1 & 0xff, - cms_rev2); + l2->cms_rev_major, l2->cms_rev_minor, + l2->cms_rev_mask_1, l2->cms_rev_mask_2, + l2->cms_rev_mask_3); } - if (max >=3D 0x80860006) { - cpuid(0x80860003, - (void *)&cpu_info[0], - (void *)&cpu_info[4], - (void *)&cpu_info[8], - (void *)&cpu_info[12]); - cpuid(0x80860004, - (void *)&cpu_info[16], - (void *)&cpu_info[20], - (void *)&cpu_info[24], - (void *)&cpu_info[28]); - cpuid(0x80860005, - (void *)&cpu_info[32], - (void *)&cpu_info[36], - (void *)&cpu_info[40], - (void *)&cpu_info[44]); - cpuid(0x80860006, - (void *)&cpu_info[48], - (void *)&cpu_info[52], - (void *)&cpu_info[56], - (void *)&cpu_info[60]); - cpu_info[64] =3D '\0'; - pr_info("CPU: %s\n", cpu_info); + + if (l3 && l4 && l5 && l6) { + u32 info[] =3D { + l3->cpu_info_0, l3->cpu_info_1, l3->cpu_info_2, l3->cpu_info_3, + l4->cpu_info_4, l4->cpu_info_5, l4->cpu_info_6, l4->cpu_info_7, + l5->cpu_info_8, l5->cpu_info_9, l5->cpu_info_10, l5->cpu_info_11, + l6->cpu_info_12, l6->cpu_info_13, l6->cpu_info_14, l6->cpu_info_15, + 0 /* Null terminator */, + }; + pr_info("CPU: %s\n", (char *)info); } =20 /* Unhide possibly hidden capability flags */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24857355F58 for ; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 27/90] x86/cpu: transmeta: Refactor CPU information printing Date: Fri, 27 Mar 2026 03:15:41 +0100 Message-ID: <20260327021645.555257-28-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the Transmeta init code has been converted to the CPUID API, refactor it into two separate functions for readability. No functional change. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/transmeta.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmet= a.c index 4b77dc1a7d9e..991e11d5c28a 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -27,19 +27,10 @@ static bool is_legacy_revision(const struct leaf_0x8086= 0001_0 *l1) l1->cpu_rev_mask_major =3D=3D 0 && l1->cpu_rev_mask_minor =3D=3D 0); } =20 -static void init_transmeta(struct cpuinfo_x86 *c) +static void print_cpu_revision(struct cpuinfo_x86 *c) { const struct leaf_0x80860001_0 *l1 =3D cpuid_leaf(c, 0x80860001); const struct leaf_0x80860002_0 *l2 =3D cpuid_leaf(c, 0x80860002); - const struct leaf_0x80860003_0 *l3 =3D cpuid_leaf(c, 0x80860003); - const struct leaf_0x80860004_0 *l4 =3D cpuid_leaf(c, 0x80860004); - const struct leaf_0x80860005_0 *l5 =3D cpuid_leaf(c, 0x80860005); - const struct leaf_0x80860006_0 *l6 =3D cpuid_leaf(c, 0x80860006); - unsigned int cap_mask, uk; - - early_init_transmeta(c); - - cpu_detect_cache_sizes(c); =20 if (l1 && is_legacy_revision(l1)) { pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", @@ -59,6 +50,14 @@ static void init_transmeta(struct cpuinfo_x86 *c) l2->cms_rev_mask_1, l2->cms_rev_mask_2, l2->cms_rev_mask_3); } +} + +static void print_cpu_info_string(struct cpuinfo_x86 *c) +{ + const struct leaf_0x80860003_0 *l3 =3D cpuid_leaf(c, 0x80860003); + const struct leaf_0x80860004_0 *l4 =3D cpuid_leaf(c, 0x80860004); + const struct leaf_0x80860005_0 *l5 =3D cpuid_leaf(c, 0x80860005); + const struct leaf_0x80860006_0 *l6 =3D cpuid_leaf(c, 0x80860006); =20 if (l3 && l4 && l5 && l6) { u32 info[] =3D { @@ -70,6 +69,17 @@ static void init_transmeta(struct cpuinfo_x86 *c) }; pr_info("CPU: %s\n", (char *)info); } +} + +static void init_transmeta(struct cpuinfo_x86 *c) +{ + unsigned int cap_mask, uk; + + early_init_transmeta(c); + cpu_detect_cache_sizes(c); + + print_cpu_revision(c); + print_cpu_info_string(c); =20 /* Unhide possibly hidden capability flags */ rdmsr(0x80860004, cap_mask, uk); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3A903563D7 for ; Fri, 27 Mar 2026 02:19:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577943; cv=none; b=YMjnb5SOsPiWM5XK7YMrEMo5+Pairm+ntqorriQgWfM+ADFGFkR3dqun9+MEjSKzVGnxsbH3b0yB2J7UuW9UNVM9hfBDuq0O2wqGillWdGybb7SSQJ+fns/MGqTcRKp4QQYC0R63AaRRQ8IVa7hibgVdpMs6lbuXBlC/K28cr7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577943; c=relaxed/simple; bh=jANKbqzBtZEK8LBdgBr9e53YS7Dh3TDy93qhGqKX2x0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sxvYAlPA/g7FEj4tHU8H3lut/KCLgWUmibYYmup3tmu780lH5qWF44dpl765lwM+HJYCUjmZFx3rDF4gCTbZYkGi53mYdZzaRctZAa5iDCSqLnpNp53dT4l+8/RLj3AgX7HbDnJbuPHhe4FLzMzc0N3DLg4oG09gAltAGabswbw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=06dDE2LI; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/3cNmJ9G; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="06dDE2LI"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/3cNmJ9G" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k6RexfKn63PVkV40YkO5QUPdJNYkFm5PzRZKkuBaxtE=; b=06dDE2LINebR3R871GYXU9Yoc35wmmPAdyWXO04zbCXL3pqOiigRM+jYoJhFgnmSuDyRFe 4RHf3iRX5fA3zcuyEaRtvg8AMYE+oOZ5600x/+qrm3/7JkfvmlJUy3x1+O9lQu4dUX4aUC xY3cqkkX4Nu/DjUwzVmX3GBy4TaDagaSBRFBUUomnn63S3xmt2UzSCAPFKBr7+2/EK+y3g sn/w14jjZ5Z6xAoLNUFAw0E/0e8uLkH2E4gPjHJ0iFEqo4J/4ReMYffr/ZOMwTGtAjVkot R6BhPuoutNFIEHvDrsEfKntHUzNqyyMSkRhs9KtEBNEEKQSWbz/WSBtVLJcj6Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577938; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k6RexfKn63PVkV40YkO5QUPdJNYkFm5PzRZKkuBaxtE=; b=/3cNmJ9G1FPF1OlirO3vxQmUPL2+jumGfbsWxbZEMQIFGS1uRDUDFNDljymvVzrXmLjsw4 MNoPyut9ReSG35Cg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 28/90] x86/cpu: centaur: Use parsed CPUID(0xc0000001) Date: Fri, 27 Mar 2026 03:15:42 +0100 Message-ID: <20260327021645.555257-29-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0xc0000001). Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their full C99 bitfields, instead of doing ugly bitwise operations on the CPUID output. Keep the x86_capability[] CPUID(0xc0000001).EDX assignment. It will be removed once X86_FEATURE translation is integrated into the CPUID model. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index a97e38fa6a9f..5f09bce3aaa7 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -12,34 +12,27 @@ =20 #include "cpu.h" =20 -#define ACE_PRESENT (1 << 6) -#define ACE_ENABLED (1 << 7) #define ACE_FCR (1 << 28) /* MSR_VIA_FCR */ - -#define RNG_PRESENT (1 << 2) -#define RNG_ENABLED (1 << 3) #define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */ =20 static void init_c3(struct cpuinfo_x86 *c) { - u32 lo, hi; - - /* Test for Centaur Extended Feature Flags presence */ - if (cpuid_eax(0xC0000000) >=3D 0xC0000001) { - u32 tmp =3D cpuid_edx(0xC0000001); + const struct leaf_0xc0000001_0 *l1 =3D cpuid_leaf(c, 0xc0000001); + u32 lo, hi; =20 - /* enable ACE unit, if present and disabled */ - if ((tmp & (ACE_PRESENT | ACE_ENABLED)) =3D=3D ACE_PRESENT) { + if (l1) { + /* Enable ACE unit, if present and disabled */ + if (l1->ace && !l1->ace_en) { rdmsr(MSR_VIA_FCR, lo, hi); - lo |=3D ACE_FCR; /* enable ACE unit */ + lo |=3D ACE_FCR; wrmsr(MSR_VIA_FCR, lo, hi); pr_info("CPU: Enabled ACE h/w crypto\n"); } =20 - /* enable RNG unit, if present and disabled */ - if ((tmp & (RNG_PRESENT | RNG_ENABLED)) =3D=3D RNG_PRESENT) { + /* Enable RNG unit, if present and disabled */ + if (l1->rng && !l1->rng_en) { rdmsr(MSR_VIA_RNG, lo, hi); - lo |=3D RNG_ENABLE; /* enable RNG unit */ + lo |=3D RNG_ENABLE; wrmsr(MSR_VIA_RNG, lo, hi); pr_info("CPU: Enabled h/w RNG\n"); } --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FF693563D7 for ; Fri, 27 Mar 2026 02:19:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577947; cv=none; b=F2sZYvqUP9Z2a8fF9nKjVcbBz2GutKtDVdQx4xB/lXiEhV1ff6xq/zDMRtRG7lfXmjpBu6EooWgVGxHO02WhvDKCOPbgFd4ZIxydX0VryfsrDDaXRJDFqrFtPFNOIBI4iDnG83McvCj2EdXAmqDwfoYJ8j7C9g90SunhIXOEzlo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577947; c=relaxed/simple; bh=IgI6mqDx6hhkfh2ojGvQfk9B8G/7cl48dQ2Q6H6JkKg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RaG/180cY5pBVNR6GvA/kKjBqRHSx1e+/dTyen1pDH5xIB8ly831uPHz8g2oNbGPVqjLbHkkuw8r8C7mbzGSZtkByZTwHPj9U8Mu+LiupE8N4lU3QHpl/anOrkCN4iKrC8NQ1rXqx+RjWD2ok8ZvngQe6shrYbQj4Uvt6PuAZdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VeXj0Qha; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3wXPN0i1; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VeXj0Qha"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3wXPN0i1" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577944; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x5TbfFLlOH7lWdPUYQq4CSUrTzKjrQx+hcGKkgKvmXM=; b=VeXj0QhaMaQu8+1tz052iTkK30iBSi5mwVek199T0DRa4kbpsx1YhLp7io3VMqNcq5rczg u6blk4fP7LlG7rTNf9oFsetmZoROp8QTx2VS9AuAnxSeM7wSim2jqhVTTVCY4n5ovhnSnm gTf4iSxboWyFSxi2NviTU2xCD/ll3dVt/uI+dAAZsiu1gmlzrSbL4hbK5yNzDYHSpdT0JK bhQC+HQ2LbXPKxmSG1Mo4z7S3txeD5anxBPgM1Em3/AZ3hCisOiTGxpXDTh+pnA4rNcxDD kQq+CscBxQkzCpIYBoYyNAKDnoOiOgGGXXoEm5TB+NyUlJMYFoaAEBSk3jNA8Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577944; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x5TbfFLlOH7lWdPUYQq4CSUrTzKjrQx+hcGKkgKvmXM=; b=3wXPN0i1EnOWiBVNfH72V6B6aLCSwOryM9FJBw7gEY65i35f4JM6kROFu152CjA3yZz0qV QVdpZRp9J6jqhWAA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 29/90] x86/cpu: zhaoxin: Use parsed CPUID(0xc0000001) Date: Fri, 27 Mar 2026 03:15:43 +0100 Message-ID: <20260327021645.555257-30-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0xc0000001). Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their full C99 bitfields, instead of doing ugly bitwise operations on the CPUID output. Keep the x86_capability[] CPUID(0xc0000001).EDX assignment. It will be removed once X86_FEATURE translation is integrated into the CPUID model. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/zhaoxin.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 55bc656aaa95..ea76e9594453 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -11,35 +11,26 @@ =20 #define MSR_ZHAOXIN_FCR57 0x00001257 =20 -#define ACE_PRESENT (1 << 6) -#define ACE_ENABLED (1 << 7) #define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */ - -#define RNG_PRESENT (1 << 2) -#define RNG_ENABLED (1 << 3) #define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */ =20 static void init_zhaoxin_cap(struct cpuinfo_x86 *c) { - u32 lo, hi; - - /* Test for Extended Feature Flags presence */ - if (cpuid_eax(0xC0000000) >=3D 0xC0000001) { - u32 tmp =3D cpuid_edx(0xC0000001); + const struct leaf_0xc0000001_0 *l1 =3D cpuid_leaf(c, 0xc0000001); + u32 lo, hi; =20 + if (l1) { /* Enable ACE unit, if present and disabled */ - if ((tmp & (ACE_PRESENT | ACE_ENABLED)) =3D=3D ACE_PRESENT) { + if (l1->ace && !l1->ace_en) { rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); - /* Enable ACE unit */ lo |=3D ACE_FCR; wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); pr_info("CPU: Enabled ACE h/w crypto\n"); } =20 /* Enable RNG unit, if present and disabled */ - if ((tmp & (RNG_PRESENT | RNG_ENABLED)) =3D=3D RNG_PRESENT) { + if (l1->rng && !l1->rng_en) { rdmsr(MSR_ZHAOXIN_FCR57, lo, hi); - /* Enable RNG unit */ lo |=3D RNG_ENABLE; wrmsr(MSR_ZHAOXIN_FCR57, lo, hi); pr_info("CPU: Enabled h/w RNG\n"); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7038340283 for ; Fri, 27 Mar 2026 02:19:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577953; cv=none; b=kmAs11mq4BQp3+qN99jQRpv+m48OgJHhG7914Mxx//2ue6YEn+Jz10IZABimcoQY92HAi3sxLHbTA74kTYlYgpO++Gh6cHTLZCFwj6VGde8WTErIXCbSIVRoYKAcPzm/N95/wdxSh1lw3Q/VnCNK+H5vVl7J+bpccRIKbjjsyXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577953; c=relaxed/simple; bh=xXzIVV9Yv9SDvzk/gkyDYEdAImp6ImyV9ovNyVj7XWs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hxsBbOIRUsFxlNt19/Fi9yU/2LWc9StIWja7Az2kCB7vwUS/8sBrHMmhGHLerl2MOMXmxAyDBT5P/0bpzzxYr+rQ8HgCmSXDXFIOmnMd1F3U//45rm48kMFu4mSjipr8YEw0tP/Y2Nag2c4cDvC2byILQZrN/xK06pQf7a9CJdo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BmAZ2MhV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GjKzcJFi; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BmAZ2MhV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GjKzcJFi" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577948; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GHzQRgWCR88w7lAuZhXQlIPfg8TpgZkJCXX0t/MBPNo=; b=BmAZ2MhVl11XGvly4N5OvurdYXq1973g/V65T88g76xMseMAdegAgzR3yrsSyyKVbpQ6wv FJyHplrvDjBckQZBk2nv9HTyBqatSy2YClC0L4thE3/pFZw06Z4XVz2AUgKXzzN/oJN4sJ BtIaxWw00N1GhXp5rEJLNNeKzg0VsrradKO/tNp3RhZsh9eniuDQ3N8/6JC1RhO8Ipm9Af VQueWPRlkSDtigfZTLEk4K/mXci7PreV03VQvE8JtNEu+exDsDOhTQ7mmJ4VGw8pejLUo9 2WnN7zgNhGi7v6jk7WTMlfM+sh46brNzVnUf13yemkyThJdJpL8veZtQR0GCNQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577948; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GHzQRgWCR88w7lAuZhXQlIPfg8TpgZkJCXX0t/MBPNo=; b=GjKzcJFizASF5B6YtZFGmgR0JWdBR4rTdCq0P1WLxKuJ4nIj7yeUpXfHXNMUEdTKuqQV9b ohZ9O8MLO4aeUEDA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 30/90] x86/cpuid: Parse CPUID(0x2) Date: Fri, 27 Mar 2026 03:15:44 +0100 Message-ID: <20260327021645.555257-31-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse CPUID(0x2). Query it only for Intel, Centaur, and Zhaoxin, given that kernel/cpu/cacheinfo.c :: init_intel_cacheinfo() is called by: kernel/cpu/intel.c cpu_dev.c_x86_vendor =3D X86_VENDOR_INTEL kernel/cpu/centaur.c cpu_dev.c_x86_vendor =3D X86_VENDOR_CENTAUR kernel/cpu/zhaoxin.c cpu_dev.c_x86_vendor =3D X86_VENDOR_ZHAOXIN At the CPUID tables, keep CPUID(0x2) marked as invalid if the whole leaf, or all of its output registers separately, were malformed. Note, cpuid_leaf_0x2() at will be removed once all call sites are transformed to new CPUID APIs. References: fe78079ec07f ("x86/cpu: Introduce and use CPUID leaf 0x2 parsin= g helpers") Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.c | 36 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 3 files changed, 39 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 8cc9f81e9526..c35de721f652 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -210,6 +210,7 @@ struct cpuid_leaves { /* Leaf Subleaf number (or max number of subleaves) */ CPUID_LEAF ( 0x0, 0 ); CPUID_LEAF ( 0x1, 0 ); + CPUID_LEAF ( 0x2, 0 ); CPUID_LEAF ( 0x16, 0 ); CPUID_LEAF ( 0x80000000, 0 ); CPUID_LEAF ( 0x80000002, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index a7e6692f767b..be340b202182 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -42,6 +42,42 @@ cpuid_read_generic(const struct cpuid_parse_entry *e, co= nst struct cpuid_read_ou cpuid_read_subleaf(e->leaf, e->subleaf + i, regs); } =20 +static void +cpuid_read_0x2(const struct cpuid_parse_entry *e, const struct cpuid_read_= output *output) +{ + union leaf_0x2_regs *regs =3D (union leaf_0x2_regs *)output->regs; + struct leaf_0x2_0 *l =3D (struct leaf_0x2_0 *)output->regs; + int invalid_regs =3D 0; + + /* + * All Intel CPUs must report an iteration count of 1. For broken hardwar= e, + * keep the leaf marked as invalid at the CPUID table. + */ + cpuid_read_subleaf(e->leaf, e->subleaf, l); + if (l->iteration_count !=3D 0x01) + return; + + /* + * The most significant bit (MSB) of each CPUID(0x2) register must be cle= ar. + * If a register is malformed, replace its 1-byte descriptors with NULL. + */ + for (int i =3D 0; i < 4; i++) { + if (regs->reg[i].invalid) { + regs->regv[i] =3D 0; + invalid_regs++; + } + } + + /* + * If all of the CPUID(0x2) output registers were malformed, keep the leaf + * marked as invalid at the CPUID table. + */ + if (invalid_regs =3D=3D 4) + return; + + output->info->nr_entries =3D 1; +} + /* * Define an extended range CPUID read function * diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 76a87a71b430..1de239370652 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -144,6 +144,7 @@ struct cpuid_parse_entry { */ #define CPUID_COMMON_ENTRIES \ /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY ( 0x2, 0, 0x2 ), \ CPUID_PARSE_ENTRY ( 0x16, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ @@ -190,6 +191,7 @@ struct cpuid_vendor_entry { =20 #define CPUID_VENDOR_ENTRIES \ /* Leaf Vendor list */ \ + CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x80860000, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860001, X86_VENDOR_TRANSMETA), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FC341F239B for ; Fri, 27 Mar 2026 02:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577956; cv=none; b=qRgat5OHx1GwXnJKvYl9c4rK6Z7ww5jZSC/GY+wz8YpE9rN4XZmSiviA4EXNXc8DW3f7ymAyd+ugcZlN14udbwHxJLqq9wFRry3pVtIhxkZytKeonvMi8M7cS8+CJTQj16QrcIVNVMN7cDm+dbe4uOXniBNW5P/E75weAwxiKR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577956; c=relaxed/simple; bh=hwVcyDnhYE9Ew8mWfAAdg/BA04xn7srypYUGwIGNpvo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CueVcJo2lz8vr1Tg4XUfHryAUjVsq0gRA5Y+7TocYSPxMvpG8GXdDqPn51d6k9mHKZaT0V+YLu3XC76DcyluC8CO1I1xKR2R/77NEhBH5yBy7cBAYIldTGUVDUvq4sRE37wSoTBPygo06mms9+bEoCy2s7/7dAkCwZNlZJqGGyM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KF2d8+i5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=YqnH6KaH; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KF2d8+i5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="YqnH6KaH" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577952; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UUQ76hlD26YEpumyfNSfOXMLQXNffvEAUoB8LCX9+mM=; b=KF2d8+i5QLjXQptX4EN17Ya8ckBvdX5XITYRTqSm/5axap/fb7ETx1dxoOnWw0qwgAjZcI 1DoCoRfTlcCqQreuJZXE4lughRLHYFOnrQQwldKJevzYhrdDYDNA1cAIIiRDtiUaCNEGOc 3VMNxfkF4FDiR21x00EMXyeS3Dm4eu8aQEYE/VtCVdykTTxFEQrE0FSyYURsMHbNLcZOGU 1FA+GJx/0YR4yLPtuizm5cJtEN+HvbRZzPU7wMGNfmCkapL9n1gumRpIoVdrDy1UIar48A +fITjgA2bZDuASzHhbEa7r+OIZ32uRlEAVFVVFcRa9OoKjhZ+WKT1TX217LiZw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577952; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UUQ76hlD26YEpumyfNSfOXMLQXNffvEAUoB8LCX9+mM=; b=YqnH6KaHeatTKx3JxQtPYcXF4kIusu1F3+YI1U3OB4wxNdfVTWzoaqJWdxDh7ePuzxasCD tJEPyWLZh8YqOhBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 31/90] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Date: Fri, 27 Mar 2026 03:15:45 +0100 Message-ID: <20260327021645.555257-32-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CPUID(0x2) output includes a "query count" byte. That byte was supposed to specify the number of repeated CPUID(0x2) subleaf 0 queries needed to extract all of the CPU's cache and TLB descriptors. Per current Intel manuals, all CPUs supporting this leaf "will always" return an iteration count of 1. Since the CPUID parser ignores any CPUID(0x2) output with an invalid iteration count, lightly warn about this once in the kernel log. Do not emit a warning if some of the CPUID(0x2) output registers, or even all of them, are invalid. This is an architecturally-defined response. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish References: b5969494c8d8 ("x86/cpu: Remove CPUID leaf 0x2 parsing loop") Link: https://lore.kernel.org/lkml/aBnmy_Bmf-H0wxqz@gmail.com --- arch/x86/kernel/cpu/cpuid_parser.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index be340b202182..bddd9937bb2b 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -3,6 +3,8 @@ * CPUID parser; for populating the system's CPUID tables. */ =20 +#define pr_fmt(fmt) "x86/cpuid: " fmt + #include =20 #include @@ -54,8 +56,11 @@ cpuid_read_0x2(const struct cpuid_parse_entry *e, const = struct cpuid_read_output * keep the leaf marked as invalid at the CPUID table. */ cpuid_read_subleaf(e->leaf, e->subleaf, l); - if (l->iteration_count !=3D 0x01) + if (l->iteration_count !=3D 0x01) { + pr_warn_once("Ignoring CPUID(0x2) due to invalid iteration count =3D %d", + l->iteration_count); return; + } =20 /* * The most significant bit (MSB) of each CPUID(0x2) register must be cle= ar. --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF7FE35DA47 for ; Fri, 27 Mar 2026 02:19:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577959; cv=none; b=oVTYdWc2nWr+ZT6ROR3HZoSFADsMMwzU9/H0TfhetNVaqXMJHGSy8hvixWV4+M37PzayTNFKXTcsOeiR/bQS3L3rw7k6iEgMa7cTZsuD0WL9hdRMFtdYngV4WniDzeakX/dB25ok1s2qJkPqnrgFLWJn0xrP2Wxr6FXFPZffUdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577959; c=relaxed/simple; bh=iQjlFScldU4IMStGVabPqPh0nbFX6tJCbXqWGmKN9Qc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iNtwob82wFuQF1Frhx+WocO1Wk+k1A0FxFvZF8zag+/cr20LCQiUysNAwToNfus2yi8Z9HfeAxY+B2ym9l4HDKakKH5AK5xdiy+8AN/NjHbBtXLscUpayUbfIiKWPVuopZV0tpIQgbpnBwC3EIQKdoQ6wSUwKWUNcKexfKYnBek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TytpIgaT; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WOcaf13i; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TytpIgaT"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WOcaf13i" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mvSRQqnY5eJAqQpd/YqUJyBnYGcpW3VxWZgxDKn0twk=; b=TytpIgaTGr31yV13RErPw/0ioN952Z6BrJyjqrl+n+WfSGKdbCR45jyXjnwM+fuwrvCL54 Qsj0fb5l72uUltULSKdidjQJeAFZIRDxyl01LzN0atIuuwiiUtgHtLw6FZ1ysjg2aIzbLy x++1FSlJG1h3F41bLI74qJviP0RB3yEE8++8553IE9R73fTNS6BaHQRYm+fruMuzcvWRL3 1mVuzgJR9O+RKlITvV11C7Eh78uOj+lJaqYmHT9O1aKbZITlhAJ7SpBBTxM4WNwcwIylRO bREvOgVw2QsstKDkCaMuUE87QAiaAmMabF8XRA2iqu3QJw/oLwnzDKggmoDtMg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577956; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mvSRQqnY5eJAqQpd/YqUJyBnYGcpW3VxWZgxDKn0twk=; b=WOcaf13iORy1nyYlWUF2RWgfcInhx8JCTCey9ABrr45KOh9W2LQTGSI9eX9ypTAMmEOxyg eDiH/P1te94ag4CQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 32/90] x86/cpuid: Introduce parsed CPUID(0x2) API Date: Fri, 27 Mar 2026 03:15:46 +0100 Message-ID: <20260327021645.555257-33-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new iterator, for_each_parsed_cpuid_0x2_desc(), for retrieving parsed CPUID(0x2) entries as 1-byte descriptors. This new macro is aimed to replace for_each_cpuid_0x2_desc(), which operates on directly queried CPUID data instead. Assert that the passed "regs" are the same size as "union leaf_0x2_regs". Use a size equivalence check, instead of a typeof() check, to give callers the freedom to either pass a "struct cpuid_regs" pointer or a "struct leaf_0x2_0" pointer; where both can returned by the parsed CPUID API at . This size comparison matches what other kernel CPUID APIs do; e.g. cpuid_read() and cpuid_read_subleaf() at . Put the size equivalence check inside a GNU statement expression, ({..}) so that it can be placed inside the macro's loop initialization. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 43 ++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 3d5a0d4918cc..a55a28e9f0f6 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -528,6 +528,49 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) __cpuid_table_nr_filled_subleaves(&(_cpuinfo)->cpuid, _leaf, n); \ }) =20 +/* + * Convenience leaf-specific functions (using parsed CPUID data): + */ + +/* + * CPUID(0x2) + */ + +/** + * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors + * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_raw() + * @_ptr: u8 pointer, for macro internal use only + * @_desc: Pointer to parsed descriptor information at each iteration + * + * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers + * @_regs. Provide the parsed information for each descriptor through @_d= esc. + * + * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB + * descriptors, switch on @_desc->t_type. + * + * Example usage for cache descriptors:: + * + * const struct leaf_0x2_table *desc; + * const struct cpuid_regs *regs; + * const u8 *ptr; + * + * regs =3D cpuid_leaf_raw(c, 0x2); + * if (!regs) { + * // Handle error + * } + * + * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * switch (desc->c_type) { + * ... + * } + * } + */ +#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ + for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ + _ptr =3D &((const union leaf_0x2_regs *)(_regs))->desc[1]; \ + _ptr < &((const union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = =3D &cpuid_0x2_table[*_ptr]);\ + _ptr++) + /* * CPUID parser exported APIs: */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C45333555B for ; Fri, 27 Mar 2026 02:19:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577965; cv=none; b=bKXs+35/ofz2wnJoEzzZxHwX6r+C09b/9pJtejM6L71IT4iSTECtg9Lxqf3srZ7QyoegvHU8LGJruslU84IoXyJN3YFPAmiwtDQZeR6dZIdid44TRDSXFg7FQ7Y4/vg6ljwZtnsGlVUDDkt6FgOWlKnie5VnDIXPzNdfMzNEuz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577965; c=relaxed/simple; bh=4UemQ89kiKz0dglcmIm9obRlF5+D8CFqfiq3knbz+0U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=deAWkj1Z0m39ogQwqwIXLqy+GuAyGYa2TeQt1z4SNpf5nhLAiV+b5vuO2HOZooC8ZIghD9totpKs+gu3HqEVKxFaJXR/HjbhAmMCU9qBVLs+45Ct3nXyY0/TlaHEOtUxACBxOX4zILgwu5kDiL1JAijIUuBrIz7d5t1jaHCYPq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NpS8XhQm; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=w0JlEiIK; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NpS8XhQm"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="w0JlEiIK" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 33/90] x86/cpu: Use parsed CPUID(0x2) Date: Fri, 27 Mar 2026 03:15:47 +0100 Message-ID: <20260327021645.555257-34-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At the Intel cacheinfo code, use parsed CPUID(0x2) access instead of a direct CPUID query. Remove the "maximum standard CPUID level >=3D 0x2" check as the parsed CPUID API output NULL check is equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 08869fecdf30..cad66ca14ca4 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -722,14 +722,14 @@ static void intel_tlb_lookup(const struct leaf_0x2_ta= ble *desc) static void intel_detect_tlb(struct cpuinfo_x86 *c) { const struct leaf_0x2_table *desc; - union leaf_0x2_regs regs; - u8 *ptr; + const struct cpuid_regs *regs; + const u8 *ptr; =20 - if (c->cpuid_level < 2) + regs =3D cpuid_leaf_raw(c, 0x2); + if (!regs) return; =20 - cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, desc) + for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F08123451CE for ; Fri, 27 Mar 2026 02:19:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577967; cv=none; b=XCFntBQdxXg82LZKYmYn+8Cy8AciXPEiVf6kpHb48mjpllwChXFYVDUshv9tgbfsMX1DdFbwqQEyruMCw4jRwH6iV2CNWYIkTK+NfdSzNRoeSoSFqUVxEGPRn3HAld7SmYcf9PpRoIzslu1Zr6MLLAts158tlYrguNST3xMIw8o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577967; c=relaxed/simple; bh=j0NNmTULtzs6O4gYMrb0bGW6VO6yqIZUGKoUspmhHZ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DbsyBfm0uWt1yh2Qi4ecgyKZAFeGh/m/MPGvr/g4vtP6eqx6eKd8wVzEdHuTs1fEgo4EgA5L/oOd0Y4BPK1ba29m2GKGJCcvBA31+rdia2gHnqNtTRtcc8vgjpKyRlYbBAbKAWRxhEdWqPzqS7b829DOD7IVXggzVfEx4S2yJTE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sQcPt0Yz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sj8VoFt2; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sQcPt0Yz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sj8VoFt2" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577964; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/W83RmVy3CtvFXEUSfKwuQmP/1LVkuagddT/fO9nTeM=; b=sQcPt0Yz4DyRtQuz9A5bQtIeFOkCYcHURL18tHbnYf2v/h9WIMkbVP8Z/zFOxlDtqSysat N1CFzGirSelWjUkAG+IDkuCBIN8z1TzV6kIPY1ETeutvoQZFhPDv3w6qQa8IHcNwJI1c99 BHrpv3v+S5gA9w6kupOTlL3bCT+96LUjQEOY+Wj2X5LrujiSyvd21IBqsvNVPSYf86f5JK DVIwbf1kHCNvXFTNRDvDB29/pOafCfHd4X35sOI+lsRpYnaETtJASILfkCf0phNW4N/MRZ mlNem65d7zm5ETJf73xXqVYYFDezQUf/BukC/eu+gF8QYi3RRh67UO7SXiGpXA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577964; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/W83RmVy3CtvFXEUSfKwuQmP/1LVkuagddT/fO9nTeM=; b=sj8VoFt29Tndb08pxsGGGDaYTmpj2uOZUYzhHEFps9PYRDniGbDGEulGtK0Ym15aOgcfgQ 9n4OjWv4qbmjnHCg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 34/90] x86/cacheinfo: Use parsed CPUID(0x2) Date: Fri, 27 Mar 2026 03:15:48 +0100 Message-ID: <20260327021645.555257-35-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x2) instead of directly invoking CPUID queries. Remove the max CPUID level check; checking cpuid_leaf_raw()'s result for NULL is enough. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 51a95b07831f..6fded356f2ee 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -391,14 +391,14 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; const struct leaf_0x2_table *desc; - union leaf_0x2_regs regs; - u8 *ptr; + const struct cpuid_regs *regs; + const u8 *ptr; =20 - if (c->cpuid_level < 2) + regs =3D cpuid_leaf_raw(c, 0x2); + if (!regs) return; =20 - cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, desc) { + for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 287C035F5E9 for ; Fri, 27 Mar 2026 02:19:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577970; cv=none; b=teKPEb5+fj2Pn7Q04i4Yowxx4+ybfLNQnTIHTYFzYTUiYmk1uyejaHH1gVAjawbZdWdSkdYj6mFkvIrLi0ODjQlh4rxGn4vZL+TU0asY8CtSRFezYBgETUMFqGTliGMKXQWcZFXMT1KeGCtmLu7bKxSvYGNebvIapMk4G5NM0gI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577970; c=relaxed/simple; bh=RULpbLxbNlVq+EeoLY3yYwrqWKJmNS5WOIz/wcF3fm0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XFfteFrSj4pafxDw4b3qXGY3vFu/bhfBJXJqQY7YfXNlG7x0N95nsZfbylQ+R99Mg644oR1QMdKJpZWCguJkp2PBnDkFCP0WTEfxAIAzHXYsbjlmUBKjdoixYuPgwHGfxEErFsaHP5ElHQpngaPdAPGo6Zsc0tMB5yULiKqIds0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nUtVKlUQ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OrnsmqDZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nUtVKlUQ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OrnsmqDZ" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577967; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sHpJLAcOnOF0ZFw62U1gI+XJHrjztCQBbGrsdL17gw8=; b=nUtVKlUQ2uyrZUmJTZdiZ9H1+Yzou0pSn+rs74P6cYnTDudd1v3BdM+FoaK0YZXkCPxAad ahu7XF+uijRocMSGVm4QEcYiyDTFkWWYsnJG5+NQBv92JZzoz0DLTacTPr7XSkBt4sTAHU 2kIU9dfWBYwhxXmKwVJqIvb7Zc8mQDaROPNiV4inYhGSfUUBKXYJA0d60Uh/RYeDYDdKQU 4IdPMuc3JPZAwGjgwM0dRPRXoq+ArDfft6tY4IKYVBIVA08YCt12BmEU1LpniGpy02nBrI 6kTp2dZbSiG6M+pibPK6jEZMVaYf9W6bQJrNhr35fapuz8ewf8ohRsJ8+wzHEg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577967; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sHpJLAcOnOF0ZFw62U1gI+XJHrjztCQBbGrsdL17gw8=; b=OrnsmqDZb8qoBfqmz1MuF4eSc85Zl1DsVk6AuRRij+o0WoHGmmGPv9jlcKMLrvL9wV4hsh aNQGNVaHX+gePfCg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 35/90] x86/cpuid: Remove direct CPUID(0x2) query helpers Date: Fri, 27 Mar 2026 03:15:49 +0100 Message-ID: <20260327021645.555257-36-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All call sites at x86/cpu and x86/cacheinfo have been converted from directly invoking CPUID(0x2) queries to parsed CPUID access. Remove the direct CPUID(0x2) query helpers cpuid_leaf_0x2() for_each_cpuid_0x2_desc() And rename the parsed CPUID(0x2) iterator macro for_each_parsed_cpuid_0x2_desc() back to for_each_cpuid_0x2_desc() since by now only parsed CPUID(0x2) access is allowed. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 75 ++------------------------------ arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/intel.c | 2 +- 3 files changed, 5 insertions(+), 74 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index a55a28e9f0f6..f4bdfe3c9325 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -212,75 +212,6 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) return 0; } =20 -/* - * CPUID(0x2) parsing: - */ - -/** - * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output - * @regs: Output parameter - * - * Query CPUID(0x2) and store its output in @regs. Force set any - * invalid 1-byte descriptor returned by the hardware to zero (the NULL - * cache/TLB descriptor) before returning it to the caller. - * - * Use for_each_cpuid_0x2_desc() to iterate over the register output in - * parsed form. - */ -static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) -{ - cpuid_read(0x2, regs); - - /* - * All Intel CPUs must report an iteration count of 1. In case - * of bogus hardware, treat all returned descriptors as NULL. - */ - if (regs->desc[0] !=3D 0x01) { - for (int i =3D 0; i < 4; i++) - regs->regv[i] =3D 0; - return; - } - - /* - * The most significant bit (MSB) of each register must be clear. - * If a register is invalid, replace its descriptors with NULL. - */ - for (int i =3D 0; i < 4; i++) { - if (regs->reg[i].invalid) - regs->regv[i] =3D 0; - } -} - -/** - * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors - * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() - * @_ptr: u8 pointer, for macro internal use only - * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration - * - * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers - * @_regs. Provide the parsed information for each descriptor through @_d= esc. - * - * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB - * descriptors, switch on @_desc->t_type. - * - * Example usage for cache descriptors:: - * - * const struct leaf_0x2_table *desc; - * union leaf_0x2_regs regs; - * u8 *ptr; - * - * cpuid_leaf_0x2(®s); - * for_each_cpuid_0x2_desc(regs, ptr, desc) { - * switch (desc->c_type) { - * ... - * } - * } - */ -#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ - for (_ptr =3D &(_regs).desc[1]; \ - _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ - _ptr++) - /* * CPUID(0x80000006) parsing: */ @@ -537,7 +468,7 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) */ =20 /** - * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors + * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_raw() * @_ptr: u8 pointer, for macro internal use only * @_desc: Pointer to parsed descriptor information at each iteration @@ -559,13 +490,13 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) * // Handle error * } * - * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * for_each_cpuid_0x2_desc(regs, ptr, desc) { * switch (desc->c_type) { * ... * } * } */ -#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ +#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ _ptr =3D &((const union leaf_0x2_regs *)(_regs))->desc[1]; \ _ptr < &((const union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = =3D &cpuid_0x2_table[*_ptr]);\ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 6fded356f2ee..d933d58a5a61 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -398,7 +398,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + for_each_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index cad66ca14ca4..615e3a4872b7 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -729,7 +729,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) + for_each_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D025346769 for ; Fri, 27 Mar 2026 02:19:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577973; cv=none; b=CMmuETPeH3lRVfnaxpenQZDm09HjASqJydu7x5CJAbJz6ImdNdF7YfD8K/StThhEbfPQIEoHbeSYirGzj/geA3DOgnyhy3kWBsScZ35ilFYMvIUDq+TRaPV9e+e5XpJ1Lnu9vbC+xR3Pia9/VKk43U+oJawIAIdF58wEBG5CNZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577973; c=relaxed/simple; bh=UI1ZimJbjEMLHwr4UDp7Hv3AfqPqElFAYKVIRZOWOLI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X0GBFnWevt03trceyWhZYQYl7Uv0ZiDy9a2082s6u4ZX/E7rL/CkQpEN4Ay9Dnur/lbnE3K7GWe/ZQ35gjnBlyjNZv750NzXoBs7yn6Omr2GpiojFhIjStS4h7CB7Iry2HJ8sf6G+vKCkeqpM96cS/j9pIS1xoje67z+5R816WE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=FzdtuYMG; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yM1zulr3; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="FzdtuYMG"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yM1zulr3" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577970; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZLBwHVoHoGi6f0Xxmk8tkpKmkAoxCT8HbQBo5YmiRX4=; b=FzdtuYMGaU9JvJBsHwLiO0w8IG6lO2XuMEr0xzK8/xfB86BariBxmHXoCTB32jG5Mv55n2 MD6/BKoacZxYlyweWsbgbPKWAgHn9rgImJ9BTmV7NhYKhffFwdnKV1KnjDvizIXpj63CMu rP48jNm1TyU0SIknA20ccxd8WtW8o5pViMGAiQK2ztVn6ZUrzGnRxMcJS9kjkWsW9Sxfvz Tv4VfnfhSRLGRKQ02H7p8q5so+u59XPVLZ0uaP0rz9DCKj2Rnmzx04UfykaO3U49ow6MNb XJJltclm8AJrI7pohy2dVqgH5tLTfp2VPFzCI+B6p+w5EU8FGIO7P5eGIZudlg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577970; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZLBwHVoHoGi6f0Xxmk8tkpKmkAoxCT8HbQBo5YmiRX4=; b=yM1zulr3rZRYIq7hlK8yNFy9KEGlY5niS+fM5BUCRlc8OQtQsXEl6VFJlze+AEOPnsUlTe oVhJY3wq3lhGFGAw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 36/90] x86/cpuid: Parse deterministic cache parameters CPUID leaves Date: Fri, 27 Mar 2026 03:15:50 +0100 Message-ID: <20260327021645.555257-37-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse CPUID(0x4) and CPUID(0x8000001d). Query CPUID(0x4) only for Intel, Centaur, and Zhaoxin as these are the x86 vendors where it is supported. Query CPUID(0x8000001d) for AMD and Hygon. Define a single CPUID parser read function for both leaves, as they have the same subleaf cache enumeration logic. Introduce the macro define_cpuid_read_function() to avoid code duplication between the CPUID parser default read function, cpuid_read_generic(), and the new CPUID(0x4)/CPUID(0x8000001d) logic. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 2 ++ arch/x86/kernel/cpu/cpuid_parser.c | 40 +++++++++++++++++++++++------- arch/x86/kernel/cpu/cpuid_parser.h | 4 +++ 3 files changed, 37 insertions(+), 9 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index c35de721f652..f77659303569 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -211,11 +211,13 @@ struct cpuid_leaves { CPUID_LEAF ( 0x0, 0 ); CPUID_LEAF ( 0x1, 0 ); CPUID_LEAF ( 0x2, 0 ); + CPUID_LEAF_N ( 0x4, 8 ); CPUID_LEAF ( 0x16, 0 ); CPUID_LEAF ( 0x80000000, 0 ); CPUID_LEAF ( 0x80000002, 0 ); CPUID_LEAF ( 0x80000003, 0 ); CPUID_LEAF ( 0x80000004, 0 ); + CPUID_LEAF_N ( 0x8000001d, 8 ); CPUID_LEAF ( 0x80860000, 0 ); CPUID_LEAF ( 0x80860001, 0 ); CPUID_LEAF ( 0x80860002, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index bddd9937bb2b..99507e99d8d9 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -31,18 +31,34 @@ static const struct cpuid_vendor_entry cpuid_vendor_ent= ries[] =3D { * Leaf read functions: */ =20 +/** + * define_cpuid_read_function() - Generate a CPUID parser read function + * @suffix: Generated function name suffix (full name becomes: cpuid_read_= @suffix()) + * @_leaf_t: Type to cast the CPUID output storage pointer + * @_leaf: Name of the CPUID output storage pointer + * @_break_c: Condition to break the CPUID parsing loop, which may referen= ce @_leaf, + * and where @_leaf stores each iteration's CPUID output. + * + * Define a CPUID parser read function according to the requirements state= d at + * 'struct cpuid_parse_entry'->read(). + */ +#define define_cpuid_read_function(suffix, _leaf_t, _leaf, _break_c) \ +static void \ +cpuid_read_##suffix(const struct cpuid_parse_entry *e, const struct cpuid_= read_output *output) \ +{ \ + struct _leaf_t *_leaf =3D (struct _leaf_t *)output->regs; \ + \ + for (int i =3D 0; i < e->maxcnt; i++, _leaf++, output->info->nr_entries++= ) { \ + cpuid_read_subleaf(e->leaf, e->subleaf + i, _leaf); \ + if (_break_c) \ + break; \ + } \ +} + /* * Default CPUID read function - * Satisfies the requirements stated at 'struct cpuid_parse_entry'->read(). */ -static void -cpuid_read_generic(const struct cpuid_parse_entry *e, const struct cpuid_r= ead_output *output) -{ - struct cpuid_regs *regs =3D output->regs; - - for (int i =3D 0; i < e->maxcnt; i++, regs++, output->info->nr_entries++) - cpuid_read_subleaf(e->leaf, e->subleaf + i, regs); -} +define_cpuid_read_function(generic, cpuid_regs, ignored, false); =20 static void cpuid_read_0x2(const struct cpuid_parse_entry *e, const struct cpuid_read_= output *output) @@ -83,6 +99,12 @@ cpuid_read_0x2(const struct cpuid_parse_entry *e, const = struct cpuid_read_output output->info->nr_entries =3D 1; } =20 +/* + * Shared read function for Intel CPUID(0x4) and AMD CPUID(0x8000001d), as= both have + * the same subleaf enumeration logic and register output format. + */ +define_cpuid_read_function(deterministic_cache, leaf_0x4_n, l, l->cache_ty= pe =3D=3D 0); + /* * Define an extended range CPUID read function * diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 1de239370652..25ca9b19e8cf 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -145,11 +145,13 @@ struct cpuid_parse_entry { #define CPUID_COMMON_ENTRIES \ /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY ( 0x2, 0, 0x2 ), \ + CPUID_PARSE_ENTRY_N ( 0x4, deterministic_cache ), \ CPUID_PARSE_ENTRY ( 0x16, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ + CPUID_PARSE_ENTRY_N ( 0x8000001d, deterministic_cache ), \ CPUID_PARSE_ENTRY ( 0x80860000, 0, 0x80860000 ), \ CPUID_PARSE_ENTRY ( 0x80860001, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80860002, 0, generic ), \ @@ -192,7 +194,9 @@ struct cpuid_vendor_entry { #define CPUID_VENDOR_ENTRIES \ /* Leaf Vendor list */ \ CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ + CPUID_VENDOR_ENTRY(0x4, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ + CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ CPUID_VENDOR_ENTRY(0x80860000, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860001, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860002, X86_VENDOR_TRANSMETA), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82A62361668 for ; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 37/90] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Date: Fri, 27 Mar 2026 03:15:51 +0100 Message-ID: <20260327021645.555257-38-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the CPUID(0x4) cache topology code for using the parsed CPUID API instead of invoking direct CPUID queries. Since the CPUID API requires a 'struct cpuinfo_x86' reference, trickle it from 's populate_cache_leaves() x86 implementation down to fill_cpuid4_info() and its Intel-specific CPUID(0x4) code. No functional change intended. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/aBnEBbDATdE2LTGU@gmail.com --- arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index d933d58a5a61..07f7e7b667ed 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,7 +252,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpui= d4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -264,13 +264,13 @@ static int intel_fill_cpuid4_info(int index, struct _= cpuid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) { u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? amd_fill_cpuid4_info(index, id4) : - intel_fill_cpuid4_info(index, id4); + intel_fill_cpuid4_info(c, index, id4); } =20 static int find_num_cache_leaves(struct cpuinfo_x86 *c) @@ -443,7 +443,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) struct _cpuid4_info id4 =3D {}; int ret; =20 - ret =3D intel_fill_cpuid4_info(i, &id4); + ret =3D intel_fill_cpuid4_info(c, i, &id4); if (ret < 0) continue; =20 @@ -612,17 +612,17 @@ int populate_cache_leaves(unsigned int cpu) struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci =3D this_cpu_ci->info_list; u8 cpu_vendor =3D boot_cpu_data.x86_vendor; - u32 apicid =3D cpu_data(cpu).topo.apicid; + struct cpuinfo_x86 *c =3D &cpu_data(cpu); struct amd_northbridge *nb =3D NULL; struct _cpuid4_info id4 =3D {}; int idx, ret; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { - ret =3D fill_cpuid4_info(idx, &id4); + ret =3D fill_cpuid4_info(c, idx, &id4); if (ret) return ret; =20 - id4.id =3D get_cache_id(apicid, &id4); + id4.id =3D get_cache_id(c->topo.apicid, &id4); =20 if (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_HYG= ON) nb =3D amd_init_l3_cache(idx); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63A35346797 for ; Fri, 27 Mar 2026 02:19:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577979; cv=none; b=E6G40gLdqQWabqcu3YauKQu47YKKFOq0IlFvo6EyImgyzrveOXHsn3TzSNgG6djICCy54tNX66LYVHto73fdvex4ogPgSyfTX0FlHKUbZ02rEq4eb9+6LIQhW0Ltom4tJf2UZqS0npNK4zo4Fr2QXlxEHPt3LstoLv1MaRxD98g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577979; c=relaxed/simple; bh=6qEaPYZTfFbGb3RiG0+fR6pFDfa/qxF7o8KFGoPGAgo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oGkO2c1hEjJ5Sv1LlOg6ntmzRYHKrkiHIhrFcv1dOnuwwwDnOxpZxxWvnMeZYz+H3PzMmZn77/4edoVCc/AUSDL+iZDMcTv/1HKZZDDmmG0eUKNnGriz6SnhQXCzDOou3AXJl5OZaF5fJkHFbvzT4pyOE1NhoI56JDgkbKQWF6I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CRjYU7qI; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uMXPLQOk; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CRjYU7qI"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uMXPLQOk" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=84dJ5ZsqsImkHCTBhgFQOb5wNlKJl20ElzbvXguKl00=; b=CRjYU7qIqaxpekBbItuS/1Q9n77jHEexHyWioAF3wl+qiRTjiUC3rh6QXVCU42FezAN/34 Oa+ml96jRbe9Nw/aqkY1mP6+nkbHIOY9zKhUO0vOEPeyT4xtl+AGFMRJvXFnQxYadgJIvx IkDMNja6QE/tBDiKxA1sJaNhX/xsl/ngxlcCuCnBLxNgpFKcu6rn6CuLUySZ5Ylg+BNrWQ PkTmFGE9Iw2cTExtsCct7udoe+Y8Noez+u5NexpKyi/lLUP3xA3pm1ICIuY0WEHFOGU8TT +Tvck7jk6iNx1wPrjaUiNsJdrLjBl5vlYHW4jM8onpY5NX0W9Lzy3n19uqStcA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=84dJ5ZsqsImkHCTBhgFQOb5wNlKJl20ElzbvXguKl00=; b=uMXPLQOk2QqpI72AU1DzJBx6YfWtAFpMaRUKGXG7iaAOu/bq8m+tgVOmHf4dR6wuTBFCsi /UIWJzta1O/643Ag== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 38/90] x86/cacheinfo: Use parsed CPUID(0x4) Date: Fri, 27 Mar 2026 03:15:52 +0100 Message-ID: <20260327021645.555257-39-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Intel cacheinfo, use parsed CPUID(0x4) instead of a direct CPUID query. Use the CPUID API cpuid_subleaf_count(c, 0x4) to determine the number of CPUID(0x4) cache subleaves instead of calling find_num_cache_leaves(). The latter function internally invokes direct CPUID(0x4) queries. Since find_num_cache_leaves() is no longer needed for Intel code paths, make its name and implementation AMD-specific. Adjust the AMD code paths accordingly. At intel_cacheinfo_0x4(), remove the max CPUID level check since cpuid_subleaf_count(c, 0x4) will return zero if CPUID(0x4) is not valid. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 40 ++++++++++++++------------------- 1 file changed, 17 insertions(+), 23 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 07f7e7b667ed..91020f85c000 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,16 +252,17 @@ static int amd_fill_cpuid4_info(int index, struct _cp= uid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; - u32 ignored; + const struct cpuid_regs *regs =3D cpuid_subleaf_n_raw(c, 0x4, index); =20 - cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &ignored); + if (!regs) + return -EIO; =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, + (union _cpuid4_leaf_eax)(regs->eax), + (union _cpuid4_leaf_ebx)(regs->ebx), + (union _cpuid4_leaf_ecx)(regs->ecx)); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -273,17 +274,16 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf intel_fill_cpuid4_info(c, index, id4); } =20 -static int find_num_cache_leaves(struct cpuinfo_x86 *c) +static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) { - unsigned int eax, ebx, ecx, edx, op; union _cpuid4_leaf_eax cache_eax; + unsigned int eax, ebx, ecx, edx; int i =3D -1; =20 - /* Do a CPUID(op) loop to calculate num_cache_leaves */ - op =3D (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_V= ENDOR_HYGON) ? 0x8000001d : 4; + /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ do { ++i; - cpuid_count(op, i, &eax, &ebx, &ecx, &edx); + cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); cache_eax.full =3D eax; } while (cache_eax.split.type !=3D CTYPE_NULL); return i; @@ -328,7 +328,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) * Newer families: LLC ID is calculated from the number * of threads sharing the L3 cache. */ - u32 llc_index =3D find_num_cache_leaves(c) - 1; + u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; struct _cpuid4_info id4 =3D {}; =20 if (!amd_fill_cpuid4_info(llc_index, &id4)) @@ -353,7 +353,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -362,7 +362,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, @@ -426,15 +426,9 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) unsigned int l2_id =3D BAD_APICID, l3_id =3D BAD_APICID; unsigned int l1d =3D 0, l1i =3D 0, l2 =3D 0, l3 =3D 0; =20 - if (c->cpuid_level < 4) - return false; - - /* - * There should be at least one leaf. A non-zero value means - * that the number of leaves has been previously initialized. - */ + /* Non-zero means that it has been previously initialized */ if (!ci->num_leaves) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x4); =20 if (!ci->num_leaves) return false; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3814C3624CF for ; Fri, 27 Mar 2026 02:19:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577983; cv=none; b=gKjs5/qh81EHcXzWUkYXvWNt8lVvfqNTgc32meJk4varHiXN4Mp9yEIPRa7ZxvBvIN09faQiIuTzJ1Gk9Nb788XfZEcn0Au8f1h3WRal8+S0VFMcr3cgBdGCfbXR1UEsK+RyfOemyIgTScuCGYYigf4UuSVQEOo6FzJjReVVDwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577983; c=relaxed/simple; bh=+W8t9MbaCWeef3NcK6ju2iq4pIm/CcMbPvUthPR09K8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pbGGT4hC/N/51/Z/i7PdN9vod6qpwmAgkdPi3uT59MhZkLdE9Ba5JI/kCAHpiYzsaiutJKboZnm7tq9qGWaLRiUMD8urWyX6lA1xrkZRHk+JRu5FjkpPBjwybsgbnIEqihMvEtT87HFfruoWLn2qNQ0O4e65unVjt5lReW+MCtA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Xjx2tWop; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XKSdKuIg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Xjx2tWop"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XKSdKuIg" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AmGDXH4djNB2zb29lHnG3L22XKvURrEeZsQJFjV31DA=; b=Xjx2tWopI8WzLL2dlxGbUMqWg/nUVGfZ1maadnynjy4EIHPthWGIgyYHaEOhYS6z2dyUOA dKd8IAERl7ugirask1XxZBSivuMso1xXDH3U4b//j6QDT8odSgw4gVbuBHyoRqSB959mWi vBD4+BXvTX/Gs7pCG2ShSlBaAZSOJkGyp1c97SGGtmhetIlf9ZohAYzZY9LVhnUcOz9P88 mb3k3i65JoZJVs/qe7iaRlRSao9PQabLnUoa8DVhmEB7KvzPDCssW/sjCOjsE4woG5hc/D BmbkLTlwDPGkNKM/fg1goX8Ed+2R4aXtsWMqzXk2rYBZmrvodJEmpWz/SRr23g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AmGDXH4djNB2zb29lHnG3L22XKvURrEeZsQJFjV31DA=; b=XKSdKuIgfdPAQjCoDH/1ISdnpbcilacoAKSuOGrgwyZB7VKzTOeudA5wbp7bYNKa8Qvp3y /kXRgL3w8L9KBECg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 39/90] x86/cacheinfo: Use parsed CPUID(0x8000001d) Date: Fri, 27 Mar 2026 03:15:53 +0100 Message-ID: <20260327021645.555257-40-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD cacheinfo, use parsed CPUID(0x8000001d) instead of CPUID queries. Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their C99 bitfields, instead of doing ugly bitwise operations on the CPUID output. Trickle down a 'struct cpuinfo_x86' reference to the relevant functions as the CPUID APIs require it. Use the parsed CPUID API cpuid_subleaf_count(c, 0x8000001d) instead of calling amd_find_num_cache_leaves() and its direct CPUID queries. Remove the latter function as it is no longer used. Keep using the 'union _cpuid4_leaf_eax/ebx/ecx' data types as they are required by the AMD CPUID(0x4) emulation code. A follow up commit will replace them with their auto-generated x86-cpuid-db equivalents. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 41 +++++++++++++-------------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 91020f85c000..86a8e1dad935 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -237,16 +237,22 @@ static int cpuid4_info_fill_done(struct _cpuid4_info = *id4, union _cpuid4_leaf_ea return 0; } =20 -static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _= cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; union _cpuid4_leaf_ecx ecx; - u32 ignored; =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) - cpuid_count(0x8000001d, index, &eax.full, &ebx.full, &ecx.full, &ignored= ); - else + if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) { + const struct cpuid_regs *regs =3D cpuid_subleaf_n_raw(c, 0x8000001d, ind= ex); + + if (!regs) + return -EIO; + + eax.full =3D regs->eax; + ebx.full =3D regs->ebx; + ecx.full =3D regs->ecx; + } else legacy_amd_cpuid4(index, &eax, &ebx, &ecx); =20 return cpuid4_info_fill_done(id4, eax, ebx, ecx); @@ -270,25 +276,10 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? - amd_fill_cpuid4_info(index, id4) : + amd_fill_cpuid4_info(c, index, id4) : intel_fill_cpuid4_info(c, index, id4); } =20 -static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) -{ - union _cpuid4_leaf_eax cache_eax; - unsigned int eax, ebx, ecx, edx; - int i =3D -1; - - /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ - do { - ++i; - cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); - cache_eax.full =3D eax; - } while (cache_eax.split.type !=3D CTYPE_NULL); - return i; -} - /* * The max shared threads number comes from CPUID(0x4) EAX[25-14] with inp= ut * ECX as cache index. Then right shift apicid by the number's order to get @@ -328,10 +319,10 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c,= u16 die_id) * Newer families: LLC ID is calculated from the number * of threads sharing the L3 cache. */ - u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; + u32 llc_index =3D cpuid_subleaf_count(c, 0x8000001d) - 1; struct _cpuid4_info id4 =3D {}; =20 - if (!amd_fill_cpuid4_info(llc_index, &id4)) + if (!amd_fill_cpuid4_info(c, llc_index, &id4)) c->topo.llc_id =3D get_cache_id(c->topo.apicid, &id4); } } @@ -353,7 +344,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D amd_find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -362,7 +353,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D amd_find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 425F8330324 for ; Fri, 27 Mar 2026 02:19:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577989; cv=none; b=m0pVWh5v7XkKUL20RWXY9rQuXJEKp0HJJSAvzLCj8kYANS3UDxnptgoLXJO1eWDbygfG8VJiRhRS4IHsKMyM9RBxyMd7zU9Lw2ZOWj5viPHhHW0nGvzdXWEPk+jjOs4aCZtvwPm459hvUrIr2TkVJRkYGEvjr5V3T5fpuCTQ3Xo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577989; c=relaxed/simple; bh=Mg0312Sjj5B5aPUD/dSROadTJqH74lwwxx90Wx2mCfY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cQI6H62okLJ1cW0wAWNj/jIU58Uo1kt6D+8F9ujgoylQCfComaNu0MhiBFvQjPHuAl04q65SlHXgGWWjjM2Z2IYACChy2e0ctVRz5kIS0IV5NrONxMHuP+hXiCReak65oOetgZvCI8aKWUzrCTobdVlmXCzXIcIZd6Ce+XbajSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=JWzY/xgL; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=77/Uhcdw; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="JWzY/xgL"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="77/Uhcdw" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 40/90] x86/cpuid: Parse CPUID(0x80000005), CPUID(0x80000006), CPUID(0x80000008) Date: Fri, 27 Mar 2026 03:15:54 +0100 Message-ID: <20260327021645.555257-41-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse AMD cacheinfo CPUID(0x80000005) and CPUID(0x80000006). Also parse the CPU capacity parameters at CPUID(0x80000008). This allows converting their call sites to parsed CPUID access instead of issuing CPUID queries. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 3 +++ arch/x86/kernel/cpu/cpuid_parser.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index f77659303569..f50e54bfb514 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -217,6 +217,9 @@ struct cpuid_leaves { CPUID_LEAF ( 0x80000002, 0 ); CPUID_LEAF ( 0x80000003, 0 ); CPUID_LEAF ( 0x80000004, 0 ); + CPUID_LEAF ( 0x80000005, 0 ); + CPUID_LEAF ( 0x80000006, 0 ); + CPUID_LEAF ( 0x80000008, 0 ); CPUID_LEAF_N ( 0x8000001d, 8 ); CPUID_LEAF ( 0x80860000, 0 ); CPUID_LEAF ( 0x80860001, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 25ca9b19e8cf..ab391de03a92 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -151,6 +151,9 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000005, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000006, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000008, 0, generic ), \ CPUID_PARSE_ENTRY_N ( 0x8000001d, deterministic_cache ), \ CPUID_PARSE_ENTRY ( 0x80860000, 0, 0x80860000 ), \ CPUID_PARSE_ENTRY ( 0x80860001, 0, generic ), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 653023644A2 for ; Fri, 27 Mar 2026 02:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577992; cv=none; b=NSxq561iWaJsEUsifqVkPP1lzFMLRrrbGtVsUOn2k8V/BbMwr1oxBUrGzf66GDXw+wxm734DwLRlFwhEmFlkryHCJ2wruvJE5rXTktv7M0gae14+Y/k6Z37RRyq2/UEcSNsVd7K+dgKnb2GGLfoQ9UnrrGnwrNvSCfw855qTG4E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774577992; c=relaxed/simple; bh=1B5FsMesNAjF3SQIwWa7/TgWMtxwmmAnuAWxOyxEcO4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iaOMcpl9QQWTiKJWR1OhfERcTUc6oGuHEOR2RK7KEfO/UQ7eQT7lhWAOx3rWRF6qNdX1z5MBWnWUGY8GdYJcoXIPztxm2qbZBZWd7hmry5NXlDzt+B8XyyvctGBX3SRb4V4RbchrDIqAFNNIge0RtBR4z0Ns1ulGne9pb6+SjxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DQD+dnam; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=a+I2c3Fg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DQD+dnam"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="a+I2c3Fg" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 41/90] x86/cacheinfo: Use auto-generated data types Date: Fri, 27 Mar 2026 03:15:55 +0100 Message-ID: <20260327021645.555257-42-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(0x4) emulation logic, use the auto-generated data type: struct leaf_0x4_n instead of the manually-defined: union _cpuid4_leaf_{eax,ebx,ecx} ones. Remove such unions entirely as they are no longer used. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db --- arch/x86/kernel/cpu/cacheinfo.c | 127 +++++++++++--------------------- 1 file changed, 42 insertions(+), 85 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 86a8e1dad935..209a0c708213 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -41,39 +41,8 @@ enum _cache_type { CTYPE_UNIFIED =3D 3 }; =20 -union _cpuid4_leaf_eax { - struct { - enum _cache_type type :5; - unsigned int level :3; - unsigned int is_self_initializing :1; - unsigned int is_fully_associative :1; - unsigned int reserved :4; - unsigned int num_threads_sharing :12; - unsigned int num_cores_on_die :6; - } split; - u32 full; -}; - -union _cpuid4_leaf_ebx { - struct { - unsigned int coherency_line_size :12; - unsigned int physical_line_partition :10; - unsigned int ways_of_associativity :10; - } split; - u32 full; -}; - -union _cpuid4_leaf_ecx { - struct { - unsigned int number_of_sets :32; - } split; - u32 full; -}; - struct _cpuid4_info { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + struct leaf_0x4_n regs; unsigned int id; unsigned long size; }; @@ -148,17 +117,14 @@ static const unsigned short assocs[] =3D { static const unsigned char levels[] =3D { 1, 1, 2, 3 }; static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 -static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax, - union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx) +static void legacy_amd_cpuid4(int index, struct leaf_0x4_n *regs) { unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; union l1_cache l1i, l1d, *l1; union l2_cache l2; union l3_cache l3; =20 - eax->full =3D 0; - ebx->full =3D 0; - ecx->full =3D 0; + *regs =3D (struct leaf_0x4_n){ }; =20 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); @@ -204,71 +170,62 @@ static void legacy_amd_cpuid4(int index, union _cpuid= 4_leaf_eax *eax, return; } =20 - eax->split.is_self_initializing =3D 1; - eax->split.type =3D types[index]; - eax->split.level =3D levels[index]; - eax->split.num_threads_sharing =3D 0; - eax->split.num_cores_on_die =3D topology_num_cores_per_package(); + regs->cache_self_init =3D 1; + regs->cache_type =3D types[index]; + regs->cache_level =3D levels[index]; + regs->num_threads_sharing =3D 0; + regs->num_cores_on_die =3D topology_num_cores_per_package(); =20 if (assoc =3D=3D AMD_CPUID4_FULLY_ASSOCIATIVE) - eax->split.is_fully_associative =3D 1; + regs->fully_associative =3D 1; =20 - ebx->split.coherency_line_size =3D line_size - 1; - ebx->split.ways_of_associativity =3D assoc - 1; - ebx->split.physical_line_partition =3D lines_per_tag - 1; - ecx->split.number_of_sets =3D (size_in_kb * 1024) / line_size / - (ebx->split.ways_of_associativity + 1) - 1; + regs->cache_linesize =3D line_size - 1; + regs->cache_nways =3D assoc - 1; + regs->cache_npartitions =3D lines_per_tag - 1; + regs->cache_nsets =3D (size_in_kb * 1024) / line_size / + (regs->cache_nways + 1) - 1; } =20 -static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_l= eaf_eax eax, - union _cpuid4_leaf_ebx ebx, union _cpuid4_leaf_ecx ecx) +static int cpuid4_info_fill_done(struct _cpuid4_info *id4, const struct le= af_0x4_n *regs) { - if (eax.split.type =3D=3D CTYPE_NULL) + if (regs->cache_type =3D=3D CTYPE_NULL) return -EIO; =20 - id4->eax =3D eax; - id4->ebx =3D ebx; - id4->ecx =3D ecx; - id4->size =3D (ecx.split.number_of_sets + 1) * - (ebx.split.coherency_line_size + 1) * - (ebx.split.physical_line_partition + 1) * - (ebx.split.ways_of_associativity + 1); + id4->regs =3D *regs; + id4->size =3D (regs->cache_nsets + 1) * + (regs->cache_linesize + 1) * + (regs->cache_npartitions + 1) * + (regs->cache_nways + 1); =20 return 0; } =20 static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _= cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + struct leaf_0x4_n l_0x4_regs; =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) { - const struct cpuid_regs *regs =3D cpuid_subleaf_n_raw(c, 0x8000001d, ind= ex); + const struct leaf_0x8000001d_n *regs =3D cpuid_subleaf_n(c, 0x8000001d, = index); =20 if (!regs) return -EIO; =20 - eax.full =3D regs->eax; - ebx.full =3D regs->ebx; - ecx.full =3D regs->ecx; + /* CPUID(0x8000001d) and CPUID(0x4) have the same bitfields */ + l_0x4_regs =3D *(struct leaf_0x4_n *)regs; } else - legacy_amd_cpuid4(index, &eax, &ebx, &ecx); + legacy_amd_cpuid4(index, &l_0x4_regs); =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, &l_0x4_regs); } =20 static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - const struct cpuid_regs *regs =3D cpuid_subleaf_n_raw(c, 0x4, index); + const struct leaf_0x4_n *regs =3D cpuid_subleaf_n(c, 0x4, index); =20 if (!regs) return -EIO; =20 - return cpuid4_info_fill_done(id4, - (union _cpuid4_leaf_eax)(regs->eax), - (union _cpuid4_leaf_ebx)(regs->ebx), - (union _cpuid4_leaf_ecx)(regs->ecx)); + return cpuid4_info_fill_done(id4, regs); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -290,7 +247,7 @@ static unsigned int get_cache_id(u32 apicid, const stru= ct _cpuid4_info *id4) unsigned long num_threads_sharing; int index_msb; =20 - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); =20 return apicid >> index_msb; @@ -406,7 +363,7 @@ static unsigned int calc_cache_topo_id(struct cpuinfo_x= 86 *c, const struct _cpui unsigned int num_threads_sharing; int index_msb; =20 - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); return c->topo.apicid & ~((1 << index_msb) - 1); } @@ -432,11 +389,11 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) if (ret < 0) continue; =20 - switch (id4.eax.split.level) { + switch (id4.regs.cache_level) { case 1: - if (id4.eax.split.type =3D=3D CTYPE_DATA) + if (id4.regs.cache_type =3D=3D CTYPE_DATA) l1d =3D id4.size / 1024; - else if (id4.eax.split.type =3D=3D CTYPE_INST) + else if (id4.regs.cache_type =3D=3D CTYPE_INST) l1i =3D id4.size / 1024; break; case 2: @@ -497,7 +454,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { unsigned int apicid, nshared, first, last; =20 - nshared =3D id4->eax.split.num_threads_sharing + 1; + nshared =3D id4->regs.num_threads_sharing + 1; apicid =3D cpu_data(cpu).topo.apicid; first =3D apicid - (apicid % nshared); last =3D first + nshared - 1; @@ -544,7 +501,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int = index, } =20 ci =3D this_cpu_ci->info_list + index; - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; =20 cpumask_set_cpu(cpu, &ci->shared_cpu_map); if (num_threads_sharing =3D=3D 1) @@ -571,13 +528,13 @@ static void ci_info_init(struct cacheinfo *ci, const = struct _cpuid4_info *id4, { ci->id =3D id4->id; ci->attributes =3D CACHE_ID; - ci->level =3D id4->eax.split.level; - ci->type =3D cache_type_map[id4->eax.split.type]; - ci->coherency_line_size =3D id4->ebx.split.coherency_line_size + 1; - ci->ways_of_associativity =3D id4->ebx.split.ways_of_associativity + 1; + ci->level =3D id4->regs.cache_level; + ci->type =3D cache_type_map[id4->regs.cache_type]; + ci->coherency_line_size =3D id4->regs.cache_linesize + 1; + ci->ways_of_associativity =3D id4->regs.cache_nways + 1; ci->size =3D id4->size; - ci->number_of_sets =3D id4->ecx.split.number_of_sets + 1; - ci->physical_line_partition =3D id4->ebx.split.physical_line_partition + = 1; + ci->number_of_sets =3D id4->regs.cache_nsets + 1; + ci->physical_line_partition =3D id4->regs.cache_npartitions + 1; ci->priv =3D nb; } =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 776EB3644A3 for ; Fri, 27 Mar 2026 02:19:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 42/90] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:15:56 +0100 Message-ID: <20260327021645.555257-43-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD CPUID(0x4)-emulation logic, use parsed CPUID(0x80000005) and CPUID(0x80000006) instead of invoking CPUID queries. Beside the CPUID parser centralization benefits, this allows using the auto generated x86-cpuid-db data types, and their C99 bitfields, instead of doing ugly bitwise operations or defining custom call site types. Remove the 'union l[123]_cache' data types as they are no longer needed. Replace the expression: ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; with: ci->num_leaves =3D cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3; since per AMD manuals, an L3 associativity level of zero implies the absence of a CPU L3 cache. While at it, separate the "Fallback AMD CPUID(0x4) emulation" comment from the "AMD_L2_L3_INVALID_ASSOC" one. The former is as a code section header. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 103 +++++++++++++------------------- 1 file changed, 40 insertions(+), 63 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 209a0c708213..7dab0d7152cc 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -56,47 +56,17 @@ static const enum cache_type cache_type_map[] =3D { }; =20 /* - * Fallback AMD CPUID(0x4) emulation + * Fallback AMD CPUID(0x4) emulation: * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) - * + */ + +/* * @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache sho= uld * be determined from CPUID(0x8000001d) instead of CPUID(0x80000006). */ - #define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff #define AMD_L2_L3_INVALID_ASSOC 0x9 =20 -union l1_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :8; - unsigned assoc :8; - unsigned size_in_kb :8; - }; - unsigned int val; -}; - -union l2_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :4; - unsigned assoc :4; - unsigned size_in_kb :16; - }; - unsigned int val; -}; - -union l3_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :4; - unsigned assoc :4; - unsigned res :2; - unsigned size_encoded :14; - }; - unsigned int val; -}; - /* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, @@ -117,50 +87,52 @@ static const unsigned short assocs[] =3D { static const unsigned char levels[] =3D { 1, 1, 2, 3 }; static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 -static void legacy_amd_cpuid4(int index, struct leaf_0x4_n *regs) +static void legacy_amd_cpuid4(struct cpuinfo_x86 *c, int index, struct lea= f_0x4_n *regs) { - unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; - union l1_cache l1i, l1d, *l1; - union l2_cache l2; - union l3_cache l3; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); + const struct cpuid_regs *el5_raw =3D cpuid_leaf_raw(c, 0x80000005); + unsigned int line_size, lines_per_tag, assoc, size_in_kb; =20 *regs =3D (struct leaf_0x4_n){ }; =20 - cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); - cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); - - l1 =3D &l1d; switch (index) { - case 1: - l1 =3D &l1i; - fallthrough; case 0: - if (!l1->val) + if (!el5 || !el5_raw->ecx) return; =20 - assoc =3D (l1->assoc =3D=3D 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->= assoc; - line_size =3D l1->line_size; - lines_per_tag =3D l1->lines_per_tag; - size_in_kb =3D l1->size_in_kb; + assoc =3D el5->l1_dcache_assoc; + line_size =3D el5->l1_dcache_line_size; + lines_per_tag =3D el5->l1_dcache_nlines; + size_in_kb =3D el5->l1_dcache_size_kb; + break; + case 1: + if (!el5 || !el5_raw->edx) + return; + + assoc =3D el5->l1_icache_assoc; + line_size =3D el5->l1_icache_line_size; + lines_per_tag =3D el5->l1_icache_nlines; + size_in_kb =3D el5->l1_icache_size_kb; break; case 2: - if (!l2.assoc || l2.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) + if (!el6 || !el6->l2_assoc || el6->l2_assoc =3D=3D AMD_L2_L3_INVALID_ASS= OC) return; =20 /* Use x86_cache_size as it might have K7 errata fixes */ - assoc =3D assocs[l2.assoc]; - line_size =3D l2.line_size; - lines_per_tag =3D l2.lines_per_tag; + assoc =3D assocs[el6->l2_assoc]; + line_size =3D el6->l2_line_size; + lines_per_tag =3D el6->l2_nlines; size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); break; case 3: - if (!l3.assoc || l3.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) + if (!el6 || !el6->l3_assoc || el6->l3_assoc =3D=3D AMD_L2_L3_INVALID_ASS= OC) return; =20 - assoc =3D assocs[l3.assoc]; - line_size =3D l3.line_size; - lines_per_tag =3D l3.lines_per_tag; - size_in_kb =3D l3.size_encoded * 512; + assoc =3D assocs[el6->l3_assoc]; + line_size =3D el6->l3_line_size; + lines_per_tag =3D el6->l3_nlines; + size_in_kb =3D el6->l3_size_range * 512; if (boot_cpu_has(X86_FEATURE_AMD_DCM)) { size_in_kb =3D size_in_kb >> 1; assoc =3D assoc >> 1; @@ -170,6 +142,10 @@ static void legacy_amd_cpuid4(int index, struct leaf_0= x4_n *regs) return; } =20 + /* For L1d and L1i caches, 0xff is the full associativity marker */ + if ((index =3D=3D 0 || index =3D=3D 1) && assoc =3D=3D 0xff) + assoc =3D AMD_CPUID4_FULLY_ASSOCIATIVE; + regs->cache_self_init =3D 1; regs->cache_type =3D types[index]; regs->cache_level =3D levels[index]; @@ -213,7 +189,7 @@ static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, = int index, struct _cpuid4 /* CPUID(0x8000001d) and CPUID(0x4) have the same bitfields */ l_0x4_regs =3D *(struct leaf_0x4_n *)regs; } else - legacy_amd_cpuid4(index, &l_0x4_regs); + legacy_amd_cpuid4(c, index, &l_0x4_regs); =20 return cpuid4_info_fill_done(id4, &l_0x4_regs); } @@ -298,12 +274,13 @@ void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *= c) =20 void init_amd_cacheinfo(struct cpuinfo_x86 *c) { + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); - else if (c->extended_cpuid_level >=3D 0x80000006) - ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; + else if (el6) + ci->num_leaves =3D (el6->l3_assoc) ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8674E34AB1F for ; Fri, 27 Mar 2026 02:20:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578003; cv=none; b=JZ4LpSeEU15XzX1hMJXEr8B0FCbMk6MfmwFpyt0ZynT2hQEFD04k73BH9WBD+JumyZ1f/HzSkK51rrCd8JZ351q9uQ9HAM2yP/vD6xK1Nw0auaV/DK8bD4bQUcM/7/qiEunp1YJp3589uqMNzbCzOJcRij8AyG+jTxooxC7b6IY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578003; c=relaxed/simple; bh=pIyLvWuUhQZx6icT2LjbX5/aGd3TSzV/SiN9yDHQu7Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KWQdaqvCYNyTh426MiqnfuE/0MxHD2LNejv/OAFrWr/emJ7ijBCe5NRQ3W+JQFfNl+CpyHHB9RrDfqjnriXNxyccVOqtrmZIkJAc0qrQMe2+4I5jowsRQFUfiAlMN8m/g2MyekIPCGnL2VRC2xwO016BlCYFWsAyiBYD0wNZhEU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0gbkCmzH; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QIe3PFxS; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0gbkCmzH"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QIe3PFxS" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774577996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZonDWpy1+jQJ9O62WLSvhrExZUpqVbLHiHBAaECowEM=; b=0gbkCmzHQNGAXAgaA31eliMtYRPXAyLL+UQvD0p+3xcPs9NjFoy2OZOOyD/EDF1sCK6/q/ 9+4kCyiBiLA0Oqns48WjtwK8Ec7SVlyNJMX53SMzN+WvHzeSOJQEp0XSxjSKHd2RWi8Isq tICd5LSllKFk8VgRA0MQ9+yf1oodLk8/2L4p7i+QwA+6weFRKRtpLHQjMTYsaZlpU3Ees2 86AVp3k24OnJkKN0AfNcVzKgZFKwsZ14T/UmWAIW1qA+7MnHSATWK/se9MP/TSmbI2b8kI F+OP+CljayBiLfGjexmPTS8QxBRBH8PVfNc6K8+GZtLIEM6jKCO/H+NwuFFXxg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774577996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZonDWpy1+jQJ9O62WLSvhrExZUpqVbLHiHBAaECowEM=; b=QIe3PFxSidIUdj7AoLnk2k5/s9W6UYnjdKTi5D1LGDmMMj1S5LcoY9dsWmiCeU2Ml4PIKc xs6jE3QOh3lYyGAQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 43/90] x86/cacheinfo: Use parsed CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:15:57 +0100 Message-ID: <20260327021645.555257-44-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD cacheinfo, use parsed CPUID(0x80000006) instead of issuing a direct CPUID query. Beside the CPUID parser centralization benefits, this allows using the auto-generated x86-cpuid-db data types, and their C99 bitfields, instead of doing ugly bitwise operations on CPUID output. For enumerating L3 cache availability, check if CPUID(0x80000006).EDX l3_assoc output is not zero. Per AMD manuals, an L3 associativity of zero implies the absence of a CPU L3 cache. Since cpuid_amd_hygon_has_l3_cache() is now using the CPUID parser APIs, move its definition under the section: "Convenience leaf-specific functions (using parsed CPUID)." Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 20 +++++++++++--------- arch/x86/kernel/amd_nb.c | 3 ++- arch/x86/kernel/cpu/cacheinfo.c | 6 +++--- 3 files changed, 16 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index f4bdfe3c9325..611ee8596115 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -212,15 +212,6 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) return 0; } =20 -/* - * CPUID(0x80000006) parsing: - */ - -static inline bool cpuid_amd_hygon_has_l3_cache(void) -{ - return cpuid_edx(0x80000006); -} - /* * 'struct cpuid_leaves' accessors (without sanity checks): * @@ -502,6 +493,17 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) _ptr < &((const union leaf_0x2_regs *)(_regs))->desc[16] && (_desc = =3D &cpuid_0x2_table[*_ptr]);\ _ptr++) =20 +/* + * CPUID(0x80000006) + */ + +static inline bool cpuid_amd_hygon_has_l3_cache(struct cpuinfo_x86 *c) +{ + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); + + return el6 && el6->l3_assoc; +} + /* * CPUID parser exported APIs: */ diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 5d364540673d..06ebbd564945 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -16,6 +16,7 @@ =20 #include #include +#include =20 static u32 *flush_words; =20 @@ -93,7 +94,7 @@ static int amd_cache_northbridges(void) if (amd_gart_present()) amd_northbridges.flags |=3D AMD_NB_GART; =20 - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(&boot_cpu_data)) return 0; =20 /* diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 7dab0d7152cc..3e40bcca1c3b 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -235,7 +235,7 @@ static unsigned int get_cache_id(u32 apicid, const stru= ct _cpuid4_info *id4) =20 void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id) { - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return; =20 if (c->x86 < 0x17) { @@ -262,7 +262,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) =20 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c) { - if (!cpuid_amd_hygon_has_l3_cache()) + if (!cpuid_amd_hygon_has_l3_cache(c)) return; =20 /* @@ -280,7 +280,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) if (boot_cpu_has(X86_FEATURE_TOPOEXT)) ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); else if (el6) - ci->num_leaves =3D (el6->l3_assoc) ? 4 : 3; + ci->num_leaves =3D cpuid_amd_hygon_has_l3_cache(c) ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03F3364937 for ; Fri, 27 Mar 2026 02:20:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578006; cv=none; b=FuP6h3/PgdVFzBZXOC9QS5kcY1riVgsNqk7XZ1KZS58pSis7DsD1dcUcJMih2HjywRrZpDQ+oN88r/TSwRISEuUFZ4bEe4VmCXMaa2w4Frzw4YpK8640ec08DrAUzroL8SLi/14Rnk99FgG0aJacdgbXOj1H9Hw+WCOqduPFwRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578006; c=relaxed/simple; bh=2FKqaDXQDLLvlw9eq3jKYIWj3nIdnlUlczEncP/7Kz8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qbeFu5kIgWDWgbnJ4tJd3u0FEHDWtr1Cmep7M1RE4sh9fCvNk09h5YvC30CTj6VYRgDB6r7Kl+qFqXFwHsCXhYGp0j9+3QIUHSiXNfiN5H7WMevm8Kyty8/e5xjhbqkBNrzKYDlmYa/ES0WXCgTJZT3Y22TWJ/VfK02q6Ol3JmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HieBFBjY; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Yw0ehc1y; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HieBFBjY"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Yw0ehc1y" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HFP83YWrjEVTjjg6IOQ79qfq8QvCeTy80hUMbnk+FwM=; b=HieBFBjYtBuPEvM3vj+LV0/BnXq9PdoKDIFmAinncWPgOaZ0i6iQJdEAMKkDKnb5CeYOe8 zX2wZm8UnE0H//YqS+9ROtmDFPUl1fRgzpM//Gx26P9xhHK7VjXxjuTZpq6Ntu/dW9o1pN gj9V+Jh6NvCTrADflCgTjrNJU8U6OVfF1BRYbbo3w/Z+NVN4T4+vt9a2sPnbM5gsfCwmGm ld3WL/toCViHSX7XL2bl5Oxt6d46bwHgkqKARRE0sDoAyeX0XLzq9rzRxj+yhHTJcCUdt+ FhGkYZYxDnA1bxronJYr+Gg6o6Zzm8q1HdOezPUtWXbJ7HM8m7j+pPUQd6uGsw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HFP83YWrjEVTjjg6IOQ79qfq8QvCeTy80hUMbnk+FwM=; b=Yw0ehc1y7JwcgET0pQ18PqWaIeFaGGhq/hRoo6rkbgpcsRJ6Sz3ni80LG971ZSY6uwdzR/ 73K8R2JpmdVz2zBw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 44/90] x86/cpu: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:15:58 +0100 Message-ID: <20260327021645.555257-45-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000005) and CPUID(0x80000006) instead of issuing CPUID queries and doing ugly bitwise operations. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f7372833dd50..5fa5463686ac 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -857,27 +857,26 @@ static void get_model_name(struct cpuinfo_x86 *c) =20 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) { - unsigned int n, dummy, ebx, ecx, edx, l2size; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); + unsigned int l2size; =20 - n =3D c->extended_cpuid_level; - - if (n >=3D 0x80000005) { - cpuid(0x80000005, &dummy, &ebx, &ecx, &edx); - c->x86_cache_size =3D (ecx>>24) + (edx>>24); + if (el5) { + c->x86_cache_size =3D el5->l1_dcache_size_kb + el5->l1_icache_size_kb; #ifdef CONFIG_X86_64 /* On K8 L1 TLB is inclusive, so don't count it */ c->x86_tlbsize =3D 0; #endif } =20 - if (n < 0x80000006) /* Some chips just has a large L1. */ + /* Some chips only have a large L1 */ + if (!el6) return; =20 - cpuid(0x80000006, &dummy, &ebx, &ecx, &edx); - l2size =3D ecx >> 16; + l2size =3D el6->l2_size_kb; =20 #ifdef CONFIG_X86_64 - c->x86_tlbsize +=3D ((ebx >> 16) & 0xfff) + (ebx & 0xfff); + c->x86_tlbsize +=3D el6->l2_dtlb_4k_nentries + el6->l2_itlb_4k_nentries; #else /* do processor-specific cache resizing */ if (this_cpu->legacy_cache_size) @@ -887,8 +886,9 @@ void cpu_detect_cache_sizes(struct cpuinfo_x86 *c) if (cachesize_override !=3D -1) l2size =3D cachesize_override; =20 + /* Again, no L2 cache is possible */ if (l2size =3D=3D 0) - return; /* Again, no L2 cache is possible */ + return; #endif =20 c->x86_cache_size =3D l2size; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDAEE366059 for ; Fri, 27 Mar 2026 02:20:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578009; cv=none; b=VQpTOD0QfapY4qgADVjwkBJp6IbGf0Wn9V4Z/mo3+3N6QJuRnNlRS7YVR9mnKKXYm3Dt2MrXe1HBsg/wbqfYoGDcxfsS22PLysf260Tmr9BRR4E5LAzjbdh1s7TDqnEnEC7h0LQdJl9wc5IrDYso2LKYvjpWCpCAFKBMFn9SO20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578009; c=relaxed/simple; bh=KbDRQZgON9sRRjUDBEU4VQwvvaWrMcTapPPTDSvsixM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iCDo++W1FmxrCIayNElzEB5qXkIawuxpJ7lr+1Hma//2AtsqRdEEdntoheQl2go9hm43kVzZsWxgAJjmsV0GMWA+q6gAjRhwwHvtjk23F8iKR/C4q08XprFGul/jQMpJa9Sa5av20oJ0HkOY6b70GiKkxxhMTx9TTDnTkFNGIoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3FVqVlaz; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=S1ALP5G+; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3FVqVlaz"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="S1ALP5G+" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578006; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ztgf+bvmZ8chEdMsyRUoulIOp3HtnYuEqxiwj/UIqdo=; b=3FVqVlazUYmGhkcPFd2vODdnkBOS/l4ghy4PXruhqDVAJkrGqGfgvZW5FgHZbX+BXu+VFG q9JCANERGss/fQYeH6imtlweu7EItyTgf0SHq1WgRsmyQGB+eyh+/vFAtmkQbVgaeQMnZj tb+Q1nVJE4NNpJkZUj+ca4S7XwgsO5bkrpQXLDekQHzyELkEEI796XxqNlFkG5qqO/baJM Hly4pNufSCJaWlpGi6EqICK7Ybqil8V7rfse72sPlUrfMs/I2Xp3Cuh+BYMcv0Gibo1fm1 wKYqi7HzmPfL7HP/08+ZvfBZdklPKz2dST36LuK70B9EnRMWc9VnrkP1pjdHqg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578006; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ztgf+bvmZ8chEdMsyRUoulIOp3HtnYuEqxiwj/UIqdo=; b=S1ALP5G+cIGn1xhwAX7PEb95KCYug7SzukzPGn++X/H89r+4YtTkgfTeYWRfq+THoM8w7I nZtp3E1XfBOzdUDw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 45/90] x86/cpu/amd: Use parsed CPUID(0x80000005) Date: Fri, 27 Mar 2026 03:15:59 +0100 Message-ID: <20260327021645.555257-46-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD BSP init, use parsed CPUID(0x80000005) instead of issuing a direct CPUID query and doing ugly bitwise operations. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/amd.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 224420f53ea9..67c983fd8d67 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only #include #include +#include #include #include #include @@ -421,6 +422,8 @@ static void tsa_init(struct cpuinfo_x86 *c) =20 static void bsp_init_amd(struct cpuinfo_x86 *c) { + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { =20 if (c->x86 > 0x10 || @@ -433,13 +436,8 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) } } =20 - if (c->x86 =3D=3D 0x15) { - unsigned long upperbit; - u32 cpuid, assoc; - - cpuid =3D cpuid_edx(0x80000005); - assoc =3D cpuid >> 16 & 0xff; - upperbit =3D ((cpuid >> 24) << 10) / assoc; + if (c->x86 =3D=3D 0x15 && el5) { + unsigned long upperbit =3D (el5->l1_icache_size_kb * SZ_1K) / el5->l1_ic= ache_assoc; =20 va_align.mask =3D (upperbit - 1) & PAGE_MASK; va_align.flags =3D ALIGN_VA_32 | ALIGN_VA_64; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CC3933067C for ; Fri, 27 Mar 2026 02:20:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578012; cv=none; b=U7sDExRoDZ5Jep7E6Tj3uks9DjnK6B7Lf9HdABBqharGwDAms58ZUhthyHq8yYuUcQQI4MOVCGJ6s+Pxr+UqZ4Gx5pC+DwXPahyHNpSpids/k9XLD1aYDgWPcGx/ds/WA0CENKclufRzScNibZ2tdK+HUWEufP0QNXR4LPFpm3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578012; c=relaxed/simple; bh=jkMO0hjjn8157XNG/+Xi7KSBrnxHXTnPq+E1cKLTB1c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d59x2yqed3ecesn5MXTgVU4Hi/aRlbymLNNv67yS+8/IL+Z3EnkhZlfPpAw0GoQRot9pq8b5ltTgUnSJt1Zw6LzAU69jBSyQ/32uepTpaB01sz0R8UGa/HyoRw3YBJijeRVyWVNilIjMeSCkKUfto05CSnewqEDVdposgkRrilc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Z4rYMFNp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=kjxi6tnL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Z4rYMFNp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="kjxi6tnL" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ANb4/iSYsCeq6/Qhn0I60Iai+Bv+XF6XwjH/S1GPJ4A=; b=Z4rYMFNp9zYOR2268bUSrx29Bimr4ohKMn0UexXcQaFIXahd+mnhd13p4dKWLHjdRROx/Z ultzUPbvMHvCbJwOE8nMoANaspNS0ljNiEOsZeLty6+R7B8PKaTIvj0Ob2CPT1QQgOGywl /B19WPM/N9+8D/PTBzzKol9+ljiIn5iZezEKZPEpFX5nLktkgIjpUDZHcrra9LwnhRT5ZU lMTQGsu2HigMY1lRI60UpjpcUtL3cXHPxqWeIlRs9XK/XE9qWf4vEzptfwkGPgzOxlVJow ZRz1Lt/NvZY9o3d+qkhoxpKymBxd9ts7o8yfkhiD8CN8vmZbRZm6VpF2X1Mljg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ANb4/iSYsCeq6/Qhn0I60Iai+Bv+XF6XwjH/S1GPJ4A=; b=kjxi6tnL4gbO71o/vTyGWVD+OD8ddpuloIKe7wartlbCoA9YN/z1pCHtyp55+Ag8+nnJ3G ZiQq6w6i6b5Z28Cg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 46/90] x86/cpu/amd: Refactor TLB detection code Date: Fri, 27 Mar 2026 03:16:00 +0100 Message-ID: <20260327021645.555257-47-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AMD's TLB init code fills below global variables: - tlb_lld_4k, tlb_lli_4k - tlb_lld_2m, tlb_lli_2m - tlb_lld_4m, tlb_lli_4m CPUID(0x80000006) reports these DTLB/ITLB numbers for L2, while CPUID(0x80000005) reports such numbers for L1. The code sets these variables with the L2 numbers by default. If the latter is not available, then the L1 numbers are used as a fallback. Refactor the TLB init logic before converting it to the parsed CPUID API. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/amd.c | 54 ++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 32 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 67c983fd8d67..e13f5d05d7cf 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1179,50 +1179,40 @@ static unsigned int amd_size_cache(struct cpuinfo_x= 86 *c, unsigned int size) =20 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) { - u32 ebx, eax, ecx, edx; - u16 mask =3D 0xfff; + u32 l2_tlb_eax, l2_tlb_ebx, l1_tlb_eax; + u16 l2_mask =3D 0xfff, l1_mask =3D 0xff; =20 - if (c->x86 < 0xf) + if (c->x86 < 0xf || c->extended_cpuid_level < 0x80000006) return; =20 - if (c->extended_cpuid_level < 0x80000006) - return; - - cpuid(0x80000006, &eax, &ebx, &ecx, &edx); + l2_tlb_eax =3D cpuid_eax(0x80000006); + l2_tlb_ebx =3D cpuid_ebx(0x80000006); + l1_tlb_eax =3D cpuid_eax(0x80000005); =20 - tlb_lld_4k =3D (ebx >> 16) & mask; - tlb_lli_4k =3D ebx & mask; + tlb_lld_4k =3D (l2_tlb_ebx >> 16) & l2_mask; + tlb_lli_4k =3D l2_tlb_ebx & l2_mask; =20 /* - * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB - * characteristics from the CPUID function 0x80000005 instead. + * K8 does not report 2M/4M entries in the L2 TLB, so always use + * the L1 TLB information there. On later CPUs, fall back to L1 + * when the L2 entry count is zero. */ - if (c->x86 =3D=3D 0xf) { - cpuid(0x80000005, &eax, &ebx, &ecx, &edx); - mask =3D 0xff; - } =20 - /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ - if (!((eax >> 16) & mask)) - tlb_lld_2m =3D (cpuid_eax(0x80000005) >> 16) & 0xff; - else - tlb_lld_2m =3D (eax >> 16) & mask; - - /* a 4M entry uses two 2M entries */ - tlb_lld_4m =3D tlb_lld_2m >> 1; + tlb_lld_2m =3D (l2_tlb_eax >> 16) & l2_mask; + if (c->x86 =3D=3D 0xf || !tlb_lld_2m) + tlb_lld_2m =3D (l1_tlb_eax >> 16) & l1_mask; =20 - /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ - if (!(eax & mask)) { + tlb_lli_2m =3D l2_tlb_eax & l2_mask; + if (c->x86 =3D=3D 0xf || !tlb_lli_2m) { /* Erratum 658 */ - if (c->x86 =3D=3D 0x15 && c->x86_model <=3D 0x1f) { + if (c->x86 =3D=3D 0x15 && c->x86_model <=3D 0x1f) tlb_lli_2m =3D 1024; - } else { - cpuid(0x80000005, &eax, &ebx, &ecx, &edx); - tlb_lli_2m =3D eax & 0xff; - } - } else - tlb_lli_2m =3D eax & mask; + else + tlb_lli_2m =3D l1_tlb_eax & l1_mask; + } =20 + /* A 4M entry uses two 2M entries */ + tlb_lld_4m =3D tlb_lld_2m >> 1; tlb_lli_4m =3D tlb_lli_2m >> 1; =20 /* Max number of pages INVLPGB can invalidate in one shot */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86F68366DAE for ; Fri, 27 Mar 2026 02:20:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578015; cv=none; b=Qvck4bhKDnf3zopqTI0dnevXEzWWRLdF3OkKlb9VB3O53isk6uWf9E505zZQROwNckRoM6pc4wnVEBcFLHZCgM6qVPN3Xa1JKflT3epQgAnYPeNBDc1+lAMICPYr57HgiSp7xCSrxDefbSB1UpiT9jjtIw5CKzkCnpLlbr7Jgw4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578015; c=relaxed/simple; bh=jwHw3hWLyrrLQ379KF5w8+hprxJhcEgL3MIQ1cUzsmc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nkGkctn4iPPOflyNUMxCv6aZOTImhVe1GYCtn/O9QQnLRf4+YN2cuTUWqvh+oeo+MDHkD/Wer1OWFaUzM+gd3ey55wDkqZI9kVj2vTYrL3v11TXrdf2ShsRvQCLXMYOXCirmbPU77ZWOxXdWTP/+GVnwWvtm16+uWtdnSaCdH/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0SHjHK4h; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2wnAJa89; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0SHjHK4h"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2wnAJa89" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 47/90] x86/cpu/amd: Use parsed CPUID(CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:16:01 +0100 Message-ID: <20260327021645.555257-48-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD TLB detection, use parsed CPUID(0x80000005) and CPUID(0x80000006) instead of direct CPUID queries and ugly bitwise operations. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/amd.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e13f5d05d7cf..5fd7f34fa284 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -1179,18 +1179,14 @@ static unsigned int amd_size_cache(struct cpuinfo_x= 86 *c, unsigned int size) =20 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) { - u32 l2_tlb_eax, l2_tlb_ebx, l1_tlb_eax; - u16 l2_mask =3D 0xfff, l1_mask =3D 0xff; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); =20 - if (c->x86 < 0xf || c->extended_cpuid_level < 0x80000006) + if (c->x86 < 0xf || !el5 || !el6) return; =20 - l2_tlb_eax =3D cpuid_eax(0x80000006); - l2_tlb_ebx =3D cpuid_ebx(0x80000006); - l1_tlb_eax =3D cpuid_eax(0x80000005); - - tlb_lld_4k =3D (l2_tlb_ebx >> 16) & l2_mask; - tlb_lli_4k =3D l2_tlb_ebx & l2_mask; + tlb_lld_4k =3D el6->l2_dtlb_4k_nentries; + tlb_lli_4k =3D el6->l2_itlb_4k_nentries; =20 /* * K8 does not report 2M/4M entries in the L2 TLB, so always use @@ -1198,17 +1194,17 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *= c) * when the L2 entry count is zero. */ =20 - tlb_lld_2m =3D (l2_tlb_eax >> 16) & l2_mask; + tlb_lld_2m =3D el6->l2_dtlb_2m_4m_nentries; if (c->x86 =3D=3D 0xf || !tlb_lld_2m) - tlb_lld_2m =3D (l1_tlb_eax >> 16) & l1_mask; + tlb_lld_2m =3D el5->l1_dtlb_2m_4m_nentries; =20 - tlb_lli_2m =3D l2_tlb_eax & l2_mask; + tlb_lli_2m =3D el6->l2_itlb_2m_4m_nentries; if (c->x86 =3D=3D 0xf || !tlb_lli_2m) { /* Erratum 658 */ if (c->x86 =3D=3D 0x15 && c->x86_model <=3D 0x1f) tlb_lli_2m =3D 1024; else - tlb_lli_2m =3D l1_tlb_eax & l1_mask; + tlb_lli_2m =3D el5->l1_itlb_2m_4m_nentries; } =20 /* A 4M entry uses two 2M entries */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D24F9351C25 for ; Fri, 27 Mar 2026 02:20:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578020; cv=none; b=uQvWumVwr6GVWCQVCZ9rJLPGnL1q9m+jD7RRDWpB2IlCacvy9OMYPShNNy9RLoQ8q+SIQAU3K81xy9J5/LZip6vDDTt6HK7IgNJlECW80JN07rpmZMss8/36/hKBhVxDmoYzG8IR61Ex0s61cFtVaWXMI4q0edO4ogMQsaU1BA8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578020; c=relaxed/simple; bh=H+R2ySs/TeQzqZ7gQrEkYaY8Hq+9Sz0DVaRsgl9tZCs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mr5K8OxRzOxhbEiIYBvgBWD0bYGKyOfN22zKAKQp+PMpou25k3XQc8R1g2oGuzAiWbACjE82Ump/KNMMcfooOQCcQlGz2Ka2c3gXDUlID3pPzZ63NeT4wB+5ORhizr/WfmDLw4Vk9yP1K3TG6FnGam8jfyG0pNk1lzno+O2vyHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=G6NiLS0h; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+gG9hqto; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="G6NiLS0h"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+gG9hqto" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 48/90] x86/cpu/hygon: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Date: Fri, 27 Mar 2026 03:16:02 +0100 Message-ID: <20260327021645.555257-49-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Hygon init, use parsed CPUID(0x80000005) and CPUID(0x80000006) instead of direct CPUID queries and ugly bitwise operations. Consolidate all comments; the code has now clear logic and bitfield names. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/hygon.c | 35 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 3e8891a9caf2..4a63538c2b3f 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -229,35 +229,32 @@ static void init_hygon(struct cpuinfo_x86 *c) clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE); } =20 +/* + * For DTLB/ITLB 2M-4M detection, fall back to L1 if L2 is disabled + */ static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c) { - u32 ebx, eax, ecx, edx; - u16 mask =3D 0xfff; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); =20 - if (c->extended_cpuid_level < 0x80000006) + if (!el5 || !el6) return; =20 - cpuid(0x80000006, &eax, &ebx, &ecx, &edx); + tlb_lld_4k =3D el6->l2_dtlb_4k_nentries; + tlb_lli_4k =3D el6->l2_itlb_4k_nentries; =20 - tlb_lld_4k =3D (ebx >> 16) & mask; - tlb_lli_4k =3D ebx & mask; + if (el6->l2_dtlb_2m_4m_nentries) + tlb_lld_2m =3D el6->l2_dtlb_2m_4m_nentries; + else + tlb_lld_2m =3D el5->l1_dtlb_2m_4m_nentries; =20 - /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ - if (!((eax >> 16) & mask)) - tlb_lld_2m =3D (cpuid_eax(0x80000005) >> 16) & 0xff; + if (el6->l2_itlb_2m_4m_nentries) + tlb_lli_2m =3D el6->l2_itlb_2m_4m_nentries; else - tlb_lld_2m =3D (eax >> 16) & mask; + tlb_lli_2m =3D el5->l1_itlb_2m_4m_nentries; =20 - /* a 4M entry uses two 2M entries */ + /* A 4M TLB entry uses two 2M entries */ tlb_lld_4m =3D tlb_lld_2m >> 1; - - /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ - if (!(eax & mask)) { - cpuid(0x80000005, &eax, &ebx, &ecx, &edx); - tlb_lli_2m =3D eax & 0xff; - } else - tlb_lli_2m =3D eax & mask; - tlb_lli_4m =3D tlb_lli_2m >> 1; } =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 152DA33BBD9 for ; Fri, 27 Mar 2026 02:20:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578024; cv=none; b=QeJIR9ZQDNOnupJ7nD784fAV4MlmkFW1WDbkk5SBqhjw/OxxHJ2PmDjz9s3UCLi1l4r+WQc9loghpRDSIhZByEHmB68HruH8SXVslCD3JxqC7WmMbKlOpupCrP+yPrUSLb93pYn/ztWGbhFjVhcl0xfs1R5G0QAjlCYX/wS/e4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578024; c=relaxed/simple; bh=K5QV4Csrx/OJgyOr6M7gAmcH7YP/aauAzE3ym9oi7oc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Iw65iIR35eNF2kV+6Toe+YMewzmL70Z3qrkmcBFDwDTnbhB6OjiGU1BOFNW0BDhjRgiPDZLQYfojRkun6iUxQC4XWNxdjpgHBl39OVH+NR9tUrAaIB/PQGzc6bZfQyPI4Hv23imBpAx92HOWZr2qjciZTd1YaKmPDX3niOMxRrY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iQLT82Nj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=EcACkX58; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iQLT82Nj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="EcACkX58" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578020; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X49npTsIRUaGG3MII35rGUtLXF7646imzEvEVZkLaaU=; b=iQLT82NjPOdLoyJJoAbdxKPzoyjBhAu4rQhXpVdDYwhtNHVM076HJeXgb2AZX5v1EDFaL2 eSJGR/uE8jJaPZssYaKSKerNjMQVDE3Ib6xxSCKLVFV/VB/oggvZ6gT3gNDymkBVuCQf8/ 73AY5SFKNfvTihHjjk5GxLlAZisnm1hAIZ08wVL1MYIyvpHqtcZVVzW8aUl9esa/MLBtLB jUgQHGeofxJHPsGW9JqVORSqzFQFPoGQDhN23R1IKsGt2uEVm+wQ6SKPh57Pi0QC4XyFTt bKI+3tL+7Ncj1jg6gmFTKSfBbUyi9FF7+voKiFRiyOerqUbtLxLBAMiK+lrlsQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578020; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X49npTsIRUaGG3MII35rGUtLXF7646imzEvEVZkLaaU=; b=EcACkX58oWlxHR7oQ7vQniZDsLlXVRmvgzcd5gdciDs94Lxlqim9xPTW/Co2a9v+LAcKeq XYKKJBc2+2sCv3Aw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 49/90] x86/cpu/centaur: Use parsed CPUID(0x80000005) Date: Fri, 27 Mar 2026 03:16:03 +0100 Message-ID: <20260327021645.555257-50-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000005) instead of issuing a CPUID query and doing ugly bitwise operations. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 5f09bce3aaa7..895cf00919d3 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -107,11 +107,11 @@ static void early_init_centaur(struct cpuinfo_x86 *c) static void init_centaur(struct cpuinfo_x86 *c) { #ifdef CONFIG_X86_32 - char *name; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + u32 lo, hi, newlo; u32 fcr_set =3D 0; u32 fcr_clr =3D 0; - u32 lo, hi, newlo; - u32 aa, bb, cc, dd; + char *name; #endif early_init_centaur(c); init_intel_cacheinfo(c); @@ -181,13 +181,8 @@ static void init_centaur(struct cpuinfo_x86 *c) /* Set 3DNow! on Winchip 2 and above. */ if (c->x86_model >=3D 8) set_cpu_cap(c, X86_FEATURE_3DNOW); - /* See if we can find out some more. */ - if (cpuid_eax(0x80000000) >=3D 0x80000005) { - /* Yes, we can. */ - cpuid(0x80000005, &aa, &bb, &cc, &dd); - /* Add L1 data and code cache sizes. */ - c->x86_cache_size =3D (cc>>24)+(dd>>24); - } + if (el5) + c->x86_cache_size =3D el5->l1_dcache_size_kb + el5->l1_icache_size_kb; sprintf(c->x86_model_id, "WinChip %s", name); } #endif --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA02D36A01B for ; Fri, 27 Mar 2026 02:20:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578028; cv=none; b=Ef7KpqRcHJu6yt4Fh6eJZaUrxqdGjUh1m/ShfN5/8G43Lx3B7tX6WAIwrHxZOk2EaZNB6YKSAvLhCikXpDDDJ06+0uS5Pb461EwknehxZBch/VjMXpeZ8XQhuxZiJW8K6bBrbokdVAYJSnrVVO+hdVLYIYRGyPG9VRTYunS/J1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578028; c=relaxed/simple; bh=16KudRD4xR2hDuMCTu815ecnor3Dwv8sz2KEEY3i4Sg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HQUNO0jBo8KQkHuUig3kGw22vlXXiU0RXI0eZLL9/23hl/IDlUfMwFINcfufAt/G6/N4IiEGts/9r9m6iTGBBpVg8ZBOyik/ui5ckZYOqL3HnwmLgyBOAoxP/1Q2V7MTQcdxY/8Y4i8q3mnpfs65Jd6FgPbMwzWbGpf752i9mk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=xxjwCVbh; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=R5FFRGFn; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="xxjwCVbh"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="R5FFRGFn" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 50/90] x86/cpu: Use parsed CPUID(0x80000008) Date: Fri, 27 Mar 2026 03:16:04 +0100 Message-ID: <20260327021645.555257-51-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000008) instead of issuing a direct CPUID query and doing ugly bitwise operations. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 5fa5463686ac..2beb53f6bed7 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1100,10 +1100,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) =20 void get_cpu_address_sizes(struct cpuinfo_x86 *c) { - u32 eax, ebx, ecx, edx; + const struct leaf_0x80000008_0 *el8 =3D cpuid_leaf(c, 0x80000008); =20 - if (!cpu_has(c, X86_FEATURE_CPUID) || - (c->extended_cpuid_level < 0x80000008)) { + if (!cpu_has(c, X86_FEATURE_CPUID) || !el8) { if (IS_ENABLED(CONFIG_X86_64)) { c->x86_clflush_size =3D 64; c->x86_phys_bits =3D 36; @@ -1118,10 +1117,8 @@ void get_cpu_address_sizes(struct cpuinfo_x86 *c) c->x86_phys_bits =3D 36; } } else { - cpuid(0x80000008, &eax, &ebx, &ecx, &edx); - - c->x86_virt_bits =3D (eax >> 8) & 0xff; - c->x86_phys_bits =3D eax & 0xff; + c->x86_virt_bits =3D el8->virt_addr_bits; + c->x86_phys_bits =3D el8->phys_addr_bits; =20 /* Provide a sane default if not enumerated: */ if (!c->x86_clflush_size) --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 208AD34FF6C for ; Fri, 27 Mar 2026 02:20:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578032; cv=none; b=EUb8y0jJvSttVQoogv9Nufi87fMlhcgR/WjrG4hB0BXwR6ALIG4HOlJjRZMbN19QldEpd9ypF5qR9hzOGuseni/RsfOmJgPZ3Ht1zdKhenM/hZqdlRPPHNd4mycYX681jzMG1GsyFmRdo5pSerPcyKg6r8LEkHk5LHnY+3QRJN4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578032; c=relaxed/simple; bh=VwUXreGC+Vi/5vw/JdCrvXHwp38HQ3xfg4TP3WOd4F4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lXjGOipnkPhnpuuD5WVbaJuHxhziNf3pz401J6DE46R3c9KE0OQabZTDnKlawTIPSBH43tvcMnoKSqG67IeDjG8SJhcrH6x4bDiycLO0YEXOipHC2WxeUrelzUOnZi+CLIpDIxBaQ51+SqXl8MuDSLXJscdwV5z42OUFxO1joRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=R8gHiAbv; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gwPIIB3g; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="R8gHiAbv"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gwPIIB3g" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9wbrrWIKKy8b9r6cx2Q/XHB/2YYtXWkLu3VJHGg4bxI=; b=R8gHiAbvMlUHHEYwlTZH11WCwLBRWIi20SCy9DMKEMK1VIrKkrv/oXpP4n1lewSzBKuWeA k70Ngh5od7OfhsXtHknLYew1ExjLWrukUyu42zYoEH6iFh4P5G0J2C226U1LjhFunaGi/N Aaht0uekoLEoxfp/vOMzz/tWMWlLgKaW8z/WgzFt3qcfQsomgQY1QCGpY0WU9pmSDZ0wPU 6hS/nOPIF6y32OxBPqgD3+54ghFf+95wtgnZsdypFOz+QIjYmkygig8+HgAoKmCF0/NNv2 poZpOj86Fcldp/HtnqHDpao+K0Se5zrVIFnDXaVzdeMJYgHnU87tyTcdOrcR4Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578029; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9wbrrWIKKy8b9r6cx2Q/XHB/2YYtXWkLu3VJHGg4bxI=; b=gwPIIB3gdBOyY65oT6TnI8lAfoyjt0lGNaxjGffoZvql4kvMGG5984Gu2HA1vEazFaOa7v w9HOPO5gWpDhfSDg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 51/90] x86/cpuid: Parse CPUID(0xa) and CPUID(0x1c) Date: Fri, 27 Mar 2026 03:16:05 +0100 Message-ID: <20260327021645.555257-52-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse CPUID(0xa) and CPUID(0x1c). This allows their call sites to be converted to the CPUID APIs next. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 2 ++ arch/x86/kernel/cpu/cpuid_parser.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index f50e54bfb514..128898d4434b 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -212,6 +212,8 @@ struct cpuid_leaves { CPUID_LEAF ( 0x1, 0 ); CPUID_LEAF ( 0x2, 0 ); CPUID_LEAF_N ( 0x4, 8 ); + CPUID_LEAF ( 0xa, 0 ); + CPUID_LEAF ( 0x1c, 0 ); CPUID_LEAF ( 0x16, 0 ); CPUID_LEAF ( 0x80000000, 0 ); CPUID_LEAF ( 0x80000002, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index ab391de03a92..8e147e7223e0 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -146,6 +146,8 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY ( 0x2, 0, 0x2 ), \ CPUID_PARSE_ENTRY_N ( 0x4, deterministic_cache ), \ + CPUID_PARSE_ENTRY ( 0xa, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x1c, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x16, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ @@ -198,7 +200,9 @@ struct cpuid_vendor_entry { /* Leaf Vendor list */ \ CPUID_VENDOR_ENTRY(0x2, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ CPUID_VENDOR_ENTRY(0x4, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ + CPUID_VENDOR_ENTRY(0xa, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ + CPUID_VENDOR_ENTRY(0x1c, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ CPUID_VENDOR_ENTRY(0x80860000, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860001, X86_VENDOR_TRANSMETA), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5838B36BCF3 for ; Fri, 27 Mar 2026 02:20:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578036; cv=none; b=ju/WN79i+Tj0uAM87MVFpAXz5xFQnWfDWF1HYw7DRH3EdWFx4hQJ6HmQvYalS0KZ+I0wvEa6WGxcp41dhrulEZZBiKCgeWboO8ijw5PdOUYX+k9XOiEwGvrqWGrUC6nf3VvjN44eLFfkJUgms56CHD3b9oL+i236MfwaOhu0qzU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578036; c=relaxed/simple; bh=5Qn7JTrQX1zgrCMOJmSHkg3rN59PTKEm6r51iNmKYM4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GajlUsA3eCCHiV+o+mvXqATwT2jE7e3yvhWj5VZXfC+ZTzEVY4FB78AlIhpsfZtGCxwWpxiWdW0+RaWVKZaUMjBPaPd7TiwzZPjWEnifv/u+Jc4z85V8bDiTgbnK34aG2UK6AqJrIqj4UQoxPwUYUcqm/jHZJdb4uySdiEfbYto= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=es8xllZX; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+nT+7LJ0; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="es8xllZX"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+nT+7LJ0" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578032; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iht5mEjzhrYTARHxYbj6POkN9dM0/zZilLNyR9zhoMA=; b=es8xllZX3xHzDjKBuIuB6CRmVE3jpf2WPGYH8yUv9lvKx7aaZKSPJRhiwqNt3Q16MkH0wx 8dxe4b7/le0nwj29BbK1CHbV1tBHZbKGFWUVVA7PLTtBjCOYCy+H180w89QVxRkHdnh5n4 0oEojcTX2Ui++nWnveiV+201xs/LDC6Wq58WGUqPlMs3IN9OWnpqUfbK6AVsxRqAm0fy8T TecD6aSOnzu2tKirsCMafFxzO8Pd4TYHCEGGwXmKAz+uvZ9QDD1OtmDJYzDL+zkeJ3lJSb QoFxOOFvgykoqtJUD1hGprl0e7WsO+NPnhsBHGrQW19Xab97YELsVHK8O+tQwA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578032; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iht5mEjzhrYTARHxYbj6POkN9dM0/zZilLNyR9zhoMA=; b=+nT+7LJ0i6TKCJooCkmOZrGsZw7XPqkF3Kc6NYchplJHXHOREbkxyTNZVRDIYMqCS4hOy8 Ueukp+alBtzp8yAA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 52/90] x86/cpu/intel: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:06 +0100 Message-ID: <20260327021645.555257-53-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Intel's PMU enumeration, use parsed CPUID(0xa) instead of a CPUID query and ugly bitwise operations. Remove comments; the generated bitfield names already make everything clear. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 615e3a4872b7..7f186c68d701 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -547,18 +547,16 @@ static const struct x86_cpu_id zmm_exclusion_list[] = =3D { =20 static void init_intel(struct cpuinfo_x86 *c) { + const struct leaf_0xa_0 *la =3D cpuid_leaf(c, 0xa); + early_init_intel(c); =20 intel_workarounds(c); =20 init_intel_cacheinfo(c); =20 - if (c->cpuid_level > 9) { - unsigned eax =3D cpuid_eax(10); - /* Check for version and the number of counters */ - if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) - set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); - } + if (la && la->pmu_version && la->num_counters_gp > 1) + set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); =20 if (cpu_has(c, X86_FEATURE_XMM2)) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E42636C0A3 for ; Fri, 27 Mar 2026 02:20:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578039; cv=none; b=svOeA6AzwmdzYjEKBT1xOM/7ywgFLZgM5VGlaUBLGK5NAnXqVuMBPTmOYganr+VWojVlTbfbV6QoLyYN+XMm7cbzH5Frxsbu7f+s5cDE+tXedKgq10sdTcoEwlhFbewuLzCQmSZa/AH1Wvv2+hSll03TcIjzPOXWU6/ZefWhRVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578039; c=relaxed/simple; bh=GJ0vuQ7qDmqzD6ffQfJTcKI5klRULf7H+l4njbgntPY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HLanES7fIcY+/92sIlTaP7589w/y5umcIASIt1QiwD4qYOj78+UYbNkI/IShLYYjby829YqG20a8eTAydZ/Lp0OphkUHRY8DbLB2XRaPnDQ+MbH9zQkH/spPmJ8PfH718XLdf7+yoYP0vDZw4UMrUZIREG+En09pOvCRCzNlLTQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TDlqIpuD; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NFXaaFfB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TDlqIpuD"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NFXaaFfB" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 53/90] x86/cpu/centaur: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:07 +0100 Message-ID: <20260327021645.555257-54-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Centaur's PMU enumeration, use parsed CPUID(0xa) instead of a direct CPUID query and ugly bitwise operations. Remove comments; the generated bitfield names already make everything clear. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 895cf00919d3..86cbe4427453 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -106,6 +106,7 @@ static void early_init_centaur(struct cpuinfo_x86 *c) =20 static void init_centaur(struct cpuinfo_x86 *c) { + const struct leaf_0xa_0 *la =3D cpuid_leaf(c, 0xa); #ifdef CONFIG_X86_32 const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); u32 lo, hi, newlo; @@ -116,17 +117,8 @@ static void init_centaur(struct cpuinfo_x86 *c) early_init_centaur(c); init_intel_cacheinfo(c); =20 - if (c->cpuid_level > 9) { - unsigned int eax =3D cpuid_eax(10); - - /* - * Check for version and the number of counters - * Version(eax[7:0]) can't be 0; - * Counters(eax[15:8]) should be greater than 1; - */ - if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) - set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); - } + if (la && la->pmu_version && la->num_counters_gp > 1) + set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); =20 #ifdef CONFIG_X86_32 if (c->x86 =3D=3D 5) { --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 922F836C5B5 for ; Fri, 27 Mar 2026 02:20:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578042; cv=none; b=iQsruJSWagb6MZ4QMCglEw0mvH+59pMAdIRHgYWly1yLO6p964ZM3TMknqeI4Cy9lqGKP0LBMTkdQCM/P1Kmv7ZkvTdIXD4HzepwAPSvJCk1XCy9eWpP2TEL0/z6eXeaf5rH3SeMaR1JGp2xo6vnXceuFUHO4vHNJg3CDoigGbc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578042; c=relaxed/simple; bh=S6PdoKoVK1RAbiChDpJafvEQ+U++BXqbd5oCCTs8c+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KechwZ7xN2Ha7K2TzHliKQt8QaSefh0B9HNG7Wo09dQegU7puXundkBXXHxHSuRQgRtW0k4VWVX+uYO7hHdUX0MJK0VGN6PgEQrYcLZPs3pDT5g+2ioCQd4c9gJ0Inz/+AZDsiSAUj44gpB+FSpl8Qyl7u/rivtGoOgNwGKOgUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nJyy3Xin; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DyrMb3MF; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nJyy3Xin"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DyrMb3MF" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 54/90] x86/cpu/zhaoxin: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:08 +0100 Message-ID: <20260327021645.555257-55-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Zhaoxin's PMU enumeration, use parsed CPUID(0xa) instead of a direct CPUID query and ugly bitwise operations. Remove comments; the generated bitfield names already make everything clear. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/zhaoxin.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index ea76e9594453..b068922efed9 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -61,20 +61,13 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c) =20 static void init_zhaoxin(struct cpuinfo_x86 *c) { + const struct leaf_0xa_0 *la =3D cpuid_leaf(c, 0xa); + early_init_zhaoxin(c); init_intel_cacheinfo(c); =20 - if (c->cpuid_level > 9) { - unsigned int eax =3D cpuid_eax(10); - - /* - * Check for version and the number of counters - * Version(eax[7:0]) can't be 0; - * Counters(eax[15:8]) should be greater than 1; - */ - if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1)) - set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); - } + if (la && la->pmu_version && la->num_counters_gp > 1) + set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); =20 if (c->x86 >=3D 0x6) init_zhaoxin_cap(c); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7F9233E35B for ; Fri, 27 Mar 2026 02:20:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578048; cv=none; b=X2kcP00WUgY2zGjSkORbgMVuOMNc8Y8wHFN7n1eOP5KJ85G2JGVK4ODsYeHYLXSk5GzCJMaqF//fKdX6uL259ThyennYIfwuMjpX6exBNzo8fYMmyDwYOppMuoAGPcbNaOJxSz/wmoYvGwH45Dsg7jz+jULoljsLbBQroPh+CUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578048; c=relaxed/simple; bh=BAtrVKMVi846Ie6chOl8KFQS2IufHw/jv9kl0xAXZcA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zuvk+EhyU32sqmABKbLSVQDmsO1adl7GFuDaJNVomZXAtnIUO0WPUjw+RkdLbCy5rqmLLs9V+9aV2ykneW92qgzM/zTIdJ/mYErOmhz3NyLBylDgV+/tAHK9eHR4hB63G8bYGl/q1tR1eO06vgMwwPbk2cl8u4IuHhuZnm8aWpA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KKrsq9Ar; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=j2zXp7Ta; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KKrsq9Ar"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="j2zXp7Ta" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578043; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L6IhjQkwIqi8FH44qYfqOqFMRg8JhPc5lRljpQEpfb8=; b=KKrsq9Argr+YAGqnkhqYakJuZJJ8OrJ4WXJJouPLDj5l/2PqqNQN8rHUj7Pt6hUhD8j015 OGVck7X0uuMxNKUa2O0FZlw9AXRz8fimF67SlB0zaJCDvgzsImILMfAh9LiIBZ/HcyIo8+ wmDbJxFaAfG96DIxg7vzeGyDGniZUo3L/2gn6Ydm2szd49TDo/o0dtZx0M2Mr88gY/cNuB v/cTtmJCHxBVQGMWiwlK10WoMfcXUl7Mx2uQSesYV6yGwcsNzLBjWQZyM8G3Gev7Q01j1M 3W9UFwm7NzQ5/sDLcbrc02X0WNRQK0TcTWMfcY9G1ZJYG40ppD8cFviNVdeK7g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578043; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=L6IhjQkwIqi8FH44qYfqOqFMRg8JhPc5lRljpQEpfb8=; b=j2zXp7Tax76cK0wClJ1q4qRYBuTwstKYTABcTSPLc1TA9cNO91Yqtd5v4aQjNYEpCVpk0C HLPt2OcJ8Fesy3AA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 55/90] perf/x86/intel: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:09 +0100 Message-ID: <20260327021645.555257-56-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Intel perfmon, use parsed CPUID(0xa) instead of issuing CPUID queries and defining custom CPUID output data types. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/intel/core.c | 41 ++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index d1107129d5ad..20dece48b994 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6577,10 +6577,11 @@ static __init void intel_arch_events_quirk(void) =20 static __init void intel_nehalem_quirk(void) { - union cpuid10_ebx ebx; + struct leaf_0xa_0 l =3D { }; + struct cpuid_regs *regs =3D (struct cpuid_regs *)&l; =20 - ebx.full =3D x86_pmu.events_maskl; - if (ebx.split.no_branch_misses_retired) { + regs->ebx =3D x86_pmu.events_maskl; + if (l.no_br_misses_retired) { /* * Erratum AAJ80 detected, we work it around by using * the BR_MISP_EXEC.ANY event. This will over-count @@ -6588,8 +6589,8 @@ static __init void intel_nehalem_quirk(void) * architectural event which is often completely bogus: */ intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] =3D 0x7f89; - ebx.split.no_branch_misses_retired =3D 0; - x86_pmu.events_maskl =3D ebx.full; + l.no_br_misses_retired =3D 0; + x86_pmu.events_maskl =3D regs->ebx; pr_info("CPU erratum AAJ80 worked around\n"); } } @@ -7522,15 +7523,13 @@ static __always_inline void intel_pmu_init_arw(stru= ct pmu *pmu) =20 __init int intel_pmu_init(void) { + const struct cpuid_regs *regs =3D cpuid_leaf_raw(&boot_cpu_data, 0xa); + const struct leaf_0xa_0 *leaf =3D cpuid_leaf(&boot_cpu_data, 0xa); struct attribute **extra_skl_attr =3D &empty_attrs; struct attribute **extra_attr =3D &empty_attrs; struct attribute **td_attr =3D &empty_attrs; struct attribute **mem_attr =3D &empty_attrs; struct attribute **tsx_attr =3D &empty_attrs; - union cpuid10_edx edx; - union cpuid10_eax eax; - union cpuid10_ebx ebx; - unsigned int fixed_mask; bool pmem =3D false; int version, i; char *name; @@ -7554,27 +7553,29 @@ __init int intel_pmu_init(void) return -ENODEV; } =20 + if (!leaf || !regs) + return -ENODEV; + /* * Check whether the Architectural PerfMon supports * Branch Misses Retired hw_event or not. */ - cpuid(10, &eax.full, &ebx.full, &fixed_mask, &edx.full); - if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT) + if (leaf->events_mask_len < ARCH_PERFMON_EVENTS_COUNT) return -ENODEV; =20 - version =3D eax.split.version_id; + version =3D leaf->pmu_version; if (version < 2) x86_pmu =3D core_pmu; else x86_pmu =3D intel_pmu; =20 x86_pmu.version =3D version; - x86_pmu.cntr_mask64 =3D GENMASK_ULL(eax.split.num_counters - 1, 0); - x86_pmu.cntval_bits =3D eax.split.bit_width; - x86_pmu.cntval_mask =3D (1ULL << eax.split.bit_width) - 1; + x86_pmu.cntr_mask64 =3D GENMASK_ULL(leaf->num_counters_gp - 1, 0); + x86_pmu.cntval_bits =3D leaf->bit_width_gp; + x86_pmu.cntval_mask =3D (1ULL << leaf->bit_width_gp) - 1; =20 - x86_pmu.events_maskl =3D ebx.full; - x86_pmu.events_mask_len =3D eax.split.mask_length; + x86_pmu.events_maskl =3D regs->ebx; + x86_pmu.events_mask_len =3D leaf->events_mask_len; =20 x86_pmu.pebs_events_mask =3D intel_pmu_pebs_mask(x86_pmu.cntr_mask64); x86_pmu.pebs_capable =3D PEBS_COUNTER_MASK; @@ -7588,9 +7589,9 @@ __init int intel_pmu_init(void) int assume =3D 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR); =20 x86_pmu.fixed_cntr_mask64 =3D - GENMASK_ULL(max((int)edx.split.num_counters_fixed, assume) - 1, 0); + GENMASK_ULL(max((int)leaf->num_counters_fixed, assume) - 1, 0); } else if (version >=3D 5) - x86_pmu.fixed_cntr_mask64 =3D fixed_mask; + x86_pmu.fixed_cntr_mask64 =3D leaf->pmu_fcounters_bitmap; =20 if (boot_cpu_has(X86_FEATURE_PDCM)) { u64 capabilities; @@ -7612,7 +7613,7 @@ __init int intel_pmu_init(void) x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last= */ =20 if (version >=3D 5) { - x86_pmu.intel_cap.anythread_deprecated =3D edx.split.anythread_deprecate= d; + x86_pmu.intel_cap.anythread_deprecated =3D leaf->anythread_deprecation; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 56/90] perf/x86/zhaoxin: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:10 +0100 Message-ID: <20260327021645.555257-57-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Zhaoxin perfmon, use parsed CPUID(0xa) instead of issuing CPUID queries and defining custom CPUID output data types. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/zhaoxin/core.c | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/zhaoxin/core.c b/arch/x86/events/zhaoxin/core.c index 6ed644fe89aa..1c487d09f65c 100644 --- a/arch/x86/events/zhaoxin/core.c +++ b/arch/x86/events/zhaoxin/core.c @@ -505,39 +505,36 @@ static __init void zhaoxin_arch_events_quirk(void) =20 __init int zhaoxin_pmu_init(void) { - union cpuid10_edx edx; - union cpuid10_eax eax; - union cpuid10_ebx ebx; + const struct cpuid_regs *regs =3D cpuid_leaf_raw(&boot_cpu_data, 0xa); + const struct leaf_0xa_0 *leaf =3D cpuid_leaf(&boot_cpu_data, 0xa); struct event_constraint *c; - unsigned int unused; - int version; =20 pr_info("Welcome to zhaoxin pmu!\n"); =20 + if (!leaf || !regs) + return -ENODEV; + /* * Check whether the Architectural PerfMon supports * hw_event or not. */ - cpuid(10, &eax.full, &ebx.full, &unused, &edx.full); - - if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT - 1) + if (leaf->events_mask_len < ARCH_PERFMON_EVENTS_COUNT - 1) return -ENODEV; =20 - version =3D eax.split.version_id; - if (version !=3D 2) + if (leaf->pmu_version !=3D 2) return -ENODEV; =20 x86_pmu =3D zhaoxin_pmu; pr_info("Version check pass!\n"); =20 - x86_pmu.version =3D version; - x86_pmu.cntr_mask64 =3D GENMASK_ULL(eax.split.num_counters - 1, 0); - x86_pmu.cntval_bits =3D eax.split.bit_width; - x86_pmu.cntval_mask =3D (1ULL << eax.split.bit_width) - 1; - x86_pmu.events_maskl =3D ebx.full; - x86_pmu.events_mask_len =3D eax.split.mask_length; + x86_pmu.version =3D leaf->pmu_version; + x86_pmu.cntr_mask64 =3D GENMASK_ULL(leaf->num_counters_gp - 1, 0); + x86_pmu.cntval_bits =3D leaf->bit_width_gp; + x86_pmu.cntval_mask =3D (1ULL << leaf->bit_width_gp) - 1; + x86_pmu.events_maskl =3D regs->ebx; + x86_pmu.events_mask_len =3D leaf->events_mask_len; =20 - x86_pmu.fixed_cntr_mask64 =3D GENMASK_ULL(edx.split.num_counters_fixed - = 1, 0); + x86_pmu.fixed_cntr_mask64 =3D GENMASK_ULL(leaf->num_counters_fixed - 1, 0= ); x86_add_quirk(zhaoxin_arch_events_quirk); =20 switch (boot_cpu_data.x86) { @@ -617,4 +614,3 @@ __init int zhaoxin_pmu_init(void) =20 return 0; } - --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7916B33E35B for ; Fri, 27 Mar 2026 02:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578054; cv=none; b=KHJRbqeYCvk8e3buEGsyePxqiCZrfK2re8wSlgS/LzxDV0piNCezp3eN9hFhhGWmDIQ4Bm2qG0TuvNUtAGRunlk3bmaM56UlVO/oK33Yv3bV5PXwagvpYPVuA8g3GKETacTZPLucpCNHYXsUX9CACjMbyIMNOFybTkuva3syw+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578054; c=relaxed/simple; bh=PpQZQwVsIHVzCnYbAsCkY08mFzSN1Fxi90+5jsTuZ6Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XB+iSLATI/S0jG3NXYXccDcLLXloQVgDtjzbOa2+KPhbAEqwpqr8UUAkf6TwHYzxK9wrdsN8tQJYL5bJ251QElwu4koGGV0yCLlSmHshdxtusL57r3+fosUlwJSbQuYU94eTSZBJ2qZANUE6R7nDEKmFb0dMJBZ3OpZe/ru1SEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2gfDN5xR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=uArAP1KB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2gfDN5xR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="uArAP1KB" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 57/90] x86/xen: Use parsed CPUID(0xa) Date: Fri, 27 Mar 2026 03:16:11 +0100 Message-ID: <20260327021645.555257-58-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Xen PMU, use parsed CPUID(0xa) instead of a direct CPUID query and ugly bitwise operations. Remove the PMU_{GENERAL,FIXED}_NR macros as they are no longer needed. Signed-off-by: Ahmed S. Darwish --- arch/x86/xen/pmu.c | 26 +++++--------------------- 1 file changed, 5 insertions(+), 21 deletions(-) diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 5f50a3ee08f5..b0ef35f2bad3 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -48,18 +48,6 @@ static __read_mostly int amd_num_counters; #define MSR_TYPE_ARCH_COUNTER 3 #define MSR_TYPE_ARCH_CTRL 4 =20 -/* Number of general pmu registers (CPUID.EAX[0xa].EAX[8..15]) */ -#define PMU_GENERAL_NR_SHIFT 8 -#define PMU_GENERAL_NR_BITS 8 -#define PMU_GENERAL_NR_MASK (((1 << PMU_GENERAL_NR_BITS) - 1) \ - << PMU_GENERAL_NR_SHIFT) - -/* Number of fixed pmu registers (CPUID.EDX[0xa].EDX[0..4]) */ -#define PMU_FIXED_NR_SHIFT 0 -#define PMU_FIXED_NR_BITS 5 -#define PMU_FIXED_NR_MASK (((1 << PMU_FIXED_NR_BITS) - 1) \ - << PMU_FIXED_NR_SHIFT) - /* Alias registers (0x4c1) for full-width writes to PMCs */ #define MSR_PMC_ALIAS_MASK (~(MSR_IA32_PERFCTR0 ^ MSR_IA32_PMC0)) =20 @@ -70,6 +58,8 @@ static __read_mostly int intel_num_arch_counters, intel_n= um_fixed_counters; =20 static void xen_pmu_arch_init(void) { + const struct leaf_0xa_0 *leaf_a =3D cpuid_leaf(&boot_cpu_data, 0xa); + if (boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_AMD) { =20 switch (boot_cpu_data.x86) { @@ -98,15 +88,9 @@ static void xen_pmu_arch_init(void) amd_ctrls_base =3D MSR_K7_EVNTSEL0; amd_msr_step =3D 1; k7_counters_mirrored =3D 0; - } else { - uint32_t eax, ebx, ecx, edx; - - cpuid(0xa, &eax, &ebx, &ecx, &edx); - - intel_num_arch_counters =3D (eax & PMU_GENERAL_NR_MASK) >> - PMU_GENERAL_NR_SHIFT; - intel_num_fixed_counters =3D (edx & PMU_FIXED_NR_MASK) >> - PMU_FIXED_NR_SHIFT; + } else if (leaf_a) { + intel_num_arch_counters =3D leaf_a->num_counters_gp; + intel_num_fixed_counters =3D leaf_a->num_counters_fixed; } } =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADB29372ED7 for ; Fri, 27 Mar 2026 02:20:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578058; cv=none; b=Xe+2gid6gMKke5+yA1MwpNmDCdUqTPhkNu+H22BE63NL8gV9+4BLtjOsCK4A/m/Y0GzoM7Ylb8xTRDMjckexB4AnUMmso3oikOoWDs4ljHm6NPEclqyv8hrGrvPQq52Pgbkv4W3PxxrMWu/ODxw3I1lrlQRq4BcWL5dyk3sq3G8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578058; c=relaxed/simple; bh=PsTllU6sNA+kea6As9e7l++xqbcFkRXHRpyiRFTUg+I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fBKqpn+muvzt+K5vo5kPneFSWzsMBudCBXFMzpUIa30sXsbpzZ0wlyCR7NKr0YClBWl5IUv3ta+8EtAGLPxguLkLQvs/pUJod9ICFc7TY8JFBIveR7ZO/nXEqIqRQR8SbZpeO/sSmVf7VdX0lwIy0agTBBVUGDsHgbaGu6ouJeQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wBP8Eb9e; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Yy+Tlxvt; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wBP8Eb9e"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Yy+Tlxvt" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578055; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kO+BQ4fERUyR/doqb1nb45u/9n2WJ1LYDd/Hl6t97Hk=; b=wBP8Eb9ecI+9s/BizsyIP4HiSolbZMxVm0DoOWiwaXhWmOanzedBXihOAUZ3m+vV2Vh47I ulOv/gzoVyGqVpQ1hqnUiLCMjo+JuMANptvvYjdbWf1g4QjXUTCdNMqbVPzNMq2tOUgTIr UF1FbFXb1JGX4kpXdYCqn2tgrLLEY/+56wAhyTpqYBQZKrP7as5J7zRrtqCYclh/zSTdtX fUpp+LreZVwtC4eeClbGTDzBKkw+lTuBuHu8wpfFjHU26ZgaR58rKLvOpnqCejGCHJ3BiT S4+jo3F/kPSvYb7qRxJQE7hBPGA65jWB7gZGPFF4ZkWf66D8cGM1Co/tIndrwg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578055; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kO+BQ4fERUyR/doqb1nb45u/9n2WJ1LYDd/Hl6t97Hk=; b=Yy+TlxvtvVbku4q4FrQjwnMkMG0ya20jprYizkoE/HEpA+Vlf017WZosiRZPg1FhFGsFCw p9S15RHd+zBU9OCg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 58/90] KVM: x86: Use standard CPUID(0xa) types Date: Fri, 27 Mar 2026 03:16:12 +0100 Message-ID: <20260327021645.555257-59-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For KVM guest CPUID build-up, use the auto-generated CPUID(0xa) types from x86-cpuid-db instead of relying on the custom perf types. The latter types are in process of getting removed from the kernel. Signed-off-by: Ahmed S. Darwish --- arch/x86/kvm/cpuid.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 8137927e7387..16ed4c001c79 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1503,28 +1503,28 @@ static inline int __do_cpuid_func(struct kvm_cpuid_= array *array, u32 function) } break; case 0xa: { /* Architectural Performance Monitoring */ - union cpuid10_eax eax =3D { }; - union cpuid10_edx edx =3D { }; + struct leaf_0xa_0 l =3D { }; + struct cpuid_regs *regs =3D (struct cpuid_regs *)&l; =20 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { entry->eax =3D entry->ebx =3D entry->ecx =3D entry->edx =3D 0; break; } =20 - eax.split.version_id =3D kvm_pmu_cap.version; - eax.split.num_counters =3D kvm_pmu_cap.num_counters_gp; - eax.split.bit_width =3D kvm_pmu_cap.bit_width_gp; - eax.split.mask_length =3D kvm_pmu_cap.events_mask_len; - edx.split.num_counters_fixed =3D kvm_pmu_cap.num_counters_fixed; - edx.split.bit_width_fixed =3D kvm_pmu_cap.bit_width_fixed; + l.pmu_version =3D kvm_pmu_cap.version; + l.num_counters_gp =3D kvm_pmu_cap.num_counters_gp; + l.bit_width_gp =3D kvm_pmu_cap.bit_width_gp; + l.events_mask_len =3D kvm_pmu_cap.events_mask_len; + l.num_counters_fixed =3D kvm_pmu_cap.num_counters_fixed; + l.bitwidth_fixed =3D kvm_pmu_cap.bit_width_fixed; =20 if (kvm_pmu_cap.version) - edx.split.anythread_deprecated =3D 1; + l.anythread_deprecation =3D 1; =20 - entry->eax =3D eax.full; + entry->eax =3D regs->eax; entry->ebx =3D kvm_pmu_cap.events_mask; entry->ecx =3D 0; - entry->edx =3D edx.full; + entry->edx =3D regs->edx; break; } case 0x1f: --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B03D1374195 for ; Fri, 27 Mar 2026 02:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578061; cv=none; b=hCr6MW27eC7BxgNPa4cg/TIMFmpRTIKYVIpikME1uEL7CFC9iP1mT0CRV7JMqAYEWhqg+9JxXJ7sCZTiImYdm9t8hDgPwKshW3aR99U9vKyRohHTix+VQqNS2spiduZfIE7uIiRDFXgH+syq/tc+/8vf898/r4Sq/O5kYBaAszI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578061; c=relaxed/simple; bh=3EwSVXzKb38A0kXx3OdyT4KXgnLusic6Pcj2rho7Nrc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B6HjaqxaRo9qbAeYV0THx7la2Qx6Gyezot3WramYQtWzMcA+px2tmbpWiSQlVAMqKTvJwflh4AQMRrE/IBpGW+ByvCyqXhB39Zspm8/umJNQDp9vpu21P70rAzJ5Xo9l072BKt7ZKYLAhe+EBGsHdtH9pBQEV3QSVbyDD31CV0E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gjc4v5XP; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3Vs7OAVx; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gjc4v5XP"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3Vs7OAVx" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578058; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RRSX54I0iJeSrYG1pJupkqNr+r3Vka+Wq09nGaVn1Sg=; b=gjc4v5XP6a+fJlAj5JOeZf3OqlGpbc6eE7X6UE9XwZB86siXFfAyb/aNyj7gCrAgDiTkG+ l3bbOkqXDDsKqdz5Kjdlay1+NS1MUuXt7VTgn8ZW7zKHQ7CaVtdbPb+bKqdplRodKPvk6o 86F4AzzXyfoHIF31YzF5xd69p30c98l0doc3BKjfGHqFxtODigITpWivytpsMaRiWJWz0z FFQwUqYlBhixWmOk4vdCpxvpZ1Ya7BCquImhenPmtO7D53O1owgl1dXjhE5WjtFsX0kKr9 xubuHN5VIy9PBCC5Lr0yr8dnq7AXZ/wo2MLlElJDGQuZMw/r2W/eFw+CTmwW3w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578058; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RRSX54I0iJeSrYG1pJupkqNr+r3Vka+Wq09nGaVn1Sg=; b=3Vs7OAVxiNn+RgHe9I/qcRVk3kqvV8Blj9W/EXBitKkHP11n85dxywX95w3GiFV7N11qc3 lpCJAkUUm6NA3nCA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 59/90] KVM: x86/pmu: Use standard CPUID(0xa) types Date: Fri, 27 Mar 2026 03:16:13 +0100 Message-ID: <20260327021645.555257-60-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For KVM PMU refresh, use the auto-generated CPUID(0xa) types from x86-cpuid-db instead of relying on the custom perf types. The latter types are in process of getting removed from the kernel. Signed-off-by: Ahmed S. Darwish --- arch/x86/kvm/vmx/pmu_intel.c | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 74e0b01185b8..e0aeb1bc04ca 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -493,8 +493,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); struct lbr_desc *lbr_desc =3D vcpu_to_lbr_desc(vcpu); struct kvm_cpuid_entry2 *entry; - union cpuid10_eax eax; - union cpuid10_edx edx; + struct leaf_0xa_0 l =3D { }; + struct cpuid_regs *regs =3D (struct cpuid_regs *)&l; u64 perf_capabilities; u64 counter_rsvd; =20 @@ -515,21 +515,18 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) if (!entry) return; =20 - eax.full =3D entry->eax; - edx.full =3D entry->edx; + regs->eax =3D entry->eax; + regs->edx =3D entry->edx; =20 - pmu->version =3D eax.split.version_id; + pmu->version =3D l.pmu_version; if (!pmu->version) return; =20 - pmu->nr_arch_gp_counters =3D min_t(int, eax.split.num_counters, - kvm_pmu_cap.num_counters_gp); - eax.split.bit_width =3D min_t(int, eax.split.bit_width, - kvm_pmu_cap.bit_width_gp); - pmu->counter_bitmask[KVM_PMC_GP] =3D BIT_ULL(eax.split.bit_width) - 1; - eax.split.mask_length =3D min_t(int, eax.split.mask_length, - kvm_pmu_cap.events_mask_len); - pmu->available_event_types =3D ~entry->ebx & (BIT_ULL(eax.split.mask_leng= th) - 1); + pmu->nr_arch_gp_counters =3D min_t(int, l.num_counters_gp, kvm_pmu_cap.nu= m_counters_gp); + l.bit_width_gp =3D min_t(int, l.bit_width_gp, kvm_pmu_cap.bit_width_gp); + pmu->counter_bitmask[KVM_PMC_GP]=3D BIT_ULL(l.bit_width_gp) - 1; + l.events_mask_len =3D min_t(int, l.events_mask_len, kvm_pmu_cap.events_m= ask_len); + pmu->available_event_types =3D ~entry->ebx & (BIT_ULL(l.events_mask_len) = - 1); =20 entry =3D kvm_find_cpuid_entry_index(vcpu, 7, 0); if (entry && @@ -552,11 +549,9 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) if (pmu->version =3D=3D 1) return; =20 - pmu->nr_arch_fixed_counters =3D min_t(int, edx.split.num_counters_fixed, - kvm_pmu_cap.num_counters_fixed); - edx.split.bit_width_fixed =3D min_t(int, edx.split.bit_width_fixed, - kvm_pmu_cap.bit_width_fixed); - pmu->counter_bitmask[KVM_PMC_FIXED] =3D BIT_ULL(edx.split.bit_width_fixed= ) - 1; + pmu->nr_arch_fixed_counters =3D min_t(int, l.num_counters_fixed, kvm_pmu_= cap.num_counters_fixed); + l.bitwidth_fixed =3D min_t(int, l.bitwidth_fixed, kvm_pmu_cap.bit_wid= th_fixed); + pmu->counter_bitmask[KVM_PMC_FIXED] =3D BIT_ULL(l.bitwidth_fixed) - 1; =20 intel_pmu_enable_fixed_counter_bits(pmu, INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER | --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6A3D376494 for ; Fri, 27 Mar 2026 02:21:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578064; cv=none; b=eksT5nbkWrJSdJOMm1DmQX0iUthB/wlgqzfX+kk4S7Ib4BVtKpN2/hgynZ1bsw/Z9rBqQZDIW7t0IuXwpuOPBguSM9p2/zn0LcRED4EGJ/IxbT407Q2PiBf5+E7joBy6gH5XOG397+EDKkK66MmpxuJU0d3ARBOn38jic4ryvrY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578064; c=relaxed/simple; bh=awt4vDKLa+dZzD0JnYQUd+M29kbqPaZBhBkngUKqw3g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UnuL1BDM9Myl6JaJFMm31DdFr1yWbpHdXq9m2gE9i+c/4OsucVBGyebfjmBGvSWbPVv8El97nxCoKGnSyVOo55Bbg34kQkcc5zCJ3tyThxM05hjfawBwt1e+4+5dXpCn24Ou1lI1jIcZ2zciA5BI+6KLoSH5kPj1KKYDpuu0GAc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=tAwC5V8D; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dxEENZ3d; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="tAwC5V8D"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dxEENZ3d" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578061; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+jZw9ggKxdfGR6G92KBvWwxNqVjS1wEIWq4sUfAWwxo=; b=tAwC5V8DFUd8g1pZaeO1zQ3zIhlsDr5mqPOx4zNmaT+5XFX0pDaW/d4y15jOWxvSC1edUH BpZvFFu5NAmtj9OSZqTswYbzaNWNBWV2BCMeKZryKaLXe2KQLxSu9La5W8JCabBX9clhNd J0FM19Ch+Vb4MV0r0zOs0eoPMrkFYA1pd69ovbnxWdgHSJI+1OruwDmoRK3pQQ9QaJEqCq tvDl6zMfDy3STbpxN8DQA0eYZeaPy68nFT8IGeov8+1btxI52r0NETBZH0peN1xN9LBUz9 MD8U6ZAE4UNbM+BGFp/1LDLyEr9CRm3fIa3bQgpR+h8iMz5z8fx1vFg739ibQQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578061; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+jZw9ggKxdfGR6G92KBvWwxNqVjS1wEIWq4sUfAWwxo=; b=dxEENZ3d8HrkT8MbLszr5n1n75EGU0r4qkmdhjNic1nbZp+2hoCtXnwe6be3UhhxrV6ehv 2UF6OK78hpic4iCw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 60/90] perf/x86: Remove custom CPUID(0xa) types Date: Fri, 27 Mar 2026 03:16:14 +0100 Message-ID: <20260327021645.555257-61-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All CPUID(0xa) sites have been transformed from direct CPUID queries to the CPUID parser APIs. Pure users of perf's custom CPUID(0xa) types have also been converted to the auto generated x86-cpuid-db data types. Remove the now-unused CPUID(0xa) types from . Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/perf_event.h | 38 ------------------------------- 1 file changed, 38 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index ff5acb8b199b..23caaba1e104 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -157,44 +157,6 @@ /* Steal the highest bit of pebs_data_cfg for SW usage */ #define PEBS_UPDATE_DS_SW BIT_ULL(63) =20 -/* - * Intel "Architectural Performance Monitoring" CPUID - * detection/enumeration details: - */ -union cpuid10_eax { - struct { - unsigned int version_id:8; - unsigned int num_counters:8; - unsigned int bit_width:8; - unsigned int mask_length:8; - } split; - unsigned int full; -}; - -union cpuid10_ebx { - struct { - unsigned int no_unhalted_core_cycles:1; - unsigned int no_instructions_retired:1; - unsigned int no_unhalted_reference_cycles:1; - unsigned int no_llc_reference:1; - unsigned int no_llc_misses:1; - unsigned int no_branch_instruction_retired:1; - unsigned int no_branch_misses_retired:1; - } split; - unsigned int full; -}; - -union cpuid10_edx { - struct { - unsigned int num_counters_fixed:5; - unsigned int bit_width_fixed:8; - unsigned int reserved1:2; - unsigned int anythread_deprecated:1; - unsigned int reserved2:16; - } split; - unsigned int full; -}; - /* * Intel "Architectural Performance Monitoring extension" CPUID * detection/enumeration details: --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1A7D376BEC for ; Fri, 27 Mar 2026 02:21:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578068; cv=none; b=QdTboQx8KiazwdLMaTyYgM+75LR6WW3/3LwbHTWKPhxWgo8i6FCzeXIsR4UE/2UyqBq1ZJsiywqh02TKupdqWxvpmve7pIbiaUmf7X1ZZzqNUUAJ/LtwD10q9bt7HgIK16rhy4OlNbyElKHcCfo1YK2r/gt76xYs5Osi/Naq2vY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578068; c=relaxed/simple; bh=CJIqPe48oi83NtLflCwO7pRjDo23buF+R/95EVAg8Fc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Au1XUd84ZMYaPhTNkShCrLxy3tvm1U8F1mBTLAK1RVHS3+SuZUI44GGIn4bK6h52B7+Yp/HDcBjNs7+ykMHELrOrqbsRn/plsw0SdGajjkhow3GjFd9NpzmQAGllyF34h0XVh9nCLAjqxlNYem4pT8RUif7W0jl/JGaVMiBnvAk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4vt1yFai; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+AyGi/Az; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4vt1yFai"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+AyGi/Az" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578064; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hcl3gDDxvBw76pQpHh0N5lzLkbf3ZnbbNEuPzu4azcY=; b=4vt1yFaiU/s7xV6FS+UNVjKIUS8di3FFlF/aBNYZqxjVwtN2tQeoFIdjScKoP8VE9QIuoR ROc1raxDvYlssOeFLxhKxrB3XQeO16HsNUmVqvJJCVrIb/Kr+z5vm9W3l+IVcfQXBACqyN SbDz2Wm9m53pZyK0z6v3bcbOEWxQuYc6masvcHIj6JjfFaR96PRKPi1XdCgKLeyHfwKcBB 1zroaAGtV85QDSK/zGSd3q0gFKXw8Szzd1dqrrgkYsRkvedID+pLHtWIsiTVKVfEc3T5Or oHAtwHVoPyFq9XVApOn5yrbZePpAnlu/ZzAjahHvAvju/rWVl/YhxRdKhyuvTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578064; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hcl3gDDxvBw76pQpHh0N5lzLkbf3ZnbbNEuPzu4azcY=; b=+AyGi/AzlDxJiNhKOYr0UjiPx0PpVTf8joGQndBpP+rWTjM+K2aAX956d5aHsxY2QVmZrS d5bLFvRqwuBUi+CQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 61/90] perf/x86/lbr: Use parsed CPUID(0x1c) Date: Fri, 27 Mar 2026 03:16:15 +0100 Message-ID: <20260327021645.555257-62-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x1c) instead of a direct CPUID query and custom perf CPUID(0x1c) data types. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/intel/lbr.c | 33 +++++++++++++++------------------ 1 file changed, 15 insertions(+), 18 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index cae2e02fe6cc..7bc48f5e5e52 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1587,19 +1587,16 @@ static bool is_arch_lbr_xsave_available(void) =20 void __init intel_pmu_arch_lbr_init(void) { + const struct leaf_0x1c_0 *l =3D cpuid_leaf(&boot_cpu_data, 0x1c); struct pmu *pmu =3D x86_get_pmu(smp_processor_id()); - union cpuid28_eax eax; - union cpuid28_ebx ebx; - union cpuid28_ecx ecx; - unsigned int unused_edx; bool arch_lbr_xsave; size_t size; u64 lbr_nr; =20 - /* Arch LBR Capabilities */ - cpuid(28, &eax.full, &ebx.full, &ecx.full, &unused_edx); + if (!l) + goto clear_arch_lbr; =20 - lbr_nr =3D fls(eax.split.lbr_depth_mask) * 8; + lbr_nr =3D fls(l->lbr_depth_mask) * 8; if (!lbr_nr) goto clear_arch_lbr; =20 @@ -1607,17 +1604,17 @@ void __init intel_pmu_arch_lbr_init(void) if (wrmsrq_safe(MSR_ARCH_LBR_DEPTH, lbr_nr)) goto clear_arch_lbr; =20 - x86_pmu.lbr_depth_mask =3D eax.split.lbr_depth_mask; - x86_pmu.lbr_deep_c_reset =3D eax.split.lbr_deep_c_reset; - x86_pmu.lbr_lip =3D eax.split.lbr_lip; - x86_pmu.lbr_cpl =3D ebx.split.lbr_cpl; - x86_pmu.lbr_filter =3D ebx.split.lbr_filter; - x86_pmu.lbr_call_stack =3D ebx.split.lbr_call_stack; - x86_pmu.lbr_mispred =3D ecx.split.lbr_mispred; - x86_pmu.lbr_timed_lbr =3D ecx.split.lbr_timed_lbr; - x86_pmu.lbr_br_type =3D ecx.split.lbr_br_type; - x86_pmu.lbr_counters =3D ecx.split.lbr_counters; - x86_pmu.lbr_nr =3D lbr_nr; + x86_pmu.lbr_depth_mask =3D l->lbr_depth_mask; + x86_pmu.lbr_deep_c_reset =3D l->lbr_deep_c_reset; + x86_pmu.lbr_lip =3D l->lbr_ip_is_lip; + x86_pmu.lbr_cpl =3D l->lbr_cpl; + x86_pmu.lbr_filter =3D l->lbr_branch_filter; + x86_pmu.lbr_call_stack =3D l->lbr_call_stack; + x86_pmu.lbr_mispred =3D l->lbr_mispredict; + x86_pmu.lbr_timed_lbr =3D l->lbr_timed_lbr; + x86_pmu.lbr_br_type =3D l->lbr_branch_type; + x86_pmu.lbr_counters =3D l->lbr_events_gpc_bmp; + x86_pmu.lbr_nr =3D lbr_nr; =20 if (!!x86_pmu.lbr_counters) x86_pmu.flags |=3D PMU_FL_BR_CNTR | PMU_FL_DYN_CONSTRAINT; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C49CC374195 for ; Fri, 27 Mar 2026 02:21:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578071; cv=none; b=Hf3t4Oh41JDvu4Xk6mj4L9iT2GwclfCUwz52nVlERRqDe8JI9/7F6WCYatQTq778l86fQ34QNxXf8kLlzRgMPd7S4MSc8IIwBNZfNKNoaISOhvEu1Bo1YLZjbe/mggFrvAzhZNfyeA015qGJrckIYU7wL6bJzSxaEmuej6w+a84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578071; c=relaxed/simple; bh=/vmDMB+L3FRPtQ4smBMI2MOUa7QWhvNRgCd/t0kYw9k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uNZ3yqxpWaUv5xKxg2dYRlkxPE2MUlYSbDTI5/m3owi5+fBwwtXf1kp1Gvc0mSkGOaaamC1bQiBC1XlDMp+g8exFvjVuRC7C+0oFRJYYUmTumUY9rytBYEwhNkfhKjVeu0xT/M/UB12/9Oj/HvKNsRIQ9o0aZBznll+jjPO3eKg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PlUjyTUR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KfRgFMOs; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PlUjyTUR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KfRgFMOs" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578067; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5NWyRVRvUH7gWmoFCLBiZjxEncoEsNggR0XVPdkNM7E=; b=PlUjyTUR3SXL+keg+FwwO+scXXwSU+Sn/fFJ0u/LKvtGqJcyQD4ha/glABARJC40iIzn+r LaADSUgc/8cOn6BKFT7VuJuo0Bm5ieCa+kKpT1OLVXfDPyy/JV825I4FgMi4Aola02/KId 1XIowq51veOrPCX64O43Op5wXpaCgjoMseambRcBHiTo334bXCa+BQnZiYadFCz2Bi/aGm TqPhGSNaxsoGLrff8twW86iCMzOfDEcwt/353rDqZ1WaaHdvUmDUmbm+SOMAPYYh3tsk3Y 9N6bpn0IDtzOfYQIypluxdt2hKEm+YQPi4oESc51f2lfz/i4QXq4dv6LIfgvmQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578067; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5NWyRVRvUH7gWmoFCLBiZjxEncoEsNggR0XVPdkNM7E=; b=KfRgFMOsiZ6mXMUjOTsxlVCYrrrRICGAK50x/g05XxnlL0GRWNj8YJPlpSOUSlQSwbhtGM TR6pZ0tsa5/Kh5Ag== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 62/90] perf/x86/lbr: Remove custom CPUID(0x1c) types Date: Fri, 27 Mar 2026 03:16:16 +0100 Message-ID: <20260327021645.555257-63-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All CPUID(0x1c) call sites have been converted from direct CPUID queries to the CPUID API and its x86-cpuid-db auto generated types. Remove the custom CPUID(0x1c) types from . Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/perf_event.h | 43 ------------------------------- 1 file changed, 43 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 23caaba1e104..c57e6c9231aa 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -197,49 +197,6 @@ union cpuid35_ebx { unsigned int full; }; =20 -/* - * Intel Architectural LBR CPUID detection/enumeration details: - */ -union cpuid28_eax { - struct { - /* Supported LBR depth values */ - unsigned int lbr_depth_mask:8; - unsigned int reserved:22; - /* Deep C-state Reset */ - unsigned int lbr_deep_c_reset:1; - /* IP values contain LIP */ - unsigned int lbr_lip:1; - } split; - unsigned int full; -}; - -union cpuid28_ebx { - struct { - /* CPL Filtering Supported */ - unsigned int lbr_cpl:1; - /* Branch Filtering Supported */ - unsigned int lbr_filter:1; - /* Call-stack Mode Supported */ - unsigned int lbr_call_stack:1; - } split; - unsigned int full; -}; - -union cpuid28_ecx { - struct { - /* Mispredict Bit Supported */ - unsigned int lbr_mispred:1; - /* Timed LBRs Supported */ - unsigned int lbr_timed_lbr:1; - /* Branch Type Field Supported */ - unsigned int lbr_br_type:1; - unsigned int reserved:13; - /* Branch counters (Event Logging) Supported */ - unsigned int lbr_counters:4; - } split; - unsigned int full; -}; - /* * AMD "Extended Performance Monitoring and Debug" CPUID * detection/enumeration details: --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1916B3783C6 for ; Fri, 27 Mar 2026 02:21:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578074; cv=none; b=PUMtLm0N4Oif4Q5Q1IPZuyW2RcKQ1njLUrO0z+twCxYQWeH0IunOBD2VgS4hbdJcITQ2Qzb1KuS6e3tSi+fKWpnedqfuC09nVg0dW+dWoI/6W5KO2fd3G/RNclDoEnMiH+12ob/31mA2ICw4OL9Zh/5vpdp3vaAEnyk3prIsOGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578074; c=relaxed/simple; bh=tW/ye2TBeMZi7c6e3HS6fnB8SzvWqScXJI8Vhy63PcA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iBOheUh9m9wjzElnD7MBy+S7qp2geon7WeIgMhbwRRWCQULNx+btPrdfoGe6gCZJftdPjxFc5eQMJaBnqMP0Pdisnf+v1byPK5URnuVKYXhpB18UK5KLloxMI4IY6LbmaIjinz0kzqcYVzBe7vATNcC8d59XDLXMbLDWYhU7SJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fV+nRaBH; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DUxyMIrB; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fV+nRaBH"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DUxyMIrB" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578071; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X3dI8J71LJ843q3U4uIyu1o3PcnILttF5OS2RDvZ59c=; b=fV+nRaBH1cOoM3h3VoMD2IMIs3IMYiOJfZ3njlNWAFMAKldYDZgN0Wsa6X09zN18yGu7Ex aZXnTj9qpTh78jmgzZb6PBf2+6zj+ecsIsRwMZ4XzBgBOaWkLKH/rKOOQpJU7RMcF/dr2V PphaM0ZjFjaBF5syyWjtPDyL6aF/vXhu7osnL0ZLtRZrB9fnr13HBxeDgy9vxZyEwKbwu+ rfG2fEQT/EyGkYb1mLXLqtmgRWzWYhQg7hi/SztDOauT/wUfqdJ5s7sEBmtK75cpPAp5Y4 qpgUEhqLYfU30fQ5E1YDbliLe+Uaf0mFszKjM2k4L08wwLegKJcaM8Kd04hDjg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578071; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=X3dI8J71LJ843q3U4uIyu1o3PcnILttF5OS2RDvZ59c=; b=DUxyMIrBTAUYKpyWiVDI1hC3AyGqV+B9NJxEsWaTIb65yfElxslaR/aHYnjE/v1mfsYCBp kIsx63f/LU1Y9zDA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 63/90] x86/cpuid: Parse CPUID(0x23) Date: Fri, 27 Mar 2026 03:16:17 +0100 Message-ID: <20260327021645.555257-64-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse Intel PMU CPUID(0x23), and all its known subleaves. This allows converting their call sites to the CPUID API next. Note, for all subleaves, make sure that subleaf 0 declares their support beforehand. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 6 +++++ arch/x86/kernel/cpu/cpuid_parser.c | 37 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 7 ++++++ 3 files changed, 50 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 128898d4434b..70ccd52a6848 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -215,6 +215,12 @@ struct cpuid_leaves { CPUID_LEAF ( 0xa, 0 ); CPUID_LEAF ( 0x1c, 0 ); CPUID_LEAF ( 0x16, 0 ); + CPUID_LEAF ( 0x23, 0 ); + CPUID_LEAF ( 0x23, 1 ); + CPUID_LEAF ( 0x23, 2 ); + CPUID_LEAF ( 0x23, 3 ); + CPUID_LEAF ( 0x23, 4 ); + CPUID_LEAF ( 0x23, 5 ); CPUID_LEAF ( 0x80000000, 0 ); CPUID_LEAF ( 0x80000002, 0 ); CPUID_LEAF ( 0x80000003, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 99507e99d8d9..de11fb4116f2 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -105,6 +105,43 @@ cpuid_read_0x2(const struct cpuid_parse_entry *e, cons= t struct cpuid_read_output */ define_cpuid_read_function(deterministic_cache, leaf_0x4_n, l, l->cache_ty= pe =3D=3D 0); =20 +static bool cpuid_0x23_has_subleaf(u32 subleaf) +{ + struct leaf_0x23_0 l; + + cpuid_read_subleaf(0x23, 0, &l); + + if (subleaf =3D=3D 1) + return l.counters_subleaf; + if (subleaf =3D=3D 2) + return l.acr_subleaf; + if (subleaf =3D=3D 3) + return l.events_subleaf; + if (subleaf =3D=3D 4) + return l.pebs_caps_subleaf; + if (subleaf =3D=3D 5) + return l.pebs_subleaf; + + return false; +} + +#define define_cpuid_0x23_subleaf_read_function(subl) \ +static void \ +cpuid_read_0x23_##subl(const struct cpuid_parse_entry *e, const struct cpu= id_read_output *output) \ +{ \ + if (!cpuid_0x23_has_subleaf(subl)) \ + return; \ + \ + cpuid_read_subleaf(e->leaf, e->subleaf, output->regs); \ + output->info->nr_entries =3D 1; \ +} + +define_cpuid_0x23_subleaf_read_function(1); +define_cpuid_0x23_subleaf_read_function(2); +define_cpuid_0x23_subleaf_read_function(3); +define_cpuid_0x23_subleaf_read_function(4); +define_cpuid_0x23_subleaf_read_function(5); + /* * Define an extended range CPUID read function * diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 8e147e7223e0..46f06792afb1 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -149,6 +149,12 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0xa, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x1c, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x16, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x23, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x23, 1, 0x23_1 ), \ + CPUID_PARSE_ENTRY ( 0x23, 2, 0x23_2 ), \ + CPUID_PARSE_ENTRY ( 0x23, 3, 0x23_3 ), \ + CPUID_PARSE_ENTRY ( 0x23, 4, 0x23_4 ), \ + CPUID_PARSE_ENTRY ( 0x23, 5, 0x23_5 ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ @@ -203,6 +209,7 @@ struct cpuid_vendor_entry { CPUID_VENDOR_ENTRY(0xa, X86_VENDOR_INTEL, X86_VENDOR_CENTAUR, X86_VENDOR= _ZHAOXIN),\ CPUID_VENDOR_ENTRY(0x16, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x1c, X86_VENDOR_INTEL), \ + CPUID_VENDOR_ENTRY(0x23, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ CPUID_VENDOR_ENTRY(0x80860000, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860001, X86_VENDOR_TRANSMETA), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2DE4A35CB66 for ; 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 64/90] perf/x86/intel: Use parsed per-CPU CPUID(0x23) Date: Fri, 27 Mar 2026 03:16:18 +0100 Message-ID: <20260327021645.555257-65-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Intel PMU capabilities, use parsed CPUID(0x23) instead of direct CPUID queries and custom perf CPUID(0x23) data types. Replace manual subleaves availability checks with checking whether the CPUID APIs return NULL. This is sufficient since the CPUID parser validates all the leaves and subleaves beforehand. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/intel/core.c | 62 +++++++++++++++++------------------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 20dece48b994..6eee7fbcef9e 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5891,51 +5891,49 @@ static inline void __intel_update_large_pebs_flags(= struct pmu *pmu) =20 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX= _FIXED)) =20 -static void update_pmu_cap(struct pmu *pmu) -{ - unsigned int eax, ebx, ecx, edx; - union cpuid35_eax eax_0; - union cpuid35_ebx ebx_0; +static void update_pmu_cap(struct pmu *pmu, int cpu) +{ + struct cpuinfo_x86 *cpuinfo =3D is_hybrid() ? &cpu_data(cpu) : &boot_cpu_= data; + const struct leaf_0x23_0 *sl0 =3D cpuid_subleaf(cpuinfo, 0x23, 0); + const struct leaf_0x23_1 *sl1 =3D cpuid_subleaf(cpuinfo, 0x23, 1); + const struct leaf_0x23_2 *sl2 =3D cpuid_subleaf(cpuinfo, 0x23, 2); + const struct leaf_0x23_4 *sl4 =3D cpuid_subleaf(cpuinfo, 0x23, 4); + const struct leaf_0x23_5 *sl5 =3D cpuid_subleaf(cpuinfo, 0x23, 5); + u64 pdists_mask =3D 0; u64 cntrs_mask =3D 0; u64 pebs_mask =3D 0; - u64 pdists_mask =3D 0; =20 - cpuid(ARCH_PERFMON_EXT_LEAF, &eax_0.full, &ebx_0.full, &ecx, &edx); + if (!sl0) + return; =20 - if (ebx_0.split.umask2) + if (sl0->unitmask2) hybrid(pmu, config_mask) |=3D ARCH_PERFMON_EVENTSEL_UMASK2; - if (ebx_0.split.eq) + if (sl0->eq) hybrid(pmu, config_mask) |=3D ARCH_PERFMON_EVENTSEL_EQ; - if (ebx_0.split.rdpmc_user_disable) + if (sl0->rdpmc_user_disable) hybrid(pmu, config_mask) |=3D ARCH_PERFMON_EVENTSEL_RDPMC_USER_DISABLE; =20 - if (eax_0.split.cntr_subleaf) { - cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_NUM_COUNTER_LEAF, - &eax, &ebx, &ecx, &edx); - hybrid(pmu, cntr_mask64) =3D eax; - hybrid(pmu, fixed_cntr_mask64) =3D ebx; - cntrs_mask =3D counter_mask(eax, ebx); + if (sl1) { + hybrid(pmu, cntr_mask64) =3D sl1->gp_counters; + hybrid(pmu, fixed_cntr_mask64) =3D sl1->fixed_counters; + cntrs_mask =3D counter_mask(sl1->gp_counters, sl1->fixed_counters); } =20 - if (eax_0.split.acr_subleaf) { - cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_ACR_LEAF, - &eax, &ebx, &ecx, &edx); + if (sl2) { /* The mask of the counters which can be reloaded */ - hybrid(pmu, acr_cntr_mask64) =3D counter_mask(eax, ebx); + hybrid(pmu, acr_cntr_mask64) =3D counter_mask(sl2->acr_gp_reload, sl2->a= cr_fixed_reload); /* The mask of the counters which can cause a reload of reloadable count= ers */ - hybrid(pmu, acr_cause_mask64) =3D counter_mask(ecx, edx); + hybrid(pmu, acr_cause_mask64) =3D counter_mask(sl2->acr_gp_trigger, sl2-= >acr_fixed_trigger); } =20 - /* Bits[5:4] should be set simultaneously if arch-PEBS is supported */ - if (eax_0.split.pebs_caps_subleaf && eax_0.split.pebs_cnts_subleaf) { - cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_CAP_LEAF, - &eax, &ebx, &ecx, &edx); - hybrid(pmu, arch_pebs_cap).caps =3D (u64)ebx << 32; + /* Both subleaves should be available if arch-PEBS is supported */ + if (sl4 && sl5) { + const struct cpuid_regs *sl4_regs =3D (const struct cpuid_regs *)sl4; + + hybrid(pmu, arch_pebs_cap).caps =3D (u64)sl4_regs->ebx << 32; =20 - cpuid_count(ARCH_PERFMON_EXT_LEAF, ARCH_PERFMON_PEBS_COUNTER_LEAF, - &eax, &ebx, &ecx, &edx); - pebs_mask =3D counter_mask(eax, ecx); - pdists_mask =3D counter_mask(ebx, edx); + pebs_mask =3D counter_mask(sl5->pebs_gp, sl5->pebs_fixed); + pdists_mask =3D counter_mask(sl5->pebs_pdist_gp, sl5->pebs_pdist_fixed); hybrid(pmu, arch_pebs_cap).counters =3D pebs_mask; hybrid(pmu, arch_pebs_cap).pdists =3D pdists_mask; =20 @@ -6038,7 +6036,7 @@ static bool init_hybrid_pmu(int cpu) goto end; =20 if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) - update_pmu_cap(&pmu->pmu); + update_pmu_cap(&pmu->pmu, cpu); =20 intel_pmu_check_hybrid_pmus(pmu); =20 @@ -8452,7 +8450,7 @@ __init int intel_pmu_init(void) * when a new type is online. */ if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) - update_pmu_cap(NULL); + update_pmu_cap(NULL, 0); =20 if (x86_pmu.arch_pebs) { static_call_update(intel_pmu_disable_event_ext, --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F75C378D9F for ; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578078; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pr0cNu6rZmuw9gMObI8KBiaV8/2gOXHSOkaRxwPz7dM=; b=wnkfb0yWx/AUKCELwUGwON8wPGi7Dzoye7W1qZGl2wtcWzzo5dg8BSM/TLAraj2d39rRIa x0x33xI/mA0Igo8cd3G3tT6R6WYTGZUFI/QUAcxEr4OTbWh7jt5NOKKq8XM6/tvdhwAv7C 35GzQLOTnw43skUit5t1jJ7UmoQvDaC0Z4lXP7ob/+rt49LlsjrdWKEEjxTERpdO864FQU aR8vAIje3kyjpgPVwtTOHb8ko4G06IqM9VhyU7EkvtcdH4jj4L7Z4iEQhMoty0drD61/wE Z1I1zpuJB3goijxPwMVFFUDbDLysSpq6g67lZVQbk64Ke6w3askt2sSjc81nVg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578078; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Pr0cNu6rZmuw9gMObI8KBiaV8/2gOXHSOkaRxwPz7dM=; b=Tzeho6t0rWIZDvjkavr9WK1DRJs0XNBdRz9GdkqHQ95njCJkxsZX3eVGuerMDOOcXhhiUP SrJD7Ph6m8+N3rAw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 65/90] perf/x86/intel: Remove custom CPUID(0x23) types Date: Fri, 27 Mar 2026 03:16:19 +0100 Message-ID: <20260327021645.555257-66-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All CPUID(0x23) call sites have been converted to the CPUID API and its auto generated x86-cpuid-db data types. Remove the custom CPUID(0x23) types from perf. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/perf_event.h | 38 +------------------------------ 1 file changed, 1 insertion(+), 37 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index c57e6c9231aa..5aa07710af12 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -157,46 +157,10 @@ /* Steal the highest bit of pebs_data_cfg for SW usage */ #define PEBS_UPDATE_DS_SW BIT_ULL(63) =20 -/* - * Intel "Architectural Performance Monitoring extension" CPUID - * detection/enumeration details: - */ -#define ARCH_PERFMON_EXT_LEAF 0x00000023 -#define ARCH_PERFMON_NUM_COUNTER_LEAF 0x1 -#define ARCH_PERFMON_ACR_LEAF 0x2 +// _CPUID_TODO_: Remove subleaf 4 and 5 after defining them #define ARCH_PERFMON_PEBS_CAP_LEAF 0x4 #define ARCH_PERFMON_PEBS_COUNTER_LEAF 0x5 =20 -union cpuid35_eax { - struct { - unsigned int leaf0:1; - /* Counters Sub-Leaf */ - unsigned int cntr_subleaf:1; - /* Auto Counter Reload Sub-Leaf */ - unsigned int acr_subleaf:1; - /* Events Sub-Leaf */ - unsigned int events_subleaf:1; - /* arch-PEBS Sub-Leaves */ - unsigned int pebs_caps_subleaf:1; - unsigned int pebs_cnts_subleaf:1; - unsigned int reserved:26; - } split; - unsigned int full; -}; - -union cpuid35_ebx { - struct { - /* UnitMask2 Supported */ - unsigned int umask2:1; - /* EQ-bit Supported */ - unsigned int eq:1; - /* rdpmc user disable Supported */ - unsigned int rdpmc_user_disable:1; - unsigned int reserved:29; - } split; - unsigned int full; -}; - /* * AMD "Extended Performance Monitoring and Debug" CPUID * detection/enumeration details: --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6675C37A481 for ; Fri, 27 Mar 2026 02:21:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578083; cv=none; b=Wj0lAhNzuWpG7TRW6v4D5278AIellYzSZRVhTID55aVSAfmozGCU2vD+b7ehU7D1Z0mzYucVAk4sniE72WgXqelknbLQEXnD6JyXrxri8kdDvlLvclwCU4tqNJeyBjl76CN3oGptsmnT6AJ3kS/8Bh0NoJSKYN6hXs+wkYaSgzg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578083; c=relaxed/simple; bh=r3JSn1+HEA3ajw2VPnamJpdfIFaiDQcAloOf66/dtKQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JHKRIYoBG3Qg42godz9kI8v/drG4GIK4tpzTk7kIgsZLKeNkYOeczYeARCnMsi1Ph5upbD0ssz7vo/D+An1Ot/lV11n09JV3LC3HCvFWQqtbWkZr7FxwQqR3L4qScUmhXI8HfQA8edD/Scl5Z6LIIaX89Gl8mIMGaMKlKwWYD7U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=sAxtdWOr; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QAscarOZ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="sAxtdWOr"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QAscarOZ" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ppk0/jYqr8dqJV5JRSY9GhFkYl4GLYVf87y+tfWguGA=; b=sAxtdWOrbxEJ/sDf5uJu4OkO1AUbGEBaZKGDkwBOh+3LpVGjTqueaD8PzuLqBFOITb6NVo N/+cFBUkG8MZ4NSp0Aek8t9+pj9A6ktfyX+RUCiu5+SVtVvn1ZHJCs0cMJBeqkhGwRrMss +qWfxw2ZEaMvITheeS+PvtbqAeE4fM3OFYLSKDddtviAyMmLgiaAaLbc+Xsqif/T3NLs31 mqEUBjxHmoQZ6NkZxIsU2O9mlyP/KqUj3fb+4ZcK6N7ZCsACVIPoQv8zBwQ/toxRzGXPkG O614HylantsZxE2EjgOemy2P9MoiX0fihPFEtoijzT8I+BZWwMoW49bAZGbuVw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578081; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ppk0/jYqr8dqJV5JRSY9GhFkYl4GLYVf87y+tfWguGA=; b=QAscarOZHSqpa3rWbeEgJB4sbkQtj+aGTqwDCvVo19rdLWwobKOO87rtQTLIJKxUFvkxSf MRkd3c9ERSgPPBAg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 66/90] x86/cpuid: Parse CPUID(0x80000022) Date: Fri, 27 Mar 2026 03:16:20 +0100 Message-ID: <20260327021645.555257-67-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse CPUID(0x80000022). Add AMD and Hygon vendor tags as it is only supported on these CPUs. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 70ccd52a6848..deddb534486a 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -229,6 +229,7 @@ struct cpuid_leaves { CPUID_LEAF ( 0x80000006, 0 ); CPUID_LEAF ( 0x80000008, 0 ); CPUID_LEAF_N ( 0x8000001d, 8 ); + CPUID_LEAF ( 0x80000022, 0 ); CPUID_LEAF ( 0x80860000, 0 ); CPUID_LEAF ( 0x80860001, 0 ); CPUID_LEAF ( 0x80860002, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 46f06792afb1..59a4d562320a 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -163,6 +163,7 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x80000006, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000008, 0, generic ), \ CPUID_PARSE_ENTRY_N ( 0x8000001d, deterministic_cache ), \ + CPUID_PARSE_ENTRY ( 0x80000022, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80860000, 0, 0x80860000 ), \ CPUID_PARSE_ENTRY ( 0x80860001, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80860002, 0, generic ), \ @@ -211,6 +212,7 @@ struct cpuid_vendor_entry { CPUID_VENDOR_ENTRY(0x1c, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x23, X86_VENDOR_INTEL), \ CPUID_VENDOR_ENTRY(0x8000001d, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ + CPUID_VENDOR_ENTRY(0x80000022, X86_VENDOR_AMD, X86_VENDOR_HYGON), \ CPUID_VENDOR_ENTRY(0x80860000, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860001, X86_VENDOR_TRANSMETA), \ CPUID_VENDOR_ENTRY(0x80860002, X86_VENDOR_TRANSMETA), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 948362DB79E for ; Fri, 27 Mar 2026 02:21:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578087; cv=none; b=EF9Rynta5LbexMBRnYm0Wu1qEt5HSnUqGXat3UPPkNAcLGFMjVcnNoBa2f9twQ0A5JPqsVZDo/0D3/ULn6VVm5Tx7UYsxkfnHyE99uItlMAEnF2rgBlJWVUU76EhH/6x4zYwJDyK+4b3fN2lferav95LaK4ZIlZON64Pm0JSAJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578087; c=relaxed/simple; bh=WNmKYoGGoPfX72KFu74LUhADohB7bAZtY3qMpGuIF3E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PqH0hMRh5TMARy4QdhvHdBHhFsyrpxe0qTMIKVg0VCIqlR4ob+jLqemzva6GwS1aC6XKOwUrddAS0+I46oNYkZllDEgvqfzhuAmabEEq5YK5bjXBAiRtPTToxzcjyJeqzQ+Mb2Rd4JMJhE6hrMJ4yQcFT382i4WodCY0nn/MQRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=L0nRVqyO; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2iOZ7lmQ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="L0nRVqyO"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2iOZ7lmQ" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578084; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dkD/CBmTA4DS7GEldcH6eyTvx2dawK8VgeuDCIh2ZeA=; b=L0nRVqyOG348X8A1b9tXahvrWwNzW/SVNeWpK67GPa+2eLttMJDfrGMpa7YtRG33dXDNQ0 qwiGjPSEGMO6mBLojcNBvjO1tUj1dcRhnlbsVHA4KMG1RUgSpV98TBoIFktsAYKlxuPDSx xY+/EmTDGkdo1urBCOARgCo/ImEf7GJu97OStwoKC5DpZyH7LCQZh6ExBJ1vsmrmAJNh9r HdsSmbC+oHhzVtHyNlzZhacGEmymdpFFFV6LPzlU1o3nyxayJM7AO6nKkWt/yrt/qzc8Bg 2aOjKC+cQNF0Lpt2Ax4LCXFxsIPfXrjXBoAAIAB+JPDfy5h2tGSK2E9+uw64RA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578084; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dkD/CBmTA4DS7GEldcH6eyTvx2dawK8VgeuDCIh2ZeA=; b=2iOZ7lmQyl9TIDES0vPSUVUr1hhMZBtLoBeBteqnx8apr3HzNVICQyzDk6ggHEbuE0/rFC u8M+Pvv3V+G2A0BQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 67/90] perf/x86/amd/lbr: Use parsed CPUID(0x80000022) Date: Fri, 27 Mar 2026 03:16:21 +0100 Message-ID: <20260327021645.555257-68-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD LBR, use parsed CPUID(0x80000022) instead of a direct CPUID query and custom perf data types. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/amd/lbr.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/amd/lbr.c b/arch/x86/events/amd/lbr.c index 5b437dc8e4ce..e5a16266545f 100644 --- a/arch/x86/events/amd/lbr.c +++ b/arch/x86/events/amd/lbr.c @@ -423,14 +423,13 @@ void amd_pmu_lbr_disable_all(void) =20 __init int amd_pmu_lbr_init(void) { - union cpuid_0x80000022_ebx ebx; + const struct leaf_0x80000022_0 *l =3D cpuid_leaf(&boot_cpu_data, 0x800000= 22); =20 - if (x86_pmu.version < 2 || !boot_cpu_has(X86_FEATURE_AMD_LBR_V2)) + if (!l || x86_pmu.version < 2 || !boot_cpu_has(X86_FEATURE_AMD_LBR_V2)) return -EOPNOTSUPP; =20 /* Set number of entries */ - ebx.full =3D cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); - x86_pmu.lbr_nr =3D ebx.split.lbr_v2_stack_sz; + x86_pmu.lbr_nr =3D l->lbr_v2_stack_size; =20 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr); =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2CCF34104B for ; Fri, 27 Mar 2026 02:21:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578092; cv=none; b=taoj8F6dl+NY+F/9uAGEwD+/It3YXTZgNCMO/3owynR1E8UBiZzNsX56DtZn4hm/MeGpqKIWNZpVIn5H/MvkoXI3c37dJKMxlYFUK3LkkceEPzwSVFDglukrPEeqoP/O39sUkYo/TztG7SMPnnXRJFoQ2uENVx9aKqJTnFTNUYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578092; c=relaxed/simple; bh=jwJAsg/Mm/RedOatvf87NqQGp+rab+N+tR0cooeewDg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kg0216MPEEIH2aM19XZh01Svi5sACaTGCXnO4exD9csWfHFO/mVx1a5RE2RK17o4b0XFnLo7/a7hJq2//vy5LxSGiLR/L80oXTOzJjaU9ZgZNg/dl9M/zxgQ+/2HQZGnMwDKxAssutOzXJGd7kw73IxCVjuGpePeqYWrk1lerOo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DUn6kq81; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=5dkeh7O7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DUn6kq81"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="5dkeh7O7" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CjD5PhWwawGbSqynH4dKNOfB+35Pn9sLrPtOZZ6jDpg=; b=DUn6kq81nxmpD/Ba8RJhpP6uPJD/eQLnwBoxxjMEy263JGWCIe3A7FFkxJFbDFqd+dDUTO i2IP/VzqdAA+igsVzsQgd2l2duyCaToqKbnMTCzK36qkafVTICZfrsCRsAp8SSwQB+YG2C 9g/wOdy9lmtt6tcwP2/e805OKyKXiitk+Y090em/YspmrMlmOPc++5HDrxGAElOnbdkmX8 9p0mAS5RmUIMAd0zDKnKOxtkwlIiXoimOyV0bW1MzO5x3Etsv72YJrjgkB3fyTIjK3n1u2 c7p/hKg3nvqnqF56brQZ6Xm4oKBv/D/pRNv57SakX+Ub4Ss7TpVhYDV8XmukCQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578088; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CjD5PhWwawGbSqynH4dKNOfB+35Pn9sLrPtOZZ6jDpg=; b=5dkeh7O7jgYucY1C/xo0IE+Tns0bvQzx+qnCiDtFKuY/dCBDVw4BVtMMg1pjcWRNrNjoC+ oVcYofkH1CFpauAg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 68/90] perf/x86/amd: Use parsed CPUID(0x80000022) Date: Fri, 27 Mar 2026 03:16:22 +0100 Message-ID: <20260327021645.555257-69-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD perf, use parsed CPUID(0x80000022) instead of direct CPUID queries and custom perf data types. For the uncore CPU hotplug callbacks, ensure that the correct per-CPU CPUID table is queried. Signed-off-by: Ahmed S. Darwish --- arch/x86/events/amd/core.c | 8 +++----- arch/x86/events/amd/uncore.c | 18 +++++++----------- 2 files changed, 10 insertions(+), 16 deletions(-) diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index d66a357f219d..b070d0be36c4 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -1410,7 +1410,7 @@ static const struct attribute_group *amd_attr_update[= ] =3D { =20 static int __init amd_core_pmu_init(void) { - union cpuid_0x80000022_ebx ebx; + const struct leaf_0x80000022_0 *leaf =3D cpuid_leaf(&boot_cpu_data, 0x800= 00022); u64 even_ctr_mask =3D 0ULL; int i; =20 @@ -1430,14 +1430,12 @@ static int __init amd_core_pmu_init(void) x86_pmu.cntr_mask64 =3D GENMASK_ULL(AMD64_NUM_COUNTERS_CORE - 1, 0); =20 /* Check for Performance Monitoring v2 support */ - if (boot_cpu_has(X86_FEATURE_PERFMON_V2)) { - ebx.full =3D cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); - + if (leaf && boot_cpu_has(X86_FEATURE_PERFMON_V2)) { /* Update PMU version for later usage */ x86_pmu.version =3D 2; =20 /* Find the number of available Core PMCs */ - x86_pmu.cntr_mask64 =3D GENMASK_ULL(ebx.split.num_core_pmc - 1, 0); + x86_pmu.cntr_mask64 =3D GENMASK_ULL(leaf->n_pmc_core - 1, 0); =20 amd_pmu_global_cntr_mask =3D x86_pmu.cntr_mask64; =20 diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c index 05cff39968ec..6a5d8f8cfbc0 100644 --- a/arch/x86/events/amd/uncore.c +++ b/arch/x86/events/amd/uncore.c @@ -692,7 +692,7 @@ static int amd_uncore_df_add(struct perf_event *event, = int flags) static void amd_uncore_df_ctx_scan(struct amd_uncore *uncore, unsigned int cpu) { - union cpuid_0x80000022_ebx ebx; + const struct leaf_0x80000022_0 *leaf =3D cpuid_leaf(&cpu_data(cpu), 0x800= 00022); union amd_uncore_info info; =20 if (!boot_cpu_has(X86_FEATURE_PERFCTR_NB)) @@ -703,10 +703,8 @@ void amd_uncore_df_ctx_scan(struct amd_uncore *uncore,= unsigned int cpu) info.split.gid =3D 0; info.split.cid =3D topology_logical_package_id(cpu); =20 - if (pmu_version >=3D 2) { - ebx.full =3D cpuid_ebx(EXT_PERFMON_DEBUG_FEATURES); - info.split.num_pmcs =3D ebx.split.num_df_pmc; - } + if (leaf && pmu_version >=3D 2) + info.split.num_pmcs =3D leaf->n_pmc_northbridge; =20 *per_cpu_ptr(uncore->info, cpu) =3D info; } @@ -990,16 +988,14 @@ static void amd_uncore_umc_read(struct perf_event *ev= ent) static void amd_uncore_umc_ctx_scan(struct amd_uncore *uncore, unsigned int cpu) { - union cpuid_0x80000022_ebx ebx; + const struct leaf_0x80000022_0 *leaf =3D cpuid_leaf(&cpu_data(cpu), 0x800= 00022); union amd_uncore_info info; - unsigned int eax, ecx, edx; =20 - if (pmu_version < 2) + if (!leaf || pmu_version < 2) return; =20 - cpuid(EXT_PERFMON_DEBUG_FEATURES, &eax, &ebx.full, &ecx, &edx); - info.split.aux_data =3D ecx; /* stash active mask */ - info.split.num_pmcs =3D ebx.split.num_umc_pmc; + info.split.aux_data =3D leaf->active_umc_bitmask; + info.split.num_pmcs =3D leaf->n_pmc_umc; info.split.gid =3D topology_logical_package_id(cpu); info.split.cid =3D topology_logical_package_id(cpu); *per_cpu_ptr(uncore->info, cpu) =3D info; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E163137C0FE for ; Fri, 27 Mar 2026 02:21:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578095; cv=none; b=XtECEWLErMfBLLf1Pumu3HzcbA0QbP4l/Kedme1kTqATn/U7Cis7XhTwDKopjsoFxAtxDnoc5x01XFnVfILYIkGdfIfet1VjKhsvMbW/kYrOShE9BqTb0gjZt8ouxKh9CNFK3XvMbpHpVAx9JhyM8WmO8m71gu8jkZ3PWGyYDbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578095; c=relaxed/simple; bh=yd7Vtdy4gL9sEsI9HoJVRuxTf7GKCX3j1SSz8BTYcKI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tvGhLP6KuypnlPovRuP9hxZcIzlLe7YV7WBY5vrlNg3PXh8i4ecHKie6lhAti0rFtNJfANpkvMqUcFuMHP0KJ1jjivD2DyDEvnhVE3ZumgO9NpqycXsjDs+6r14rNsYxC0vOg7xrwid9bhFS5A7p2iH6+mBiTzCu8zL8S5oDVv0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Nsn11No0; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jW8zc4q6; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Nsn11No0"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jW8zc4q6" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T4y3r2qIMfh5P36zdKzdnROesQmFS5DUOtqzJp2p6ws=; b=Nsn11No0/60unGv49T9iBXDJ3zTyjaJ0fxSW6D9yEhE95eU7LN95jSStiLZKJ3dqCvAbuZ zI7f7ZM1gRAsxOee1It7E3pOJ9pnfsWCgPABiklzCMyARh9srDCKFAXPTSkRRZP5cBb3ot SIwEQDXEwcp22f1BJsPCfn02+yrg6/LRLkciO5OftLLSOGlYk5tIS3voc8q00BBDz6k8W1 XJowt+2EWgGJVthqLph9Eh1EYYdEVLzZjGR2TUnGAUY+odjKYYZdOGLMQkDrOGwgdsvOhA WQksgBk4DVzEoeQAEy7kRx/qcAoNFi9uZ7kLOlaL/CBOXAwJUb0ESQMEKBAh+Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578092; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=T4y3r2qIMfh5P36zdKzdnROesQmFS5DUOtqzJp2p6ws=; b=jW8zc4q6ntHBxEtz9meI7F+r14F4m1cL6kQtiYrDs/Na4fvQdyqc7rc62Gb/rXFFPM7bQQ kEZ1bGShHGX20vBw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 69/90] KVM: x86: Use standard CPUID(0x80000022) types Date: Fri, 27 Mar 2026 03:16:23 +0100 Message-ID: <20260327021645.555257-70-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use standard CPUID(0x80000022) types from x86-cpuid-db instead of relying on custom perf types. The latter are in process of getting removed from the kernel. Signed-off-by: Ahmed S. Darwish --- arch/x86/kvm/cpuid.c | 7 ++++--- arch/x86/kvm/svm/pmu.c | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 16ed4c001c79..ca769e390e62 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1870,7 +1870,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_ar= ray *array, u32 function) break; /* AMD Extended Performance Monitoring and Debug */ case 0x80000022: { - union cpuid_0x80000022_ebx ebx =3D { }; + struct leaf_0x80000022_0 leaf =3D { }; + struct cpuid_regs *regs =3D (struct cpuid_regs *)&leaf; =20 entry->ecx =3D entry->edx =3D 0; if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { @@ -1880,8 +1881,8 @@ static inline int __do_cpuid_func(struct kvm_cpuid_ar= ray *array, u32 function) =20 cpuid_entry_override(entry, CPUID_8000_0022_EAX); =20 - ebx.split.num_core_pmc =3D kvm_pmu_cap.num_counters_gp; - entry->ebx =3D ebx.full; + leaf.n_pmc_core =3D kvm_pmu_cap.num_counters_gp; + entry->ebx =3D regs->ebx; break; } /*Add support for Centaur's CPUID instruction*/ diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 7aa298eeb072..7c89b330fb73 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -179,7 +179,8 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struc= t msr_data *msr_info) static void amd_pmu_refresh(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); - union cpuid_0x80000022_ebx ebx; + struct leaf_0x80000022_0 leaf =3D { }; + struct cpuid_regs *regs =3D (struct cpuid_regs *)&leaf; =20 pmu->version =3D 1; if (guest_cpu_cap_has(vcpu, X86_FEATURE_PERFMON_V2)) { @@ -190,8 +191,8 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) */ BUILD_BUG_ON(x86_feature_cpuid(X86_FEATURE_PERFMON_V2).function !=3D 0x8= 0000022 || x86_feature_cpuid(X86_FEATURE_PERFMON_V2).index); - ebx.full =3D kvm_find_cpuid_entry_index(vcpu, 0x80000022, 0)->ebx; - pmu->nr_arch_gp_counters =3D ebx.split.num_core_pmc; + regs->ebx =3D kvm_find_cpuid_entry_index(vcpu, 0x80000022, 0)->ebx; + pmu->nr_arch_gp_counters =3D leaf.n_pmc_core; } else if (guest_cpu_cap_has(vcpu, X86_FEATURE_PERFCTR_CORE)) { pmu->nr_arch_gp_counters =3D AMD64_NUM_COUNTERS_CORE; } else { --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2479A37D123 for ; Fri, 27 Mar 2026 02:21:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578099; cv=none; b=s65B6aFLSdoimKMstT1C4wnNh1H2wh8sgd76mBHpDwtEbsp3rYuWXx+YyEVpEUbSmqRZjCDqG/FF2dWto0fBofNh7Hu2Hux6yG56DcYdUa+2HVDpZMk0Cx9/zIa+dj4uDPkKPLQz1gdHo39+sZe6+kQNWfO/pKCBm8FlSLa2BSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578099; c=relaxed/simple; bh=g019V/HJY76Wdkl5YQ2Z90xSZdvx6m1Y2lha2zoxKAU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X8LYJvX6wWkiLUM0ihM4nXxV9wEaH9NGJI+d6qk/Tn0BbaRNNbqs1p8QUFv0OBMaz1kgD++K0eIV7xkXg5AMTnxi/vCIlElsB4E9VA2cfO6w5p/4a/CqKe53c+6J52XTHDkQfANxSTEKZfhUk8ljfevXpyu+yv2oldQBDE4RopY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=qB+4epl7; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=8wKfEPCJ; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="qB+4epl7"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="8wKfEPCJ" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578095; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yayzzN5dmTMT0wbpfuB90WdBwo9M4Uvccr/uJId1r0k=; b=qB+4epl7GJrK0HoEY+9IgNYu1WFKVqueKyYZjSNFJh99/W3eYGr5MC7ZlMUR2i+T1tAm1m WfOdz2BQPMfNSbbkC2QdTzxfPDWfLvLXj1EZciTeAT6UrhoGV796SPkR2Cafk7yqVuulzP PIxWknSHW7dlP8gut8IU99hvsgcvYLK1VMzQg+p2btSkqPM0xk5qXgPqLh/qz6YbRnCr3v 72DfQxCLWCEe5YykvV02rrcMnmdaxqeH9i3GAhAFaukCivnL9NBvehHT1XB/EF6TDxDDGY I3Qbzzw54sxnX6N5J3WBxAO9sm4e4X5fltgS+WlCrjbqChS9UR5KvQ+wXcG2vg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578095; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yayzzN5dmTMT0wbpfuB90WdBwo9M4Uvccr/uJId1r0k=; b=8wKfEPCJA/BDKAkAV20kHxz2LmxPtso/hvxVMxH+4EXd4P0KAdoetM6lEkti3NcuvGscth LlFTCM4uWxGGOACg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 70/90] perf/x86: Remove custom CPUID(0x80000022) types Date: Fri, 27 Mar 2026 03:16:24 +0100 Message-ID: <20260327021645.555257-71-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All CPUID(0x80000022) call sites have been converted to the CPUID API and its auto generated x86-cpuid-db data types. Remove the custom CPUID(0x80000022) types from perf. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/perf_event.h | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 5aa07710af12..e90c79424c70 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -161,24 +161,6 @@ #define ARCH_PERFMON_PEBS_CAP_LEAF 0x4 #define ARCH_PERFMON_PEBS_COUNTER_LEAF 0x5 =20 -/* - * AMD "Extended Performance Monitoring and Debug" CPUID - * detection/enumeration details: - */ -union cpuid_0x80000022_ebx { - struct { - /* Number of Core Performance Counters */ - unsigned int num_core_pmc:4; - /* Number of available LBR Stack Entries */ - unsigned int lbr_v2_stack_sz:6; - /* Number of Data Fabric Counters */ - unsigned int num_df_pmc:6; - /* Number of Unified Memory Controller Counters */ - unsigned int num_umc_pmc:6; - } split; - unsigned int full; -}; - struct x86_pmu_capability { int version; int num_counters_gp; @@ -498,11 +480,6 @@ struct arch_pebs_cntr_header { u32 reserved; }; =20 -/* - * AMD Extended Performance Monitoring and Debug cpuid feature detection - */ -#define EXT_PERFMON_DEBUG_FEATURES 0x80000022 - /* * IBS cpuid feature detection */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9EF137E31D for ; Fri, 27 Mar 2026 02:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578103; cv=none; b=K1DINb7ofrCjSpeITx/6mwFk3sL6nWWltgUTsXybsXxmS5M8T+Gvf3+xh5WZXqfE2si8EirwXdx6T0pcj0JIL/cnI3QfcPyBKZyqU3zctsfHmzNErvQvksFI16ON0l1Gfe2nQ12jjcoR6WuUAf0fqgacT3OllLiaez+39MfIe8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578103; c=relaxed/simple; bh=HEeHRVVrEuUUbRpSfoa+QXNVD9dpzMDbgiomQdcXspc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OQ+a3CNPAA3JimNMdNwdEyY0WSAPPxFou1eEgBF04F6jWGVm0gB97cIYxbRAeb03c7VhYFXe1os/rPLfWLTMgDI2Rh7WGOpnRBHkSZKbzevf/LXcEK7OfJWKRPsXk1uZ7RIg9UYBa8xx3ZSknF6QXZOIaNxq/TxOVJR+ygOn4z0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=NWqlJSDr; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0htWTfxF; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="NWqlJSDr"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0htWTfxF" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AN0roFz7loLCdTE0vAo5+uzFEyfGPxcURyW1aCQlNRY=; b=NWqlJSDrfgnwhzX8quin6l3/Y84e+vwD2VLKaQPmZXtTsLUpGTNQi+gR7zcdryQ98mLggC qrEPtiXKuns3v+MryrkWecheLRNFcNHO9uqdxKBh9GwCz8RlUTDcAxv0XRr46e5SHKrANC STdHa5rCW4jDAvgJtQA+0fd7BeA2BqhGZ/57pySJn1ar7CjuM3X+9j2EiTra0+ogiO8Sz2 PdG+eYATMASK/3qV7SLrCZ/Q+mAF01mFJerJOcSToTTXvzTs1qRjeeiDvzbkSN4rECzl+m HeivV3AGSTqGIfU85AIEhmznBbYkxE+KZMr4qHauLXPh3iJAc4fzLmCtNhkd4Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578099; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AN0roFz7loLCdTE0vAo5+uzFEyfGPxcURyW1aCQlNRY=; b=0htWTfxFT9GNNBcYeiTm00cwS5r5ykvt+ZtO6BqfiQSUROfw5BcziNaVb6XIU7YKWTgJ3+ AnkemAYQiLjCgMAg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 71/90] x86/cpuid: Parse CPUID(0x80000007) Date: Fri, 27 Mar 2026 03:16:25 +0100 Message-ID: <20260327021645.555257-72-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse CPUID(0x80000007). This allows the cpuinfo_x86::x86_power call sites to be converted to the CPUID APIs next. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index deddb534486a..6180acd35f59 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -227,6 +227,7 @@ struct cpuid_leaves { CPUID_LEAF ( 0x80000004, 0 ); CPUID_LEAF ( 0x80000005, 0 ); CPUID_LEAF ( 0x80000006, 0 ); + CPUID_LEAF ( 0x80000007, 0 ); CPUID_LEAF ( 0x80000008, 0 ); CPUID_LEAF_N ( 0x8000001d, 8 ); CPUID_LEAF ( 0x80000022, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 59a4d562320a..c81f76c1c077 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -161,6 +161,7 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000005, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000006, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000007, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000008, 0, generic ), \ CPUID_PARSE_ENTRY_N ( 0x8000001d, deterministic_cache ), \ CPUID_PARSE_ENTRY ( 0x80000022, 0, generic ), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B466A37E31D for ; Fri, 27 Mar 2026 02:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578107; cv=none; b=hWmk3XGURTg9IKXTdxh0sYI4QLiGcGvIX2HAc+h2HlWpRwFjRTyei2Wl5v4MtDhv81SG5gz33lFAUO+NGM//j+n9bR6bc8Q4yK2uLyZci8tx7Fl+BzFKjbmtLWEOR/qMAo05vN4I3brHW3+DaQxFCgS6NdY/Zpmc+MdqOdsCoVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578107; c=relaxed/simple; bh=e+MD6ty8wZ8eXxKciAGHSIOudpMchrw7xhC0CyM2pj8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SiKuyCbfYQeLmATVgZeKfXKBi8hnJzyhje3d7vvRnGTt1JVTjVy6ugi4PltX4PqHrd4msJFQzHtsyJefLGXPrHp/0C6oh8azF7i1cUbJPQuHt6i9Kivl8fBTsHhIOoLay6AXB+EY4WHtAVnyUnC2m/DjA3CGjkpw/HdEp1f7fwc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gA4s3k74; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IYnd99zf; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gA4s3k74"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IYnd99zf" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AAvn3qOEM3Vwm1f30Pnr1M3ypziLQ66JJBfFkFAQwUk=; b=gA4s3k74so7G6qcgUbYVcmVn1b/loSp00pbqx+Fg83DHGRreqiG/hfSXAxLtHdAEU2ECpE xCvnPxxi5c9TWnVRRJ+m3PBewJtjA7JA2B0wIiRKrWhvRy3N8lNJqtYnYEprQjYLBW3UqB gl1htlswRa84f+k9g00H5hIEvKWpoua0mBO8/Jae3X5qoys2vQwgl61dOhmuk6N16PUsTj e+Zb5MnJ1jb+jwhMhuntmvb0P+gPZKnKJpN/XBsayUodB4/UbuWVyAWor0lgDOujDdz2/p EaUexuOf7z9W/PTGYGXcE89rssJHwEnp85FO570jH3+tI4YO5VO01ifcZ1MVwg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578103; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AAvn3qOEM3Vwm1f30Pnr1M3ypziLQ66JJBfFkFAQwUk=; b=IYnd99zfFihdtioVnMI61uNbVKy584cBN2cA0sG9OmVfjV1lA+2oDI0YTdby4rdyVMCFUV QefCnvAulwBwR2CQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 72/90] x86/cpu: Use parsed CPUID(0x80000007) Date: Fri, 27 Mar 2026 03:16:26 +0100 Message-ID: <20260327021645.555257-73-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For Intel, Centar, and Zhaoxin early init, use parsed CPUID(0x80000007) instead of doing ugly bitwise operations on cpuinfo_x86::x86_power. The latter is backed by a direct CPUID query and will be later removed. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 4 +++- arch/x86/kernel/cpu/intel.c | 13 +++++++------ arch/x86/kernel/cpu/zhaoxin.c | 4 +++- 3 files changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 86cbe4427453..29688aec2231 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -89,6 +89,8 @@ enum { =20 static void early_init_centaur(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); + #ifdef CONFIG_X86_32 /* Emulate MTRRs using Centaur's MCR. */ if (c->x86 =3D=3D 5) @@ -98,7 +100,7 @@ static void early_init_centaur(struct cpuinfo_x86 *c) (c->x86 >=3D 7)) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); =20 - if (c->x86_power & (1 << 8)) { + if (el7 && el7->constant_tsc) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 7f186c68d701..e84042d1bbca 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -215,6 +215,7 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) =20 static void early_init_intel(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); u64 misc_enable; =20 if (c->x86 >=3D 6 && !cpu_has(c, X86_FEATURE_IA64)) @@ -262,16 +263,16 @@ static void early_init_intel(struct cpuinfo_x86 *c) c->x86_phys_bits =3D 36; =20 /* - * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate - * with P/T states and does not stop in deep C-states. + * CPUID(0x80000007).constant_tsc implies that TSC runs at constant + * rate with P/T states and does not stop in deep C-states * - * It is also reliable across cores and sockets. (but not across - * cabinets - we turn it off in that case explicitly.) + * It is also reliable across cores and sockets, but not across + * cabinets; disable it explicitly in that case. * * Use a model-specific check for some older CPUs that have invariant - * TSC but may not report it architecturally via 8000_0007. + * TSC but may not report it architecturally via CPUID(0x80000007). */ - if (c->x86_power & (1 << 8)) { + if (el7 && el7->constant_tsc) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } else if ((c->x86_vfm >=3D INTEL_P4_PRESCOTT && c->x86_vfm <=3D INTEL_P4= _CEDARMILL) || diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index b068922efed9..5918f9387c87 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -50,10 +50,12 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c) =20 static void early_init_zhaoxin(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); + if (c->x86 >=3D 0x6) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); =20 - if (c->x86_power & (1 << 8)) { + if (el7 && el7->constant_tsc) { set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); } --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3361A3815EC for ; Fri, 27 Mar 2026 02:21:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578110; cv=none; b=fRlnzxrVjbeGuoeEettPeXz7QspstPaNrfH+JPIOtVC30HT8Ef4f70LOVWpNqrlXktGmQzdJB6IPY5oFEJ/liBMHCNH38zH2IzjerFsRq5WPGJXmlx+r31N4yZlVm0lNeH1YzQr9g1a2MISf5z13c8yRwyPcMDQBzScpWhusmzw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578110; c=relaxed/simple; bh=3ip9D8kjLufcOqX9eQBZGeqe4HxRgtZuOovV0z6vdc0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QdS2RSX3fNxm1JSRhNcLvhdCwwO+13NiWrujEeGsZYYvS5ektBrmTaovV/jY3OYRwL4J3LVZ9r4XC5on8DnVpwY2WdyRLa8KsD2oM+Qho1g+frcrTeWea1JuzYy1ayZDjodyQ3xeX0p75I1oMxbuzx7dXnfUPAWXbonom7Ejs90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cAbrlM3H; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KvkYHOBM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cAbrlM3H"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KvkYHOBM" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 73/90] x86/cpu: amd/hygon: Use parsed CPUID(0x80000007) Date: Fri, 27 Mar 2026 03:16:27 +0100 Message-ID: <20260327021645.555257-74-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000007) instead of doing ugly bitwise operations on cpuinfo_x86::x86_power. The latter is backed by a direct CPUID query and will be later removed. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/amd.c | 25 +++++++++++-------------- arch/x86/kernel/cpu/hygon.c | 25 +++++++++++-------------- 2 files changed, 22 insertions(+), 28 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 5fd7f34fa284..96b67b8b694c 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -611,6 +611,7 @@ static void early_detect_mem_encrypt(struct cpuinfo_x86= *c) =20 static void early_init_amd(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); u32 dummy; =20 if (c->x86 >=3D 0xf) @@ -618,22 +619,18 @@ static void early_init_amd(struct cpuinfo_x86 *c) =20 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); =20 - /* - * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate - * with P/T states and does not stop in deep C-states - */ - if (c->x86_power & (1 << 8)) { - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - } + if (el7) { + if (el7->constant_tsc) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } =20 - /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ - if (c->x86_power & BIT(12)) - set_cpu_cap(c, X86_FEATURE_ACC_POWER); + if (el7->proc_power_reporting) + set_cpu_cap(c, X86_FEATURE_ACC_POWER); =20 - /* Bit 14 indicates the Runtime Average Power Limit interface. */ - if (c->x86_power & BIT(14)) - set_cpu_cap(c, X86_FEATURE_RAPL); + if (el7->rapl_interface) + set_cpu_cap(c, X86_FEATURE_RAPL); + } =20 #ifdef CONFIG_X86_64 set_cpu_cap(c, X86_FEATURE_SYSCALL32); diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c index 4a63538c2b3f..8f31005bc802 100644 --- a/arch/x86/kernel/cpu/hygon.c +++ b/arch/x86/kernel/cpu/hygon.c @@ -125,28 +125,25 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c) =20 static void early_init_hygon(struct cpuinfo_x86 *c) { + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); u32 dummy; =20 set_cpu_cap(c, X86_FEATURE_K8); =20 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); =20 - /* - * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate - * with P/T states and does not stop in deep C-states - */ - if (c->x86_power & (1 << 8)) { - set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); - set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); - } + if (el7) { + if (el7->constant_tsc) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } =20 - /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ - if (c->x86_power & BIT(12)) - set_cpu_cap(c, X86_FEATURE_ACC_POWER); + if (el7->proc_power_reporting) + set_cpu_cap(c, X86_FEATURE_ACC_POWER); =20 - /* Bit 14 indicates the Runtime Average Power Limit interface. */ - if (c->x86_power & BIT(14)) - set_cpu_cap(c, X86_FEATURE_RAPL); + if (el7->rapl_interface) + set_cpu_cap(c, X86_FEATURE_RAPL); + } =20 #ifdef CONFIG_X86_64 set_cpu_cap(c, X86_FEATURE_SYSCALL32); --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59C6D344DB8 for ; Fri, 27 Mar 2026 02:21:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578115; cv=none; b=YJ06cAuGfmULgvafTgrys6A6euSSUn5qglGErn8tQ+1mPJUEk57ABRuW3dnXF1+ZpNIARPYIWvR7+5OuxfNjzkVI+ZpVak3Q2k9mvS1m1vdHEuLuE6jUSzEyRrw4s6PY8GTrzHL6QeQyczGOBwqv3oXCQAXbZ4IVT5TPU6KiS8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578115; c=relaxed/simple; bh=yGpyp2VbqfBRv/6K19duLXjw9GnyTPW2kBHoesDamuY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XxdqNuzpKzDl8Kg0/ug5n4T7wTCuVslvD5E8XbslR736FixGyBNTOBfK4GbLLQF+G7eJ+OJXlDsCDODEbpEaWHeTn+UioEWwYtjDo+8dFivZJyPZ4HEQL/+eITQl/KKfYGjU0yYykjig2epFHAEcau56Rih65RQl51rXCELJMXo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=3PAAlfxq; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KHANFXrE; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="3PAAlfxq"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KHANFXrE" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578111; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BdKN2UCc2MyJyZk8Qlu2N8awUuHIlp3nYdn+49Tvn0Y=; b=3PAAlfxqMsDfyp23cD127uE3JQPud0P4acXmuBT8U1+ZWeYSKBFLAxqOThSC18NMzNIMBN QdUMtXjD5/pmX5w0ccER5RJEsfEILF7Soi6VO4crRkrkEjky5DMxdzXw2qnb8OsP1UpQNN gjnADZ+9ZoId/wecdO8+hFP8pqWfBROGnFaJm2ESYZFC/86cB33ssmSBXu4wDqTHPO7f3y zsWzTZu4UrC/zGJ1H2vOkYXQJo9md4xjPwUTtqytV3xCuJTjTNSO+n29AjRnee9QMhsRiA ThG9qHHutKffwfHwzyHTfimajh/frHw59S0bAWFiVQn3L6awdtvppiKVH77L2g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578111; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BdKN2UCc2MyJyZk8Qlu2N8awUuHIlp3nYdn+49Tvn0Y=; b=KHANFXrEur7p/JOfGDtCk4WskxBK9pjmgsYLnMyptSrvwX3oqes3QuN00iSFanPcnDFESq wPeBWoMBJ8tsvUBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 74/90] x86/cpu: cpuinfo: Use parsed CPUID(0x80000007) Date: Fri, 27 Mar 2026 03:16:28 +0100 Message-ID: <20260327021645.555257-75-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For /proc/cpuinfo "power management" line, use parsed CPUID(0x80000007) instead of poking at cpuinfo_x86::x86_power. The latter is backed by a direct CPUID query and will be later removed. Remove the x86_power_flags[] strings table as it has no more users. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpufeature.h | 1 - arch/x86/kernel/cpu/Makefile | 2 +- arch/x86/kernel/cpu/powerflags.c | 24 ------------ arch/x86/kernel/cpu/proc.c | 61 ++++++++++++++++++++++++------- 4 files changed, 49 insertions(+), 39 deletions(-) delete mode 100644 arch/x86/kernel/cpu/powerflags.c diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 3ddc1d33399b..520949560138 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -39,7 +39,6 @@ enum cpuid_leafs }; =20 extern const char * const x86_cap_flags[NCAPINTS*32]; -extern const char * const x86_power_flags[32]; =20 /* * In order to save room, we index into this array by doing diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index d62e2d60a965..5c091d9fc9ee 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -27,7 +27,7 @@ obj-y +=3D bugs.o obj-y +=3D aperfmperf.o obj-y +=3D cpuid-deps.o cpuid_0x2_table.o obj-y +=3D umwait.o -obj-y +=3D capflags.o powerflags.o +obj-y +=3D capflags.o =20 obj-$(CONFIG_X86_LOCAL_APIC) +=3D topology.o =20 diff --git a/arch/x86/kernel/cpu/powerflags.c b/arch/x86/kernel/cpu/powerfl= ags.c deleted file mode 100644 index fd6ec2aa0303..000000000000 --- a/arch/x86/kernel/cpu/powerflags.c +++ /dev/null @@ -1,24 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Strings for the various x86 power flags - * - * This file must not contain any executable code. - */ - -#include - -const char *const x86_power_flags[32] =3D { - "ts", /* temperature sensor */ - "fid", /* frequency id control */ - "vid", /* voltage id control */ - "ttp", /* thermal trip */ - "tm", /* hardware thermal control */ - "stc", /* software thermal control */ - "100mhzsteps", /* 100 MHz multiplier control */ - "hwpstate", /* hardware P-state control */ - "", /* tsc invariant mapped to constant_tsc */ - "cpb", /* core performance boost */ - "eff_freq_ro", /* Readonly aperf/mperf */ - "proc_feedback", /* processor feedback interface */ - "acc_power", /* accumulated power mechanism */ -}; diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c index 6571d432cbe3..89471bcfcc32 100644 --- a/arch/x86/kernel/cpu/proc.c +++ b/arch/x86/kernel/cpu/proc.c @@ -4,9 +4,11 @@ #include #include #include -#include #include =20 +#include +#include + #include "cpu.h" =20 #ifdef CONFIG_X86_VMX_FEATURE_NAMES @@ -60,6 +62,50 @@ static void show_cpuinfo_misc(struct seq_file *m, struct= cpuinfo_x86 *c) } #endif =20 +static void show_cpuinfo_power(struct cpuinfo_x86 *c, struct seq_file *m) +{ + const struct cpuid_regs *el7_regs =3D cpuid_leaf_raw(c, 0x80000007); + const struct leaf_0x80000007_0 *el7 =3D cpuid_leaf(c, 0x80000007); + + seq_puts(m, "power management:"); + + if (!el7_regs || !el7) + return; + + if (el7->digital_temp) + seq_puts(m, " ts"); + if (el7->powernow_freq_id) + seq_puts(m, " fid"); + if (el7->powernow_volt_id) + seq_puts(m, " vid"); + if (el7->thermal_trip) + seq_puts(m, " ttp"); + if (el7->hw_thermal_control) + seq_puts(m, " tm"); + if (el7->sw_thermal_control) + seq_puts(m, " stc"); + if (el7->_100mhz_steps) + seq_puts(m, " 100mhzsteps"); + if (el7->hw_pstate) + seq_puts(m, " hwpstate"); + + /* Keep constant_tsc off the power management line */ + + if (el7->core_perf_boost) + seq_puts(m, " cpb"); + if (el7->eff_freq_ro) + seq_puts(m, " eff_freq_ro"); + if (el7->proc_feedback) + seq_puts(m, " proc_feedback"); + if (el7->proc_power_reporting) + seq_puts(m, " acc_power"); + + /* Afterwards, just output the offsets of set bits */ + for (int i =3D 13; i < 32; i++) + if (el7_regs->edx & BIT(i)) + seq_printf(m, " [%d]", i); +} + static int show_cpuinfo(struct seq_file *m, void *v) { struct cpuinfo_x86 *c =3D v; @@ -138,18 +184,7 @@ static int show_cpuinfo(struct seq_file *m, void *v) seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n", c->x86_phys_bits, c->x86_virt_bits); =20 - seq_puts(m, "power management:"); - for (i =3D 0; i < 32; i++) { - if (c->x86_power & (1 << i)) { - if (i < ARRAY_SIZE(x86_power_flags) && - x86_power_flags[i]) - seq_printf(m, "%s%s", - x86_power_flags[i][0] ? " " : "", - x86_power_flags[i]); - else - seq_printf(m, " [%d]", i); - } - } + show_cpuinfo_power(c, m); =20 seq_puts(m, "\n\n"); =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6D3BD384230 for ; Fri, 27 Mar 2026 02:21:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578118; cv=none; b=P8TG6YqC7K2L0G58C9oz29rfh1Sp53A52iDl3oWV5E8Nk/AIF2/RFH00hP+ME4CMcQQzMsS1H3g8paK3L4yZZaAnqkPkHD8PDDs4RSMWSnMY0fPcIn23O7nRP4N3/MaIz3OUoKY629Qwxqu5wW0cXm9AoR5VClfk5mUJgRhjIpY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578118; c=relaxed/simple; bh=SEtDelFttYyAA1iLr5xwi84uQX0GCqD4IZPsVMstLzs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EhiOv+gGVrtRBa0N3w4G7QaYpPbNwFrvtkG3kS4vS+BDY8SrZMbKwuMX/nI2NGbhfJYd+oLsJVBOmYZf89pzO3eWLco8QJkMJ9O5sR4biXXllDz4xSUDWM6aIEeuq+3qFemR0NB0pc7MTMB0A5OXNxvxLbAuhBX0G0Vq/6jmokc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GLLQk54U; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wpXoDH6b; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GLLQk54U"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wpXoDH6b" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 75/90] KVM: x86: Use parsed CPUID(0x80000007) Date: Fri, 27 Mar 2026 03:16:29 +0100 Message-ID: <20260327021645.555257-76-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For KVM cpuid, use parsed CPUID(0x80000007) instead of poking at x86_power. The latter is backed by a direct CPUID query and will be removed later. Signed-off-by: Ahmed S. Darwish --- arch/x86/kvm/cpuid.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index ca769e390e62..efc155e1da10 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -1763,13 +1763,18 @@ static inline int __do_cpuid_func(struct kvm_cpuid_= array *array, u32 function) /* Drop reserved bits, pass host L2 cache and TLB info. */ entry->edx &=3D ~GENMASK(17, 16); break; - case 0x80000007: /* Advanced power management */ + case 0x80000007: { /* Advanced power management */ + const struct cpuid_regs *el7 =3D cpuid_leaf_raw(&boot_cpu_data, 0x800000= 07); + cpuid_entry_override(entry, CPUID_8000_0007_EDX); =20 - /* mask against host */ - entry->edx &=3D boot_cpu_data.x86_power; + /* Mask against host */ + if (el7) + entry->edx &=3D el7->edx; + entry->eax =3D entry->ebx =3D entry->ecx =3D 0; break; + } case 0x80000008: { /* * GuestPhysAddrSize (EAX[23:16]) is intended for software --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F20138656A for ; Fri, 27 Mar 2026 02:22:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578121; cv=none; b=jofp7bh/+IWs9imtBTUgg1SebdnKmqSkBqC+VFXIZRdSIE7y9Kgt+8iRbKlOvVI+iYxboqr0Yo8Ec+wIYtKJwlTcLgn43faSgPtT1W0AIQgLym6ht63KSRQIkYlIDjtwAfBVq5SuYz2gE2t/tfHP1qfpLgyVjm8jiTZ8NjCPYsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578121; c=relaxed/simple; bh=s1f3pyf+/i5IW706fn6yTdIIunq0yuSWr/ay+LNfuFo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EhK1r577YY4WeB6QIhXoaQ6wsPxs5PSTScp7PQzeLINnOv5K3w6DN4HDMJONg+2QChDb/vLY9Ds93aobkxG2yGPfFGAMQWm6lXs3oiVP/+vFShrDdUYIN/+KveWKasDAGW/REb+HiRBN7JkH+D3gT9nnX40kFBydB/mgzjYKCYI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q69I9Vl4; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MEvB2xdi; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q69I9Vl4"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MEvB2xdi" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578119; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B1/dj0aiJxPrVtjeZ/PwDKekOoP3+cq3AouSDZ8vkV4=; b=Q69I9Vl4ufRub2ZemEWv35dy9KTO4JDnTjicg9NqfJjzYf7igbLdNDfm3A6sK7YtOwbfnK rzVipmjv0ntjIqy+5J+pH3qI/ecrT3bpOjuhInXQ7a+d1P1CM4tG/PrJ7LpR2rVo0BZigP qkq8cvEOPJUnfN7xg25K3r4iorgIKCsJZ0NWwWYv1KFd89QRmJf0Hs335zT+FaGyJPjTnU CouR21YF2W/wVYBZlYjkebIWCO+J16Uhc4WUDzg5iOWQTay1U9jrfok6297rsmLZ9C/Raq 5BZSFmTgsIPGSQS8Q9h5hzE/gHBn78ebCKHPTAyBX/YYx6+P+6aLREMQu17jHQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578119; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B1/dj0aiJxPrVtjeZ/PwDKekOoP3+cq3AouSDZ8vkV4=; b=MEvB2xdiYu4THBCPpBZ+LNmEpKg8HjNwz0Bf5t8k7xp05epRUWh+5P1IP85pXkZI5CU95Z vm6cK0Go1z5IGVBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 76/90] x86/microcode: Allocate cpuinfo_x86 snapshots on the heap Date: Fri, 27 Mar 2026 03:16:30 +0100 Message-ID: <20260327021645.555257-77-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" load_late_stop_cpus() snapshots CPU capabilities before a late microcode update, while microcode_check() snapshots the capabilities again after the update. Both functions allocate their struct cpuinfo_x86 snapshots on the stack. Meanwhile, cpuinfo_x86 contains the parsed CPUID tables where more leaves will be added; resulting in "stack frame length exceeded" warnings. Allocate the before/after cpuinfo_x86 snapshots on the heap. For load_late_stop_cpus(), do the memory allocation before the microcode staging step. This leaves no leaked or stale microcode state in -ENOMEM failure modes. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 11 ++++++++--- arch/x86/kernel/cpu/microcode/core.c | 9 ++++++--- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2beb53f6bed7..ece5a59124f5 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2543,15 +2543,20 @@ void store_cpu_caps(struct cpuinfo_x86 *curr_info) */ void microcode_check(struct cpuinfo_x86 *prev_info) { - struct cpuinfo_x86 curr_info; + struct cpuinfo_x86 *curr_info __free(kfree) =3D kmalloc_obj(*curr_info); =20 perf_check_microcode(); =20 amd_check_microcode(); =20 - store_cpu_caps(&curr_info); + if (!curr_info) { + pr_warn("x86/CPU: Microcode update CPU capability changes check was skip= ped (ENOMEM)\n"); + return; + } + + store_cpu_caps(curr_info); =20 - if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability, + if (!memcmp(&prev_info->x86_capability, &curr_info->x86_capability, sizeof(prev_info->x86_capability))) return; =20 diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/mic= rocode/core.c index 56d791aeac4e..7a00671540bc 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -588,16 +588,19 @@ static int load_cpus_stopped(void *unused) =20 static int load_late_stop_cpus(bool is_safe) { + struct cpuinfo_x86 *prev_info __free(kfree) =3D kmalloc_obj(*prev_info); unsigned int cpu, updated =3D 0, failed =3D 0, timedout =3D 0, siblings = =3D 0; unsigned int nr_offl, offline =3D 0; int old_rev =3D boot_cpu_data.microcode; - struct cpuinfo_x86 prev_info; =20 if (!is_safe) { pr_err("Late microcode loading without minimal revision check.\n"); pr_err("You should switch to early loading, if possible.\n"); } =20 + if (!prev_info) + return -ENOMEM; + /* * Pre-load the microcode image into a staging device. This * process is preemptible and does not require stopping CPUs. @@ -617,7 +620,7 @@ static int load_late_stop_cpus(bool is_safe) * Take a snapshot before the microcode update in order to compare and * check whether any bits changed after an update. */ - store_cpu_caps(&prev_info); + store_cpu_caps(prev_info); =20 if (microcode_ops->use_nmi) static_branch_enable_cpuslocked(µcode_nmi_handler_enable); @@ -666,7 +669,7 @@ static int load_late_stop_cpus(bool is_safe) num_online_cpus() - (updated + siblings)); } pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); - microcode_check(&prev_info); + microcode_check(prev_info); =20 return updated + siblings =3D=3D num_online_cpus() ? 0 : -EIO; } --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9979F3890E7 for ; Fri, 27 Mar 2026 02:22:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578124; cv=none; b=s8fAhg8ypcIRChd2DhIrfL1NTEu2Yx0sWwcicAto6HHmepoFlDSH5vvklHooBlhs/cBydYsSxaWCJ98AauCXnCFZkUG7Ou/f2e+zVHhafaFwG75u5CAIiesUXUQtboE8TrT6ACOCqADIWVveN1KyzlrkLlsJ+Kxf6Tno02wvdao= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578124; c=relaxed/simple; bh=jM6IyPtqSl0Z/qb+GWetwbBK0Q5qGgMBAsPTAYXFv64=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qi7r5Uwpw/U1sD6M0PDJtghzrjmmZB67dc/hRGLAak56Wtuj7VFbG1/Y0AFFx3EOidfbaIph9rxa/LifuIMC3y3Wl7/32qNkQ9mEfO/DYOVstX737soOUWLvvLJ2FtJOOGVXmEpS49I2UYL8XieAa8BQRQj55cLKnwo7HNOlzEE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=W4KS8TML; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=6m7ZH0Q4; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="W4KS8TML"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="6m7ZH0Q4" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 77/90] x86/cpuid: Parse leaves backing X86_FEATURE words Date: Fri, 27 Mar 2026 03:16:31 +0100 Message-ID: <20260327021645.555257-78-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID parser support for: CPUID(0x6) CPUID(0x7) CPUID(0x7).1 CPUID(0xd).1 CPUID(0x80000001) CPUID(0x8000000a) CPUID(0x8000001f) CPUID(0x80000021) where one or more of these leaves output registers back the X86_FEATURE words at . Handle CPUID(0x7).1 via a custom reader. Its availability depends on the subleaf count reported by CPUID(0x7).0, so check that first. Do not use a custom reader for CPUID(0xd).1. Per the Intel SDM regarding CPUID(0xd)'s subleaf availability: "sub-leafs 0 and 1 are always valid". Note, this prepares for later changes that will route X86_FEATURE queries from cpuinfo_x86::x86_capability[] to the system's CPUID tables. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 8 ++++++++ arch/x86/kernel/cpu/cpuid_parser.c | 13 +++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 8 ++++++++ 3 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 6180acd35f59..204d6277c8cd 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -212,7 +212,11 @@ struct cpuid_leaves { CPUID_LEAF ( 0x1, 0 ); CPUID_LEAF ( 0x2, 0 ); CPUID_LEAF_N ( 0x4, 8 ); + CPUID_LEAF ( 0x6, 0 ); + CPUID_LEAF ( 0x7, 0 ); + CPUID_LEAF ( 0x7, 1 ); CPUID_LEAF ( 0xa, 0 ); + CPUID_LEAF ( 0xd, 1 ); CPUID_LEAF ( 0x1c, 0 ); CPUID_LEAF ( 0x16, 0 ); CPUID_LEAF ( 0x23, 0 ); @@ -222,6 +226,7 @@ struct cpuid_leaves { CPUID_LEAF ( 0x23, 4 ); CPUID_LEAF ( 0x23, 5 ); CPUID_LEAF ( 0x80000000, 0 ); + CPUID_LEAF ( 0x80000001, 0 ); CPUID_LEAF ( 0x80000002, 0 ); CPUID_LEAF ( 0x80000003, 0 ); CPUID_LEAF ( 0x80000004, 0 ); @@ -229,7 +234,10 @@ struct cpuid_leaves { CPUID_LEAF ( 0x80000006, 0 ); CPUID_LEAF ( 0x80000007, 0 ); CPUID_LEAF ( 0x80000008, 0 ); + CPUID_LEAF ( 0x8000000a, 0 ); CPUID_LEAF_N ( 0x8000001d, 8 ); + CPUID_LEAF ( 0x8000001f, 0 ); + CPUID_LEAF ( 0x80000021, 0 ); CPUID_LEAF ( 0x80000022, 0 ); CPUID_LEAF ( 0x80860000, 0 ); CPUID_LEAF ( 0x80860001, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index de11fb4116f2..b3bf4141db15 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -99,6 +99,19 @@ cpuid_read_0x2(const struct cpuid_parse_entry *e, const = struct cpuid_read_output output->info->nr_entries =3D 1; } =20 +static void +cpuid_read_0x7_1(const struct cpuid_parse_entry *e, const struct cpuid_rea= d_output *output) +{ + struct leaf_0x7_0 l7; + + cpuid_read_subleaf(0x7, 0, &l7); + if (l7.leaf7_n_subleaves =3D=3D 0) + return; + + cpuid_read_subleaf(e->leaf, e->subleaf, output->regs); + output->info->nr_entries =3D 1; +} + /* * Shared read function for Intel CPUID(0x4) and AMD CPUID(0x8000001d), as= both have * the same subleaf enumeration logic and register output format. diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index c81f76c1c077..f6a620a03312 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -146,7 +146,11 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY ( 0x2, 0, 0x2 ), \ CPUID_PARSE_ENTRY_N ( 0x4, deterministic_cache ), \ + CPUID_PARSE_ENTRY ( 0x6, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x7, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x7, 1, 0x7_1 ), \ CPUID_PARSE_ENTRY ( 0xa, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0xd, 1, generic ), \ CPUID_PARSE_ENTRY ( 0x1c, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x16, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x23, 0, generic ), \ @@ -156,6 +160,7 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x23, 4, 0x23_4 ), \ CPUID_PARSE_ENTRY ( 0x23, 5, 0x23_5 ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ + CPUID_PARSE_ENTRY ( 0x80000001, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000003, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000004, 0, generic ), \ @@ -163,7 +168,10 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x80000006, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000007, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000008, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x8000000a, 0, generic ), \ CPUID_PARSE_ENTRY_N ( 0x8000001d, deterministic_cache ), \ + CPUID_PARSE_ENTRY ( 0x8000001f, 0, generic ), \ + CPUID_PARSE_ENTRY ( 0x80000021, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000022, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80860000, 0, 0x80860000 ), \ CPUID_PARSE_ENTRY ( 0x80860001, 0, generic ), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F375138B7BE for ; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B+fk+/TuRwEZZ2ihuSM8rA4eRhVclgy/Iky91vo+GTg=; b=k0KcPtOK/hZ9AUFYJO6RMTz0dqOw7JuAHAlc01Ecg0Xr2PsPKE3ZfZvld0rYGD5JvPCXhd 2fxhwcynjsKAhmxGk6wUhuTkJJ7Wm3ZcDubQG1SVd97ghgb2Q9YExWPynOPzYV+h+5lgrA aegDSHzKvUkxdseotjhT7JHRFO/R5Jw20BzbGEeyO3HOOn9K6C+s8BvfYExk8aQ9vLNtt2 JYUgUePW8yKKiXW8WhjT1yuV2qPT13h0iuKX0bgQZSYPYl/zJIdQjWbwdhtjJ+mdg3JvPd X7CCsKf1O3bNN0kVcehKCPxDaCfOyWtSU6TuPIAEtUvjlXPvJW59UdhfIO2vlA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578125; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B+fk+/TuRwEZZ2ihuSM8rA4eRhVclgy/Iky91vo+GTg=; b=EltMKYWrYA1HU5AKK/ryztolpl8+mo/X9y3sky5rofrSmbnY9dWAwVLfdpq5+u0UVQWWt/ Q5ZGmCygj4ocHJCQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 78/90] x86/cpuid: Parse Linux synthetic CPUID leaves Date: Fri, 27 Mar 2026 03:16:32 +0100 Message-ID: <20260327021645.555257-79-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The X86_FEATURE words at contain both hardware-defined CPUID register bits and Linux-defined synthetic bits. The hardware-defined bits already map naturally into the parsed CPUID tables, but the synthetic bits do not. This gets feature enumeration split between the CPUID parser and the feature APIs. For this, the x86-cpuid-db project provides a 1:1 bitfield mapping for the synthetic X86_FEATURE words using the CPUID range 0x4c780000. The range prefix 0x4c78 is for Linux in its shorthand ASCII form Lx, where Linux becomes a virtual vendor mirroring hardware vendors like AMD and Intel. Cover all the synthetic feature and bug words by parsing CPUID(0x4c780001), CPUID(0x4c780001).1, and CPUID(0x4c780002). Skip these synthetic CPUID leaves in the debugfs code which compares each cached CPUID value against its actual hardware backing. Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/874ixernra.ffs@tglx Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v3.0/CHANGELOG.r= st --- arch/x86/include/asm/cpuid/types.h | 5 +++++ arch/x86/kernel/cpu/cpuid_debugfs.c | 4 ++++ arch/x86/kernel/cpu/cpuid_parser.c | 17 +++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 3 +++ 4 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 204d6277c8cd..263e82e89f70 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -39,11 +39,13 @@ enum cpuid_regs_idx { #define CPUID_EXT_START 0x80000000 #define CPUID_TMX_START 0x80860000 #define CPUID_CTR_START 0xc0000000 +#define CPUID_LNX_START 0x4c780000 =20 #define CPUID_BASE_END CPUID_RANGE_MAX(CPUID_BASE_START) #define CPUID_EXT_END CPUID_RANGE_MAX(CPUID_EXT_START) #define CPUID_TMX_END CPUID_RANGE_MAX(CPUID_TMX_START) #define CPUID_CTR_END CPUID_RANGE_MAX(CPUID_CTR_START) +#define CPUID_LNX_END CPUID_RANGE_MAX(CPUID_LNX_START) =20 /* * Types for CPUID(0x2) parsing: @@ -225,6 +227,9 @@ struct cpuid_leaves { CPUID_LEAF ( 0x23, 3 ); CPUID_LEAF ( 0x23, 4 ); CPUID_LEAF ( 0x23, 5 ); + CPUID_LEAF ( 0x4c780001, 0 ); + CPUID_LEAF ( 0x4c780001, 1 ); + CPUID_LEAF ( 0x4c780002, 0 ); CPUID_LEAF ( 0x80000000, 0 ); CPUID_LEAF ( 0x80000001, 0 ); CPUID_LEAF ( 0x80000002, 0 ); diff --git a/arch/x86/kernel/cpu/cpuid_debugfs.c b/arch/x86/kernel/cpu/cpui= d_debugfs.c index 4bd874bffffc..c1ae9d7449cc 100644 --- a/arch/x86/kernel/cpu/cpuid_debugfs.c +++ b/arch/x86/kernel/cpu/cpuid_debugfs.c @@ -36,6 +36,10 @@ cpuid_show_leaf(struct seq_file *m, uintptr_t cpu_id, co= nst struct cpuid_parse_e }; int ret; =20 + /* Ignore synthetic ranges as they have no hardware backing */ + if (CPUID_RANGE(entry->leaf) =3D=3D CPUID_LNX_START) + continue; + seq_printf(m, "Leaf 0x%08x, subleaf %u:\n", entry->leaf, subleaf); =20 ret =3D smp_call_function_single(cpu_id, cpuid_this_cpu, ®s, true); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index b3bf4141db15..9e22081f649d 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -155,6 +155,21 @@ define_cpuid_0x23_subleaf_read_function(3); define_cpuid_0x23_subleaf_read_function(4); define_cpuid_0x23_subleaf_read_function(5); =20 +/* + * Synthetic CPUID leaves read function + * + * These leaves do not exist in hardware. They reserve slots in the per-C= PU + * CPUID tables for the synthetic Linux-defined X86_FEATURE and X86_BUG wo= rds. + * + * Always mark the read as successful; the actual bits will be populated v= ia + * the X86_FEATURE bit update helpers at . + */ +static void +cpuid_read_synthetic(const struct cpuid_parse_entry *e, const struct cpuid= _read_output *output) +{ + output->info->nr_entries =3D 1; +} + /* * Define an extended range CPUID read function * @@ -242,6 +257,7 @@ static unsigned int cpuid_range_max_leaf(const struct c= puid_table *t, unsigned i case CPUID_EXT_START: return el0 ? el0->max_ext_leaf : 0; case CPUID_TMX_START: return tl0 ? tl0->max_tra_leaf : 0; case CPUID_CTR_START: return cl0 ? cl0->max_cntr_leaf : 0; + case CPUID_LNX_START: return CPUID_LNX_END; default: return 0; } } @@ -305,6 +321,7 @@ cpuid_fill_table(struct cpuid_table *t, const struct cp= uid_parse_entry entries[] { CPUID_EXT_START, CPUID_EXT_END }, { CPUID_TMX_START, CPUID_TMX_END }, { CPUID_CTR_START, CPUID_CTR_END }, + { CPUID_LNX_START, CPUID_LNX_END }, }; =20 for (unsigned int i =3D 0; i < ARRAY_SIZE(ranges); i++) diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index f6a620a03312..e7c07346452e 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -159,6 +159,9 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY ( 0x23, 3, 0x23_3 ), \ CPUID_PARSE_ENTRY ( 0x23, 4, 0x23_4 ), \ CPUID_PARSE_ENTRY ( 0x23, 5, 0x23_5 ), \ + CPUID_PARSE_ENTRY ( 0x4c780001, 0, synthetic ), \ + CPUID_PARSE_ENTRY ( 0x4c780001, 1, synthetic ), \ + CPUID_PARSE_ENTRY ( 0x4c780002, 0, synthetic ), \ CPUID_PARSE_ENTRY ( 0x80000000, 0, 0x80000000 ), \ CPUID_PARSE_ENTRY ( 0x80000001, 0, generic ), \ CPUID_PARSE_ENTRY ( 0x80000002, 0, generic ), \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 631BB38C2B7 for ; Fri, 27 Mar 2026 02:22:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578131; cv=none; b=mkYPnU87tFLdkqqCk/R6k6owi6kGQyQ/VDBUXSJt0uxzb+5MJYbPgnIACAkTaezvORVnDIUSXg9vIeSyoWbb2LaL0UrQtPdYzJIA/99Rmuzf0Kdg3IhDwpzk1pzD/ZHOwS8fwRlmYXj8G9vS0+CpFDiDuextFSmwR4Ga/5APAow= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578131; c=relaxed/simple; bh=NWJxhTrPyemmaLJBtzm7jBfm9qCsSL8Zg5nZ3NFouI8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EuTHyM2mqL7Wf+3dOyO7Ca+80eywTLViCMh579CRWMWHQBsxAUsLbkOxor1C7vzDyiVfvInZNOHQJZfMCGuXPEFdLBTFwkbHh7SED2981IcxiBu7637bqkxVm5vlwFG3n5WkGN1SMA+IFj0ZjOUT8BGVZs3ARBicD3o33htm7Pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=jNCl66Dg; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BdTBr9QK; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="jNCl66Dg"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BdTBr9QK" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LDLNRpHDyvch9f35CIYfvvYvKFQXjZknY9odVNm73dI=; b=jNCl66DgVCqvTzvvp7q/TGn4UOSMllBcvEBfRTTFdKZP62BSpMHKzsUohYufdMpeIxxIbk 6enQDvZf3PVQug19XJSwGsM0c7KP+k88os0/X4Jc/zyEdvvVkDBo9k8uG/eKIu+I82Psj5 PjbLTTRwCcyDxC76SHgIsss52213atiqLM6sSh41lzuHoqtJssuXXHzh/1pgIlQcSWiVAw dulFx0fUYfXMwbiVCj0O/gQBgbBGThw9LkQr/OkX9wl72TZZb5OZefc6d9A0qp0cihs+m4 KUvPNDj5IMM4aQ6mXTA/q/JpbIV9X/Yu384zxNC0o7VBPr01S18V9/jawh3Lyw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578129; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LDLNRpHDyvch9f35CIYfvvYvKFQXjZknY9odVNm73dI=; b=BdTBr9QKAz6XrvxwZLJxmZ7xz4dnrU96BVzY6dKSo1+CCSG7B4PpPiReadBmQStQktpUo9 tkHiq7q/Rqy9haDA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 79/90] x86/cpuid: Introduce a compile-time X86_FEATURE word map Date: Fri, 27 Mar 2026 03:16:33 +0100 Message-ID: <20260327021645.555257-80-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare for routing X86_FEATURE queries to the CPUID tables instead of to cpuinfo_x86::x86_capability[]. The latter will be later removed to make the CPUID tables a "single source of Truth" for all x86 feature state. Build a compile time map from an X86_FEATURE word to its cached CPUID leaf/subleaf register output. Use a compile time table to preserve the feature querying optimizations at . Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 59 +++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 263e82e89f70..6b0790408b85 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -168,9 +168,12 @@ struct leaf_parse_info { * Use an array of storage entries to accommodate CPUID leaves with multip= le subleaves * having the same output format. This is common for hierarchical enumera= tion; e.g., * CPUID(0x4), CPUID(0x12), and CPUID(0x8000001d). + * + * Align all CPUID outputs to unsigned long. They're passed to bitops for= X86_FEATURE + * queries, which require the alignment. */ #define __CPUID_LEAF(_name, _count) \ - struct _name _name[_count]; \ + struct _name _name[_count] __aligned(sizeof(unsigned long));\ struct leaf_parse_info _name##_info =20 /** @@ -267,9 +270,61 @@ struct cpuid_leaves { * * This is to be embedded inside 'struct cpuinfo_x86' to provide parsed and * sanitized CPUID data per CPU. + * + * Align the leaves to unsigned long since their elements are passed to bi= tops + * for X86_FEATURE querying. */ struct cpuid_table { - struct cpuid_leaves leaves; + struct cpuid_leaves leaves __aligned(sizeof(unsigned long)); +}; + +/* + * X86_FEATURE word mappings: + * + * Build a compile-time mapping table from an X86_FEAT= URE + * word to its corresponding cached entry in a CPUID table. + */ + +#define __BUG(n) (NCAPINTS + (n)) + +struct cpuid_cpufeature { + unsigned int leaves_offset; /* Offset from a struct cpuid_leaves instance= */ + unsigned int cpuid_reg; /* Output register: CPUID_EAX -> CPUID_EDX */ }; =20 +#define __cpu_feature_word(_word, _leaf, _subleaf, _reg) \ + [_word] =3D { \ + .leaves_offset =3D offsetof(struct cpuid_leaves, leaf_##_leaf##_##_suble= af),\ + .cpuid_reg =3D _reg, \ + } + +#define CPUID_FEATURE_WORDS_MAP \ +{ \ + /* X86_FEATURE word, Leaf, Subleaf, Output reg */ \ + __cpu_feature_word(0, 0x1, 0, CPUID_EDX), \ + __cpu_feature_word(1, 0x80000001, 0, CPUID_EDX), \ + __cpu_feature_word(2, 0x80860001, 0, CPUID_EDX), \ + __cpu_feature_word(3, 0x4c780001, 0, CPUID_EAX), \ + __cpu_feature_word(4, 0x1, 0, CPUID_ECX), \ + __cpu_feature_word(5, 0xc0000001, 0, CPUID_EDX), \ + __cpu_feature_word(6, 0x80000001, 0, CPUID_ECX), \ + __cpu_feature_word(7, 0x4c780001, 0, CPUID_EBX), \ + __cpu_feature_word(8, 0x4c780001, 0, CPUID_ECX), \ + __cpu_feature_word(9, 0x7, 0, CPUID_EBX), \ + __cpu_feature_word(10, 0xd, 1, CPUID_EAX), \ + __cpu_feature_word(11, 0x4c780001, 0, CPUID_EDX), \ + __cpu_feature_word(12, 0x7, 1, CPUID_EAX), \ + __cpu_feature_word(13, 0x80000008, 0, CPUID_EBX), \ + __cpu_feature_word(14, 0x6, 0, CPUID_EAX), \ + __cpu_feature_word(15, 0x8000000a, 0, CPUID_EDX), \ + __cpu_feature_word(16, 0x7, 0, CPUID_ECX), \ + __cpu_feature_word(17, 0x4c780001, 1, CPUID_EAX), \ + __cpu_feature_word(18, 0x7, 0, CPUID_EDX), \ + __cpu_feature_word(19, 0x8000001f, 0, CPUID_EAX), \ + __cpu_feature_word(20, 0x80000021, 0, CPUID_EAX), \ + __cpu_feature_word(21, 0x4c780001, 1, CPUID_EBX), \ + __cpu_feature_word(__BUG(0), 0x4c780002, 0, CPUID_EAX), \ + __cpu_feature_word(__BUG(1), 0x4c780002, 0, CPUID_EBX), \ +} + #endif /* _ASM_X86_CPUID_TYPES_H */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7919638D6B0 for ; Fri, 27 Mar 2026 02:22:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578134; cv=none; b=hQE9dwJSOOMg75hgJxuhUxcBtAW87biH8SMCGulvLkzOjha/AwJFWSnVyfPVuz5BqY2sbFkcUaMvNj2bUrXFjygMu2ziAiGDslKEQpF/MNHgJA0wea0GIaAYRPdcsb0HBQcLuLApPDKBrpPtQjj4A/ui7x53RJjJAK7alHtzdjc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578134; c=relaxed/simple; bh=H2P2x2GCC1j+u0lfoI7QZrY4dwB6yoLIf1txXLoMAqg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r8SF4k/WCqqVRceVbUpENSBPUj9L9hQ/a7/aHg2ZsN6w7ppAGbTOPo05eVZePUtSOEZkp30MDt+Ymx9BRA1BhATCEp7QDKDg9CozaS3FOk1GcyL1ILHFpqpPAkKyGKEzvF3QU8b39Z9sjy2L2ttKPQmu6tpkeyydn2yI3a9p2X8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=yzIIGQFj; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wkO3oi0L; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="yzIIGQFj"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wkO3oi0L" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 80/90] x86/cpuid: Introduce X86_FEATURE and CPUID word APIs Date: Fri, 27 Mar 2026 03:16:34 +0100 Message-ID: <20260327021645.555257-81-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce helper APIs to translate: - X86_FEATURE symbols from - CPUID word indices from into offsets within the cached CPUID tables. These helpers will be used to route all X86_FEATURE and CPUID word querying into the centralized CPUID tables, instead of their current routing to cpuinfo_x86::x86_capability[]. Thus removing the latter from the kernel. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 125 +++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 611ee8596115..b60a408c8fec 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -504,6 +504,131 @@ static inline bool cpuid_amd_hygon_has_l3_cache(struc= t cpuinfo_x86 *c) return el6 && el6->l3_assoc; } =20 +/* + * X86_FEATURE mapping: + * + * These macros are for the internal X86_FEATURE queryi= ng. + * Do everything at compile-time to preserve that header's query optimizat= ions. + * + * @_feature: X86_FEATURE symbol + */ + +#define __feature_word(_feature) ((_feature) / 32) +#define __feature_word_bit(_feature) ((_feature) % 32) + +/* + * Return cached CPUID output offset for @_feature; within 'struct cpuid_l= eaves'. + */ +#define __feature_byte_offset(_feature) \ +({ \ + struct cpuid_cpufeature ____map[] =3D CPUID_FEATURE_WORDS_MAP; \ + unsigned int ____word =3D __feature_word(_feature); \ + \ + ____map[____word].leaves_offset; \ +}) + +/* + * Return CPUID output register for @_feature; i.e., CPUID_EAX -> CPUID_ED= X. + */ +#define __feature_register(_feature) \ +({ \ + struct cpuid_cpufeature ____map[] =3D CPUID_FEATURE_WORDS_MAP; \ + unsigned int ____word =3D __feature_word(_feature); \ + \ + ____map[____word].cpuid_reg; \ +}) + +/* + * Return bit offset for @_feature. This is for bitops, where the offset = is + * relative to ((u8 *)&cpuid_leaves + __feature_byte_offset(@_feature)). + */ +#define __feature_bit_offset(_feature) \ +({ \ + 32 * __feature_register(_feature) + __feature_word_bit(_feature); \ +}) + +/** + * cpuid_feature_byte_offset() - Return X86_FEATURE byte offset + * @_feature: X86_FEATURE symbol from + * + * Return CPUID table 'struct cpuid_leaves' byte offset, for @_feature. + */ +#define cpuid_feature_byte_offset(_feature) __feature_byte_offset(_feature) + +/** + * cpuid_feature_bitmap() - Return X86_FEATURE bitmap + * @_cpuinfo: CPU capability structure ('struct cpuinfo_x86') + * @_feature: X86_FEATURE symbol from + * + * Return CPUID table bitmap, within @_cpuinfo, for @_feature. The return= ed + * bitmap is unsigned long aligned, for bitops access. + */ +#define cpuid_feature_bitmap(_cpuinfo, _feature) \ + (unsigned long *)((u8 *)&(_cpuinfo)->cpuid.leaves + __feature_byte_offset= (_feature)) + +/** + * cpuid_feature_bit_offset() + * @_feature: X86_FEATURE symbol from + * + * Return CPUID table bit offset, for @_feature, within the bitmap returne= d by + * cpuid_feature_bitmap(). + */ +#define cpuid_feature_bit_offset(_feature) __feature_bit_offset(_feature) + +/* + * CPUID word mapping: + */ + +static inline u32 *__cpuid_word_address(struct cpuinfo_x86 *c, u16 word) +{ + u16 feature =3D word * 32; + + return (u32 *)cpuid_feature_bitmap(c, feature) + __feature_register(featu= re); +} + +/** + * cpuid_word() - Return the CPUID word's raw u32 value + * @c: CPU capability structure ('struct cpuinfo_x86') + * @word: CPUID word number as defined at "enum cpuid_leafs" + */ +static inline u32 cpuid_word(struct cpuinfo_x86 *c, u16 word) +{ + return *__cpuid_word_address(c, word); +} + +/** + * cpuid_word_set() - Set the CPUID word's raw u32 value + * @c: CPU capability structure ('struct cpuinfo_x86') + * @word: CPUID word number as defined at "enum cpuid_leafs" + * @val: Raw u32 value to set the word to + */ +static inline void cpuid_word_set(struct cpuinfo_x86 *c, u16 word, u32 val) +{ + *__cpuid_word_address(c, word) =3D val; +} + +/** + * cpuid_word_set_bits() - Set bits at CPUID word according to passed map + * @c: CPU capability structure ('struct cpuinfo_x86') + * @word: CPUID word number as defined at "enum cpuid_leafs" + * @map: Map of bits to be set + */ +static inline void cpuid_word_set_bits(struct cpuinfo_x86 *c, u16 word, u3= 2 map) +{ + *__cpuid_word_address(c, word) |=3D map; +} + +/** + * cpuid_word_clear_bits() - Clear bits at CPUID word according to passed = map + * @c: CPU capability structure ('struct cpuinfo_x86') + * @word: CPUID word number as defined at "enum cpuid_leafs" + * @map: Map of bits to be cleared + */ +static inline void cpuid_word_clear_bits(struct cpuinfo_x86 *c, u16 word, = u32 map) +{ + *__cpuid_word_address(c, word) &=3D ~map; +} + /* * CPUID parser exported APIs: */ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95A7938F22D for ; Fri, 27 Mar 2026 02:22:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578139; cv=none; b=eQ4g+Nw6nDUhFIeLpEKLC3d4Xr5iv+bEZY6o4k9ycYD8rODhoqZNk3ib+ahvMIrIipBiTmwvJ3bI99ilIOfQxOcOwC1dRR+b8SZxQ+R2/6/nAFtsYFV3Xj52nVN+Y2JlLoujXZwhA9DP4SyqmvOr+NS6RWEZLYR2gLUTm/sz1JA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578139; c=relaxed/simple; bh=UGzU1mq0mWTa3MC6NaQ1zDuSMBjlUw2dx1/E5mRiol8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q/17PRqVdycHh96TWe+e8/s8CvJ8vHQB8mOhpWWicmXF7DAndYFq0TwCyOVH2Ryr/1Yz5tGB+joEtBsgHmE96jOZfTgVeIGuF4kpHCFulM2pt/JR6410hoczgNx0keSQ556xs5UP9B8hyGFafwg+tAtR5HPKVQeNP3Fa5v1x6jA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=csX6smVV; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=c+mj4E82; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="csX6smVV"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="c+mj4E82" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578135; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DXjrn8JaZj55Y3q5GBHuBALmB2iH7f42lYVO8MWGAqs=; b=csX6smVVqU8dVFeANDf4oVE/WqfJGsfwdxGccsu01oM3RwMI+Mhb9/frKKykSl8P3vuTYY MKiqPNwsF7ljjsXn/N/aX1D6IWasOKfZgYplyAfWDGDFkwfEOYQtnOwYQsWWy2X4JvtvwH H8YqrgOM9upbrNpdghzWtdsSQpYNkx6l/No4dX64EeGu1nlttzYjQFm+GG1DALhwEvnkJ5 ml9CgFGcYoOmCxm7iz2tB1Rp6RuzBfYt6HpVQVtSHiNXJIlJbQzypiMfmKLb7SeLAUE6Mr mE/T36xeYYzepYT79bwm0XVPQB0YunRaSXbZDfQhD8gcHaK3hxPgHYHa+SoQFA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578135; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=DXjrn8JaZj55Y3q5GBHuBALmB2iH7f42lYVO8MWGAqs=; b=c+mj4E82tg6Mi/6J6Xu2BgGQizDC3Vs5kyuQP7tNoyi2miIUsCCOpN1Dg+cMQN42f7wnnj 7F40lfI0uCaEGWAg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 81/90] x86/percpu: Add offset argument to x86_this_cpu_test_bit() Date: Fri, 27 Mar 2026 03:16:35 +0100 Message-ID: <20260327021645.555257-82-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" x86_this_cpu_test_bit() assumes that the queried bitmap starts at the base address of the percpu object. For X86_FEATURE bitops, this matches the current cpuinfo_x86::x86_capability[] layout. Upcoming changes though will route all X86_FEATURE queries to the CPUID tables, where the bitmap resides at the per-CPU CPUID table plus an offset. Add an offset argument to x86_this_cpu_test_bit(). Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpufeature.h | 2 +- arch/x86/include/asm/percpu.h | 34 ++++++++++++++++++------------- 2 files changed, 21 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 520949560138..b12bde4986b5 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -56,7 +56,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; =20 #define this_cpu_has(bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ - x86_this_cpu_test_bit(bit, cpu_info.x86_capability)) + x86_this_cpu_test_bit(bit, cpu_info.x86_capability, 0)) =20 /* * This is the default CPU features testing macro to use in code. diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h index 409981468cba..8a36f0bb979d 100644 --- a/arch/x86/include/asm/percpu.h +++ b/arch/x86/include/asm/percpu.h @@ -89,15 +89,17 @@ #endif /* CONFIG_SMP */ =20 #if defined(CONFIG_USE_X86_SEG_SUPPORT) && defined(USE_TYPEOF_UNQUAL) -# define __my_cpu_type(var) typeof(var) -# define __my_cpu_ptr(ptr) (ptr) -# define __my_cpu_var(var) (var) +# define __my_cpu_type(var) typeof(var) +# define __my_cpu_ptr(ptr) (ptr) +# define __my_cpu_ptr_off(ptr, off) (typeof(ptr))((uintptr_t)(ptr) + (off)) +# define __my_cpu_var(var) (var) =20 -# define __percpu_qual __percpu_seg_override +# define __percpu_qual __percpu_seg_override #else -# define __my_cpu_type(var) typeof(var) __percpu_seg_override -# define __my_cpu_ptr(ptr) (__my_cpu_type(*(ptr))*)(__force uintptr_t)(ptr) -# define __my_cpu_var(var) (*__my_cpu_ptr(&(var))) +# define __my_cpu_type(var) typeof(var) __percpu_seg_override +# define __my_cpu_ptr(ptr) (__my_cpu_type(*(ptr))*)(__force uintptr_t)(pt= r) +# define __my_cpu_ptr_off(ptr, off) (__my_cpu_type(*(ptr))*)((__force uint= ptr_t)(ptr) + (off)) +# define __my_cpu_var(var) (*__my_cpu_ptr(&(var))) #endif =20 #define __force_percpu_arg(x) __force_percpu_prefix "%" #x @@ -570,29 +572,33 @@ do { \ */ #define this_cpu_read_stable(pcp) __pcpu_size_call_return(this_cpu_read_= stable_, pcp) =20 -#define x86_this_cpu_constant_test_bit(_nr, _var) \ +#define x86_this_cpu_constant_test_bit(_nr, _var, _offset) \ ({ \ unsigned long __percpu *addr__ =3D \ - (unsigned long __percpu *)&(_var) + BIT_WORD(_nr); \ + (unsigned long __percpu *)((u8 __percpu *)&(_var) + (_offset)) +\ + BIT_WORD(_nr); \ + \ + /* Ensure bitops safety */ \ + BUILD_BUG_ON(!IS_ALIGNED((unsigned long)(_offset), sizeof(unsigned long))= );\ \ !!(BIT_MASK(_nr) & raw_cpu_read(*addr__)); \ }) =20 -#define x86_this_cpu_variable_test_bit(_nr, _var) \ +#define x86_this_cpu_variable_test_bit(_nr, _var, _offset) \ ({ \ bool oldbit; \ \ asm volatile("btl %[nr], " __percpu_arg([var]) \ : "=3D@ccc" (oldbit) \ - : [var] "m" (__my_cpu_var(_var)), \ + : [var] "m" (*__my_cpu_ptr_off(&(_var), _offset)), \ [nr] "rI" (_nr)); \ oldbit; \ }) =20 -#define x86_this_cpu_test_bit(_nr, _var) \ +#define x86_this_cpu_test_bit(_nr, _var, _offset) \ (__builtin_constant_p(_nr) \ - ? x86_this_cpu_constant_test_bit(_nr, _var) \ - : x86_this_cpu_variable_test_bit(_nr, _var)) + ? x86_this_cpu_constant_test_bit(_nr, _var, _offset) \ + : x86_this_cpu_variable_test_bit(_nr, _var, _offset)) =20 =20 #include --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C74E938F248 for ; Fri, 27 Mar 2026 02:22:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578141; cv=none; b=PH6p/AkEoiwDjvodcbBc9/Nate0ENXd3QJ9Hj/ywszDNRnLpkUNrjmlzC13GYkV6Bc3URx1wvcwETIecL+xhU9zK2aHPwMgnr51c8U3cwI4uy0FTwPcvrN4HxkU7t6R2atadwoEHXXfr7x8nYbR3OCoFiblInTr2i9PUmidzsBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578141; c=relaxed/simple; bh=sE08eqiU2xZOGqhKPBhyfzLZOLKANlL3MRoJtZaBHhg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d9D23zBe98yJ4FEo3pcmILLf0Cfa7xK9DMv8lFOdV4tnqHtzO0ENdcY/lcudAH7Xrv4iUF4gG9cnAsvBzM4d0Jyo4aQe/N00WbVqt2jz9spXvuUak7xdv8twprAAhWWHm/DzCACbb2BKrK9SwUHhhZuyRTimrS07LuYm5l2WiuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VAL0CxNE; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=6SvnV/2V; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VAL0CxNE"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="6SvnV/2V" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 82/90] x86/cpufeature: Factor out a __static_cpu_has() helper Date: Fri, 27 Mar 2026 03:16:36 +0100 Message-ID: <20260327021645.555257-83-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Later changes will route X86_FEATURE querying to centralized CPUID tables. In that case, the X86_FEATURE's bit value from is different from the bitmap's own bit value to be checked by the fallback capability-byte "testb" check. Factor the asm goto fallback code out of _static_cpu_has() and into __static_cpu_has(). Pass the X86_FEATURE bit, and the bitmap offset bit, separately. No functional change intended. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpufeature.h | 44 +++++++++++++++++-------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index b12bde4986b5..48643b4b1e24 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -90,29 +90,33 @@ void check_cpufeature_deps(struct cpuinfo_x86 *c); #define setup_force_cpu_bug(bit) setup_force_cpu_cap(bit) =20 /* - * Do not use an "m" constraint for [cap_byte] here: gcc doesn't know - * that this is only used on a fallback path and will sometimes cause - * it to manifest the address of boot_cpu_data in a register, fouling - * the mainline (post-initialization) code. + * Helper macro for CPU feature detection with alternative instructions. + * + * Do not use an "m" constraint for [cap_byte]: GCC does not know that thi= s is + * only used on a fallback path and will sometimes manifest the address of + * boot_cpu_data in a register, fouling the mainline post-initialization c= ode. */ +#define __static_cpu_has(_feature_bit, _bitmap, _bitmap_bit) \ + asm goto(ALTERNATIVE_TERNARY("jmp 6f", %c[feature], "", "jmp %l[t_no]") \ + ".pushsection .altinstr_aux,\"ax\"\n" \ + "6:\n" \ + ANNOTATE_DATA_SPECIAL "\n" \ + " testb %[bitnum], %a[cap_byte]\n" \ + " jnz %l[t_yes]\n" \ + " jmp %l[t_no]\n" \ + ".popsection\n" \ + : : [feature] "i" (_feature_bit), \ + [bitnum] "i" (1 << ((_bitmap_bit) & 7)), \ + [cap_byte] "i" (&((const char *)(_bitmap))[(_bitmap_bit) >> 3]) \ + : : t_yes, t_no); \ + t_yes: \ + return true; \ + t_no: \ + return false \ + static __always_inline bool _static_cpu_has(u16 bit) { - asm goto(ALTERNATIVE_TERNARY("jmp 6f", %c[feature], "", "jmp %l[t_no]") - ".pushsection .altinstr_aux,\"ax\"\n" - "6:\n" - ANNOTATE_DATA_SPECIAL "\n" - " testb %[bitnum], %a[cap_byte]\n" - " jnz %l[t_yes]\n" - " jmp %l[t_no]\n" - ".popsection\n" - : : [feature] "i" (bit), - [bitnum] "i" (1 << (bit & 7)), - [cap_byte] "i" (&((const char *)boot_cpu_data.x86_capability)[bit >= > 3]) - : : t_yes, t_no); -t_yes: - return true; -t_no: - return false; + __static_cpu_has(bit, &boot_cpu_data.x86_capability, bit); } =20 #define static_cpu_has(bit) \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C72AE390232 for ; Fri, 27 Mar 2026 02:22:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578144; cv=none; b=tBVcbHmvAXGsK/gRRuFgarjtfxOnuKALSMaQ3gV1QfLY/msZ540pqwFd0TvhiM41sH/JSVFDvaKrmJlg/wsDek8PSHXIkzKgVEiOjMuooUuc7R+Or9joXF2K0ajlrWv1slNMqoee3D0FEdhePPtuAteOobWMya2z7czrwk+oOSU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578144; c=relaxed/simple; bh=6u56gGqiFSlQULYqPbCpUcByvv1U0v2TQGZ0PDDjEPE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d+/4PX2OxEX3OZfLON7fg9+X3M3BSTL4HWvWAuya9CscwyJ6ukKFSrX/N9kNcdArDlwkF0wVUgCv7IiJbkMeGVLHrhD8Tt/yBBckQoOSDYnZSTe1NWlBS/cK1kEEqLrW17ug19FfC0FEeyU7Br0bSIzZsMbgJCiEMem5crOLqO4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Tc9hRJhR; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GZqaPIE8; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Tc9hRJhR"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GZqaPIE8" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 83/90] x86/asm/32: Cache CPUID(0x1).EDX in cpuid_table Date: Fri, 27 Mar 2026 03:16:37 +0100 Message-ID: <20260327021645.555257-84-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The x86-32 early boot code initializes new_cpu_data from the boot CPU and stores CPUID(0x1).EDX in cpuinfo_x86::x86_capability[]. Introduce the CPUINFO_CPUID_0x1_EDX asm-offset, and store %edx in the cached CPUID table entry for new_cpu_data. This prepares for the removal of cpuinfo_x86::x86_capability[]. Note that the definition of CPUINFO_CPUID_0x1_EDX is much more complex than X86_CAPABILITY, even though both are used as: movl $1,%eax cpuid ... movl %edx,X86_CAPABILITY movl %edx,CPUINFO_CPUID_0x1_EDX This is because CPUID(0x1).EDX is conveniently the first word of cpuinfo_x86::x86_capability[], but not of cpuinfo_x86::cpuid_table. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/asm-offsets.c | 5 +++++ arch/x86/kernel/head_32.S | 2 ++ 2 files changed, 7 insertions(+) diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 081816888f7a..0bc36d617801 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -40,6 +40,11 @@ static void __used common(void) OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level); OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability); OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id); + DEFINE(CPUINFO_CPUID_0x1_EDX, + offsetof(struct cpuinfo_x86, cpuid) + + offsetof(struct cpuid_table, leaves) + + offsetof(struct cpuid_leaves, leaf_0x1_0) + + offsetof(struct cpuid_regs, edx)); =20 BLANK(); OFFSET(TASK_threadsp, task_struct, thread.sp); diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index 80ef5d386b03..6dcc27014641 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -43,6 +43,7 @@ #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id +#define X86_FEATUREFLAG new_cpu_data+CPUINFO_CPUID_0x1_EDX =20 /* * Worst-case size of the kernel mapping we need to make: @@ -263,6 +264,7 @@ SYM_FUNC_START(startup_32_smp) andb $0x0f,%cl # mask mask revision movb %cl,X86_STEPPING movl %edx,X86_CAPABILITY + movl %edx,X86_FEATUREFLAG =20 .Lis486: movl $0x50022,%ecx # set AM, WP, NE and MP --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDEDC391E50 for ; Fri, 27 Mar 2026 02:22:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578147; cv=none; b=fVRqFNSZN6V8Ca0tlUvD+j2/gQ03iyXbNClmhytprk+3VVgLg1T3WCNXREX678jUBpGDO9oqqVuNh3tecouNuteOcyTr8JtSv8Gysa9erwG+P/difll/mZpV9peePiIKIEPldmQQ77wlDniOXbYNDlDD1nNeS9b+GV0wgccqRHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578147; c=relaxed/simple; bh=ZC6cayXPQB++VGU7lbfwTnlHNRagvHsVZIHkEwJvNow=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r9DIYOMakEBPTuurfQgT+sbcwMyAIv7+n+0lqzmEKl3ynmgBpdo6cUgIJoNumQ0cn97ZNqEKSwSKxUCteE+xy7cZtg73lowF0bvJQ+4hQVSpTpptahius87YCmV6sCK2TnR9Hg3Neqlm3Ldt87QefSzdS17+eMHnKsRxhal//+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=IAt71GAd; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9XUEPOQh; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="IAt71GAd"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9XUEPOQh" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578144; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=29BHdsmcC1HkjHvSYOV5p+PktPO/Lj1IRStMOz+HANo=; b=IAt71GAdMC5Mosk6wjOYlZHDxhBWMFw1mmx5wzPjzMtMXH0qht5ZYU4VHh4SiupCOEvwF/ 2PmsfkwxsHioM+gUWLCCYLhBbRwVd/sM846d0BXpU6hU3h53WKqSJWSL05SGYEhdwBfts3 XGly2dlySP/2GdJf54Ks/V6jsTffXohXfzyOpNz6PPHj8LTy/UOf+i9v+3ZLqH39TDEGg4 5QQvdbKcZaGnALqFy0x/viNwLmw2PDrnmN7Ky5MZoVYvdmZcmQmBPF3c9u/YXG6C6lbJnI a2+Huw5zKs+oAVhv8tlh/5CP2pzpWZEssvjVjDre6TgEoOuu1KhtZcNTnyYymA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578144; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=29BHdsmcC1HkjHvSYOV5p+PktPO/Lj1IRStMOz+HANo=; b=9XUEPOQhdScxHBTXM7dU0V5do0W5J6gcnmox1UmmwT37008/mmuZW7KKWBp0RlUssRnP6R a2VgM4GnXSe4bADA== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 84/90] x86: Route all feature queries to the CPUID tables Date: Fri, 27 Mar 2026 03:16:38 +0100 Message-ID: <20260327021645.555257-85-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use the CPUID API's cpuid_feature_*() and cpuid_word_*() helpers to route all feature querying to the CPUID tables instead of to x86_capability[]. This allows the CPUID tables to act as a single source of truth for x86 feature state; both hardware-backed and synthetic. Do this routing in one shot, not to fragment x86 state tracking between CPUID tables and x86_capability[]. The latter will be fully removed. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpufeature.h | 12 ++++++--- arch/x86/include/asm/elf.h | 2 +- arch/x86/kernel/cpu/common.c | 41 +++++++++++++++++-------------- arch/x86/kernel/cpu/cpuid-deps.c | 2 +- arch/x86/kernel/mpparse.c | 2 +- arch/x86/kvm/cpuid.c | 3 +-- 6 files changed, 34 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufe= ature.h index 48643b4b1e24..58d5e4f3891c 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -10,6 +10,7 @@ #include #include #include +#include =20 enum cpuid_leafs { @@ -48,7 +49,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; #define x86_bug_flag(flag) x86_bug_flags[flag] =20 #define test_cpu_cap(c, bit) \ - arch_test_bit(bit, (unsigned long *)((c)->x86_capability)) + arch_test_bit(cpuid_feature_bit_offset(bit), cpuid_feature_bitmap(c, bit)) =20 #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ @@ -56,7 +57,7 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; =20 #define this_cpu_has(bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ - x86_this_cpu_test_bit(bit, cpu_info.x86_capability, 0)) + x86_this_cpu_test_bit(cpuid_feature_bit_offset(bit), cpu_info.cpuid.leav= es, cpuid_feature_byte_offset(bit))) =20 /* * This is the default CPU features testing macro to use in code. @@ -72,7 +73,8 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; =20 #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) =20 -#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capabi= lity)) +#define set_cpu_cap(c, bit) \ + set_bit(cpuid_feature_bit_offset(bit), cpuid_feature_bitmap(c, bit)) =20 extern void setup_clear_cpu_cap(unsigned int bit); extern void clear_cpu_cap(struct cpuinfo_x86 *c, unsigned int bit); @@ -116,7 +118,9 @@ void check_cpufeature_deps(struct cpuinfo_x86 *c); =20 static __always_inline bool _static_cpu_has(u16 bit) { - __static_cpu_has(bit, &boot_cpu_data.x86_capability, bit); + __static_cpu_has(bit, + cpuid_feature_bitmap(&boot_cpu_data, bit), + cpuid_feature_bit_offset(bit)); } =20 #define static_cpu_has(bit) \ diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h index 2ba5f166e58f..33deebdde48a 100644 --- a/arch/x86/include/asm/elf.h +++ b/arch/x86/include/asm/elf.h @@ -239,7 +239,7 @@ extern int force_personality32; instruction set this CPU supports. This could be done in user space, but it's not easy, and we've already done it here. */ =20 -#define ELF_HWCAP (boot_cpu_data.x86_capability[CPUID_1_EDX]) +#define ELF_HWCAP cpuid_word(&boot_cpu_data, CPUID_1_EDX) =20 extern u32 elf_hwcap2; =20 diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index ece5a59124f5..98e53f5aa41d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -968,11 +968,9 @@ void cpu_detect(struct cpuinfo_x86 *c) =20 static void apply_forced_caps(struct cpuinfo_x86 *c) { - int i; - - for (i =3D 0; i < NCAPINTS + NBUGINTS; i++) { - c->x86_capability[i] &=3D ~cpu_caps_cleared[i]; - c->x86_capability[i] |=3D cpu_caps_set[i]; + for (int i =3D 0; i < NCAPINTS + NBUGINTS; i++) { + cpuid_word_clear_bits(c, i, cpu_caps_cleared[i]); + cpuid_word_set_bits(c, i, cpu_caps_set[i]); } } =20 @@ -2002,8 +2000,6 @@ static void generic_identify(struct cpuinfo_x86 *c) */ static void identify_cpu(struct cpuinfo_x86 *c) { - int i; - c->loops_per_jiffy =3D loops_per_jiffy; c->x86_cache_size =3D 0; c->x86_vendor =3D X86_VENDOR_UNKNOWN; @@ -2112,13 +2108,13 @@ static void identify_cpu(struct cpuinfo_x86 *c) * executed, c =3D=3D &boot_cpu_data. */ if (c !=3D &boot_cpu_data) { - /* AND the already accumulated flags with these */ - for (i =3D 0; i < NCAPINTS; i++) - boot_cpu_data.x86_capability[i] &=3D c->x86_capability[i]; + /* Clear boot_cpu_data features that are not on this CPU */ + for (int i =3D 0; i < NCAPINTS; i++) + cpuid_word_clear_bits(&boot_cpu_data, i, ~cpuid_word(c, i)); =20 - /* OR, i.e. replicate the bug flags */ - for (i =3D NCAPINTS; i < NCAPINTS + NBUGINTS; i++) - c->x86_capability[i] |=3D boot_cpu_data.x86_capability[i]; + /* Replicate boot_cpu_data's bug flags to this CPU */ + for (int i =3D NCAPINTS; i < NCAPINTS + NBUGINTS; i++) + cpuid_word_set_bits(c, i, cpuid_word(&boot_cpu_data, i)); } =20 ppin_init(c); @@ -2521,12 +2517,17 @@ void cpu_init(void) */ void store_cpu_caps(struct cpuinfo_x86 *curr_info) { + const struct leaf_0x0_0 *l0; + /* Reload CPUID max function as it might've changed. */ - curr_info->cpuid_level =3D cpuid_eax(0); + cpuid_refresh_leaf(curr_info, 0x0); + l0 =3D cpuid_leaf(curr_info, 0x0); + if (l0) + curr_info->cpuid_level =3D l0->max_std_leaf; =20 /* Copy all capability leafs and pick up the synthetic ones. */ - memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability, - sizeof(curr_info->x86_capability)); + for (int i =3D 0; i < NCAPINTS + NBUGINTS; i++) + cpuid_word_set(curr_info, i, cpuid_word(&boot_cpu_data, i)); =20 /* Get the hardware CPUID leafs */ get_cpu_cap(curr_info); @@ -2556,10 +2557,12 @@ void microcode_check(struct cpuinfo_x86 *prev_info) =20 store_cpu_caps(curr_info); =20 - if (!memcmp(&prev_info->x86_capability, &curr_info->x86_capability, - sizeof(prev_info->x86_capability))) - return; + for (int i =3D 0; i < NCAPINTS + NBUGINTS; i++) + if (cpuid_word(prev_info, i) !=3D cpuid_word(curr_info, i)) + goto err; =20 + return; +err: pr_warn("x86/CPU: CPU features have changed after loading microcode, but = might not take effect.\n"); pr_warn("x86/CPU: Please consider either early loading through initrd/bui= lt-in or a potential BIOS update.\n"); } diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 146f6f8b0650..78374450374a 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -106,7 +106,7 @@ static inline void clear_feature(struct cpuinfo_x86 *c,= unsigned int feature) clear_cpu_cap(&boot_cpu_data, feature); set_bit(feature, (unsigned long *)cpu_caps_cleared); } else { - clear_bit(feature, (unsigned long *)c->x86_capability); + clear_bit(cpuid_feature_bit_offset(feature), cpuid_feature_bitmap(c, fea= ture)); } } =20 diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c index 4a1b1b28abf9..a66f22db640f 100644 --- a/arch/x86/kernel/mpparse.c +++ b/arch/x86/kernel/mpparse.c @@ -384,7 +384,7 @@ static inline void __init construct_default_ISA_mptable= (int mpc_default_type) processor.cpuflag =3D CPU_ENABLED; processor.cpufeature =3D (boot_cpu_data.x86 << 8) | (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_stepping; - processor.featureflag =3D boot_cpu_data.x86_capability[CPUID_1_EDX]; + processor.featureflag =3D cpuid_word(&boot_cpu_data, CPUID_1_EDX); processor.reserved[0] =3D 0; processor.reserved[1] =3D 0; for (i =3D 0; i < 2; i++) { diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index efc155e1da10..161fa2b23bdb 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -704,7 +704,6 @@ static __always_inline u32 raw_cpuid_get(struct cpuid_r= eg cpuid) do { \ const struct cpuid_reg cpuid =3D x86_feature_cpuid(leaf * 32); \ const u32 __maybe_unused kvm_cpu_cap_init_in_progress =3D leaf; \ - const u32 *kernel_cpu_caps =3D boot_cpu_data.x86_capability; \ u32 kvm_cpu_cap_passthrough =3D 0; \ u32 kvm_cpu_cap_synthesized =3D 0; \ u32 kvm_cpu_cap_emulated =3D 0; \ @@ -715,7 +714,7 @@ do { \ kvm_cpu_caps[leaf] =3D kvm_cpu_cap_features; \ \ if (leaf < NCAPINTS) \ - kvm_cpu_caps[leaf] &=3D kernel_cpu_caps[leaf]; \ + kvm_cpu_caps[leaf] &=3D cpuid_word(&boot_cpu_data, leaf);\ \ kvm_cpu_caps[leaf] |=3D kvm_cpu_cap_passthrough; \ kvm_cpu_caps[leaf] &=3D (raw_cpuid_get(cpuid) | \ --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDF7B3921D0 for ; Fri, 27 Mar 2026 02:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578151; cv=none; b=sZzQUm4LAVZR83paiyjuRY+HseWE50ExaryDlxIhtjfoQhzTjRB1TGIco0lEQT8LoRigUsN9zFzLqv9CaKRbU3/mhDLUPHtbIiRlcBUtH1cVbqq89/Nn+DmbFyf0+ZK6HM2k6cEye66LIFrR0cV7fhtaH5XOLa+wfZLKyYa/Clk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578151; c=relaxed/simple; bh=NcyHq7OCmwiFaPHG91BMY6vz5YdXWgJNRJb1ugfFLkw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tV5yCSeMjZPaEWtleRbjBhESFI/5ubB8pPL9PPKz3Q1tHu/v6+5kc7IpVCsUC76r97y+5oVXdTLNpxMh5Oif3nXDnTnikmiQFwTH1NzOKwiu9uwAMPdA03IF2RvZZSgLtoPIe5v7TeYVbwP9tTKGFO7hWxq98ZBV+pvqhCjEsRw= ARC-Authentication-Results: i=1; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578147; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eVM/2a8qsyfJPHaCxnwzGObirqjcz/jVYuSOKlyUg48=; b=CPb6kTPaRCRNyhGCnUwVoBMYCBSrzurpQjhU412CXiTZXBmQD3OTrW2ZYmKiO/5jmy0QQI DPgpf1+QNzUYhl9ZK/u2f+RzD7J8SbulBn46Hb19fd5+97r8jZl2DBSRiWxwcp2WSxGE0q BJ+usOuJaqDZgVOUrGhT7zOn+J9O6KD/Pw3yJvqNilueLELCBac10ERje1WcpgouSUstxw DiI87r0mxGqC3NbxAqptbk/vla6kPd/2g/6OqpPMTv3OMGPPAqxeGq1u8888+Oh6Mus2cp Tue9//CLBhbOY9SR+7Kcoh54e2V+U1/SHw+qlPAyFnZn56mmvwAohdABvPp1VQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578147; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eVM/2a8qsyfJPHaCxnwzGObirqjcz/jVYuSOKlyUg48=; b=5s7+3XQZ5lwG1Czyfvi+cvMel8m9Wk5SIBWSb2nGgPYY4Pnz057FXbdAZiuh06ERGo6Z6E n1ZCQDNSzBMiWuBg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 85/90] x86/cpu: Remove x86_capability[] and x86_power initialization Date: Fri, 27 Mar 2026 03:16:39 +0100 Message-ID: <20260327021645.555257-86-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X86_FEATURE queries are now routed to the CPUID tables instead of to x86_capability[]. x86_power call sites have all been converted to parsed CPUID(0x80000007) access. Remove all direct CPUID queries which populate x86_capability[] and x86_power. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 58 ------------------------------------ 1 file changed, 58 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 98e53f5aa41d..4c2739f31e3d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1018,70 +1018,12 @@ static void init_speculation_control(struct cpuinfo= _x86 *c) void get_cpu_cap(struct cpuinfo_x86 *c) { const struct leaf_0x80000000_0 *el0; - u32 eax, ebx, ecx, edx; =20 cpuid_scan_cpu(c); =20 - /* Intel-defined flags: level 0x00000001 */ - if (c->cpuid_level >=3D 0x00000001) { - cpuid(0x00000001, &eax, &ebx, &ecx, &edx); - - c->x86_capability[CPUID_1_ECX] =3D ecx; - c->x86_capability[CPUID_1_EDX] =3D edx; - } - - /* Thermal and Power Management Leaf: level 0x00000006 (eax) */ - if (c->cpuid_level >=3D 0x00000006) - c->x86_capability[CPUID_6_EAX] =3D cpuid_eax(0x00000006); - - /* Additional Intel-defined flags: level 0x00000007 */ - if (c->cpuid_level >=3D 0x00000007) { - cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx); - c->x86_capability[CPUID_7_0_EBX] =3D ebx; - c->x86_capability[CPUID_7_ECX] =3D ecx; - c->x86_capability[CPUID_7_EDX] =3D edx; - - /* Check valid sub-leaf index before accessing it */ - if (eax >=3D 1) { - cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx); - c->x86_capability[CPUID_7_1_EAX] =3D eax; - } - } - - /* Extended state features: level 0x0000000d */ - if (c->cpuid_level >=3D 0x0000000d) { - cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx); - - c->x86_capability[CPUID_D_1_EAX] =3D eax; - } - el0 =3D cpuid_leaf(c, 0x80000000); c->extended_cpuid_level =3D el0 ? el0->max_ext_leaf : 0; =20 - if (c->extended_cpuid_level >=3D 0x80000001) { - cpuid(0x80000001, &eax, &ebx, &ecx, &edx); - - c->x86_capability[CPUID_8000_0001_ECX] =3D ecx; - c->x86_capability[CPUID_8000_0001_EDX] =3D edx; - } - - if (c->extended_cpuid_level >=3D 0x80000007) - c->x86_power =3D cpuid_edx(0x80000007); - - if (c->extended_cpuid_level >=3D 0x80000008) { - cpuid(0x80000008, &eax, &ebx, &ecx, &edx); - c->x86_capability[CPUID_8000_0008_EBX] =3D ebx; - } - - if (c->extended_cpuid_level >=3D 0x8000000a) - c->x86_capability[CPUID_8000_000A_EDX] =3D cpuid_edx(0x8000000a); - - if (c->extended_cpuid_level >=3D 0x8000001f) - c->x86_capability[CPUID_8000_001F_EAX] =3D cpuid_eax(0x8000001f); - - if (c->extended_cpuid_level >=3D 0x80000021) - c->x86_capability[CPUID_8000_0021_EAX] =3D cpuid_eax(0x80000021); - init_scattered_cpuid_features(c); init_speculation_control(c); =20 --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFDF439281D for ; Fri, 27 Mar 2026 02:22:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578154; cv=none; b=Hr14q7pUB2VMBel7RYm501gWaOplnP1qJH4reVNaY+oZ6WO0Dwi0vulb08okHrVIxMC7R3u8PfPSP2lf5V1njAPhJRAvNKXcLf1hE2k3lGUqJqvi7WOvzVgwKRU1prORwnQgJf/MBGlGBFRFFF2lDSzPPaenPYXvy1xgpNtjq3w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578154; c=relaxed/simple; bh=ynA/HPkCCdgnDJSl9aU9Tk56ktM4xINS/RyRhV4OtQk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i8TIQN7wkT7ajMQP6cJIhjnaPTdfZXKHZwnZav2lyaZVXET9ADry3fSh1UAWFbN1OL1tBib7c2N5+TcgMPcS6SDhkRYhWwhY+bTgps4w0h2l51yytaxm/0nniBLa6pCoBGhVaBKcxOW666kqHT1drNVCgIR4fqId8W3iHMREWPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=iYygi1+7; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=2JlxhDWd; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="iYygi1+7"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="2JlxhDWd" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578150; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lRnJLFYUKewqy8Wxd9RkA3zX/wU9Hzrsxeiv+vKeuvU=; b=iYygi1+76Cl9CpPn86hvIeJP8jGkwCXeRia25T70nCH+ynQ/dJOK2zXVNsURqOFfHpnLsk gqJyQr6HP9WC3nFMSqfQ2g6AkRAi6GkO6TZgjALn401hp5VPcuf75uLI5OignF76bfyDa+ V/RmMVheks9iUSVEa/betp3klbAE3TBsjIdi0QIOgz8TyplkZd/ZxnlGFWS5MdifCIQ6pE HpHHHEthAqDYdaVn+7Xz7fB4VlL414lh/NHGTjCD/ETms0kyYRpGlb9Um2ykQTYXQGltBP gT/G38zDpTmAwPU+LblkF3KZVUl8RiG2yf9qf+o0XV+z5guWueJEjm2xkcLVbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578150; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lRnJLFYUKewqy8Wxd9RkA3zX/wU9Hzrsxeiv+vKeuvU=; b=2JlxhDWdaQkuYmUl044xveuHVTGHUAAroptKjfgiCGT25jEalH9MUxnLt6BevxZaiRSmIp uD6bM7gVqCmmcQBQ== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 86/90] x86/cpu/transmeta: Remove x86_capability[] CPUID initialization Date: Fri, 27 Mar 2026 03:16:40 +0100 Message-ID: <20260327021645.555257-87-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X86_FEATURE queries are now routed to the CPUID tables instead of to x86_capability[]. Remove all direct CPUID queries which populate x86_capability[]. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/transmeta.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/x86/kernel/cpu/transmeta.c b/arch/x86/kernel/cpu/transmet= a.c index 991e11d5c28a..47964f43a740 100644 --- a/arch/x86/kernel/cpu/transmeta.c +++ b/arch/x86/kernel/cpu/transmeta.c @@ -10,14 +10,6 @@ =20 #include "cpu.h" =20 -static void early_init_transmeta(struct cpuinfo_x86 *c) -{ - const struct leaf_0x80860000_0 *l =3D cpuid_leaf(c, 0x80860000); - - if (l && l->max_tra_leaf >=3D 0x80860001) - c->x86_capability[CPUID_8086_0001_EDX] =3D cpuid_edx(0x80860001); -} - /* * If CPU revision is 0x02000000, then CPUID(0x80860002) should be used in= stead. */ @@ -85,7 +77,6 @@ static void init_transmeta(struct cpuinfo_x86 *c) rdmsr(0x80860004, cap_mask, uk); wrmsr(0x80860004, ~0, uk); cpuid_refresh_leaf(c, 0x1); - c->x86_capability[CPUID_1_EDX] =3D cpuid_edx(0x00000001); wrmsr(0x80860004, cap_mask, uk); =20 /* All Transmeta CPUs have a constant TSC */ @@ -103,7 +94,6 @@ static void init_transmeta(struct cpuinfo_x86 *c) static const struct cpu_dev transmeta_cpu_dev =3D { .c_vendor =3D "Transmeta", .c_ident =3D { "GenuineTMx86", "TransmetaCPU" }, - .c_early_init =3D early_init_transmeta, .c_init =3D init_transmeta, .c_x86_vendor =3D X86_VENDOR_TRANSMETA, }; --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2578392820 for ; Fri, 27 Mar 2026 02:22:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578156; cv=none; b=RWybICuoJ3UPYrUBjGuvzS9Wff3OC6brL90mGM7o5aNy5neAblSyRhZnwBucDNNDqaW2EX8vYQb5OixZk6Dq70LJ/oYAIYICCvkyLN9QjS/DjIfG7BlfcPKbcYSpQuELYnPGwT7q+I88ZcpfhtJ0tzQXFpE10VJb95m375F7ifw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578156; c=relaxed/simple; bh=O1DUzfl/y2F/gnNIzuI8mbSsD1Ph8MwszabFmfGynUU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OOiQ4ynC3vTLQRpGQ+Cpr4T4UhY+vupOW7ArYY0lxLP1oj3j97AoWibasdEeGRKKyO6mrIxEUuy5eD0bdE5twYVoZ8UB/8yhjvLk107EvoKQarzDD47fCYpkeEUkOQ2sHk6wqcTxoF11GnaOxNmcimdG3Q2pZpmeYpWjUewcV38= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=m5A1Kb2X; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MePTuquC; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="m5A1Kb2X"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MePTuquC" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OAqQxD4w7NdN72ZHq9rATOZSGwIFSb4iHHdAnOHx8ho=; b=m5A1Kb2XVdmwknze8+2os1nMctvpR555izg7F+nZzLWpaLpZ8sU7rL/ByKKisG2+UEinKs zYLLdh20q+taFQNF/QO5CS7JkYtBzBK2hl0kgkVZ2GmpVCnF/wo5rD0j2O0nbMdvXJ+1NN 94IJubFX2O7B5TVXKZ5NZafKxGvgxEkIfk/N4CG6LsfMFQg/HUwcMZQc50iYpbNbbLrlOD Xuo5ShDMuH+ZBRhYlA3soqQ4mcL2G13pPUmcExtgzj0OcxtQokmaVkdN/eEnyMfi4tpCW2 NorFuFHEloyYT6lMHMOfGA9+g0VtXaqfKeB9UXIQBpZ71cQfhalgmS36QCPV4g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OAqQxD4w7NdN72ZHq9rATOZSGwIFSb4iHHdAnOHx8ho=; b=MePTuquCidQxnMp2f64seZvlxcVGBdcCnpu4qluUSnSZgIXa/UUHf6yV1n2Aggu3LM8WJ3 rdagW16/oONAAEBw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 87/90] x86/cpu: centaur/zhaoxin: Remove x86_capability[] initialization Date: Fri, 27 Mar 2026 03:16:41 +0100 Message-ID: <20260327021645.555257-88-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X86_FEATURE queries are now routed to the CPUID tables instead of to x86_capability[]. Remove all direct CPUID queries which populate x86_capability[]. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/centaur.c | 1 - arch/x86/kernel/cpu/zhaoxin.c | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c index 29688aec2231..8f614003d82c 100644 --- a/arch/x86/kernel/cpu/centaur.c +++ b/arch/x86/kernel/cpu/centaur.c @@ -42,7 +42,6 @@ static void init_c3(struct cpuinfo_x86 *c) * EDX feature bits. Refresh the leaf. */ cpuid_refresh_leaf(c, 0xc0000001); - c->x86_capability[CPUID_C000_0001_EDX] =3D cpuid_edx(0xC0000001); } #ifdef CONFIG_X86_32 /* Cyrix III family needs CX8 & PGE explicitly enabled. */ diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c index 5918f9387c87..7f576f0296b7 100644 --- a/arch/x86/kernel/cpu/zhaoxin.c +++ b/arch/x86/kernel/cpu/zhaoxin.c @@ -41,7 +41,6 @@ static void init_zhaoxin_cap(struct cpuinfo_x86 *c) * EDX feature bits. Refresh the leaf. */ cpuid_refresh_leaf(c, 0xc0000001); - c->x86_capability[CPUID_C000_0001_EDX] =3D cpuid_edx(0xC0000001); } =20 if (c->x86 >=3D 0x6) --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D209C3939C8 for ; Fri, 27 Mar 2026 02:22:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578160; cv=none; b=RsHjJPhAzux99IRksRL+zOgfxobVQi1ABfhqB9NEZo0MiMYX+zVx5qpXFpB00jp6Y7J1DjSTh+1Hvtq0EmL7NhFOWWInoj9NWAcLCZw/bmWYpkqqvD0ROW+SXottVeN1NAKJGFtVCRk0AXAeRrjtNpl0H3MxbAMZogR4zvnGHGE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578160; c=relaxed/simple; bh=oLu12pslI3diZk7qLpjI51uc3xRnsaHx0471coV8pQk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AEe9n/QsGaW/5rYFvFLo51WBRB/kxVIG9rjQa0cbxhYowmtqaxPhXVs7tRx1LgqnxoCnL0FMyfBuQ219emz9PBIzesp27Ad9yPQPwaZNqHb4H8aFJOHq3kNjJHE/YW/zrTeWyQoFzM8e0Sn+hkvEL7TqN29REGGv81IpVCSgFu4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TSUyG/Uo; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=lQoBK2Do; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TSUyG/Uo"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="lQoBK2Do" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578157; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LftgPTXKl4qmU4BeuavS76vMB5Umy9LKzMATlo8gpA4=; b=TSUyG/UozkOWk9nKMhDDKV97O+qgoke9Ba4SisWmpiFngW9RQ3XB7eUWr1l3BxF1Sk+KV5 8vuE9iHgybKwfG0Dhct7dpuVxmQt/tIK2hoH6jQtFpcXyS42gz0EGPIVqqi0OfjKt4YbVY i933KNYGCy1oMT9hrmFb/8WGt2AFvLF7T6rNR23Ebstc+/6lLevSNjU8/OQV1LjtLm7j+P HGIFqOjfbGX8A+sKfZhSjhAS9UehHfNEt9wVm3FbN+GmDc/sZ71ysrEz43TEP6eP11+OMx MxvpNnrJg8Rhbsw6puQCMYLN2P/P62Kn8VEL+dmCobjQP7WEW5TPvAakFxbeDQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578157; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LftgPTXKl4qmU4BeuavS76vMB5Umy9LKzMATlo8gpA4=; b=lQoBK2DoAkFz5vp9jKrFZpE1XjShTv/dqvw4fUcIkjmFsl3uvJDdr35o0EC8av33z2JwZI I/ZReWD6MoVTN5Cg== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 88/90] KVM: x86: Remove BUILD_BUG_ON() x86_capability[] check Date: Fri, 27 Mar 2026 03:16:42 +0100 Message-ID: <20260327021645.555257-89-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM's direct access to cpuinfo_x86::x86_capability[] has been replaced with the cpuid_word_*() APIs. The former is getting removed from the kernel. Adjust the kvm_cpu_caps[] alignment comment accordingly. Remove BUILD_BUG_ON() related to x86_capability[] as it does not matte anymore. Signed-off-by: Ahmed S. Darwish --- arch/x86/kvm/cpuid.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 161fa2b23bdb..dac12dfdf47a 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -30,8 +30,8 @@ #include "xen.h" =20 /* - * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need t= o be - * aligned to sizeof(unsigned long) because it's not accessed via bitops. + * No unsigned long alignment is needed. The CPUID tables X86_FEATURE + * words are accessed by bitops, but this table is not. */ u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_cpu_caps); @@ -838,9 +838,6 @@ void kvm_initialize_cpu_caps(void) WARN_ON_ONCE(kvm_is_configuring_cpu_caps); kvm_is_configuring_cpu_caps =3D true; =20 - BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))= > - sizeof(boot_cpu_data.x86_capability)); - kvm_cpu_cap_init(CPUID_1_ECX, F(XMM3), F(PCLMULQDQ), --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCEDF393DE2 for ; Fri, 27 Mar 2026 02:22:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578163; cv=none; b=fcXVUFmjOtRMiEtzubyhTvkptvpx0+yVgJdj7zo5DEt2TqxHQ25c5rI0iHVDzxbaCNUIuIvHcwVE7BZlbC/BbyTOH+anDUgfCzxAgzi0UeXmQukka/YqjxwqEzoAhi7B/pNGMkxkgjxJWCok8lJRA7D3riqMAe6IwKQ861cUe5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578163; c=relaxed/simple; bh=848d03O4fqGkPw8RNKK0B5rZdud1fHSIT/vsGY/eySI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VQVYXBemeLhVf+sUt+eLH+XSzHJC2wVaYkrM8vGu5aF4rOIwP0nhyHoK8o29wpCu75IlFXsHn2VRxaWzWqiOQxOIgiTjEzOx899bXJ+Z6C5CuUIa8cXIfsGJ4lYwtnzw6sfU6M9LjN29NraHRGVWT1jYM/ckljjMx0xZngMqFgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BvVVceFI; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wWkdcO7m; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BvVVceFI"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wWkdcO7m" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1774578160; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9dkS9uSyMgO/9YEi0dhzEZ5jY0wmaplyfiAhz43RAAc=; b=BvVVceFIHrrWxPJdOMHKyP/QHZMumb88Z+VKLl3Ezi/bFVosUoMfJNF7dj8KE/YUCVQjmb gSJ1EwEWCg8JodibVaoL5cx09F/0YvbWVxqQa8sdBFIOqMy2MJx456/q4rV4Pai+hBn8xq NxYNDxX+VSzCDlTcgr43JXsw6XMk61N8iCI3TtDQZr/b7ICZnTXDV8H1T+MAP4Oj2w/tUH HZ+/NAvsNN6dVi4bevuiyW2u82YTiJYhmcwGeHO2t3kT9kn8MtRxrloDU4RjKa8BUe5CxY A+36oK+UvyvO/HaJaCBs9JydKQSZISkvNByimiGCfVOQXJ537chXS6yXB/Nwgw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1774578160; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9dkS9uSyMgO/9YEi0dhzEZ5jY0wmaplyfiAhz43RAAc=; b=wWkdcO7mq9fVkmHoddPvSTdYUmvF06KEJfYZx51R1Gummkuoj2SO1TMmCo9PyByiimBnjn fviPeA+smZaLVKCw== To: Borislav Petkov , Dave Hansen , Ingo Molnar Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 89/90] x86/cpu: Remove x86_capability[] and x86_power Date: Fri, 27 Mar 2026 03:16:43 +0100 Message-ID: <20260327021645.555257-90-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X86_FEATURE queries are now routed to the CPUID tables instead of to x86_capability[]. x86_power call sites have all been converted to parsed CPUID(0x80000007) access. Remove x86_capability[] and x86_power from struct cpuinfo_x86. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/processor.h | 10 ---------- arch/x86/kernel/asm-offsets.c | 1 - arch/x86/kernel/cpu/common.c | 5 ----- arch/x86/kernel/head_32.S | 2 -- 4 files changed, 18 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index 5ee0dcbd548c..b5c89229d9a2 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -153,15 +153,6 @@ struct cpuinfo_x86 { __u32 extended_cpuid_level; /* Maximum supported CPUID level, -1=3Dno CPUID: */ int cpuid_level; - /* - * Align to size of unsigned long because the x86_capability array - * is passed to bitops which require the alignment. Use unnamed - * union to enforce the array is aligned to size of unsigned long. - */ - union { - __u32 x86_capability[NCAPINTS + NBUGINTS]; - unsigned long x86_capability_alignment; - }; char x86_vendor_id[16]; char x86_model_id[64]; struct cpuinfo_topology topo; @@ -173,7 +164,6 @@ struct cpuinfo_x86 { int x86_cache_max_rmid; /* max index */ int x86_cache_occ_scale; /* scale to bytes */ int x86_cache_mbm_width_offset; - int x86_power; unsigned long loops_per_jiffy; /* protected processor identification number */ u64 ppin; diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c index 0bc36d617801..98d2cd03d0af 100644 --- a/arch/x86/kernel/asm-offsets.c +++ b/arch/x86/kernel/asm-offsets.c @@ -38,7 +38,6 @@ static void __used common(void) OFFSET(CPUINFO_x86_model, cpuinfo_x86, x86_model); OFFSET(CPUINFO_x86_stepping, cpuinfo_x86, x86_stepping); OFFSET(CPUINFO_cpuid_level, cpuinfo_x86, cpuid_level); - OFFSET(CPUINFO_x86_capability, cpuinfo_x86, x86_capability); OFFSET(CPUINFO_x86_vendor_id, cpuinfo_x86, x86_vendor_id); DEFINE(CPUINFO_CPUID_0x1_EDX, offsetof(struct cpuinfo_x86, cpuid) + diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 4c2739f31e3d..a5e94f09c5dd 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1727,7 +1727,6 @@ static void __init cpu_parse_early_param(void) */ static void __init early_identify_cpu(struct cpuinfo_x86 *c) { - memset(&c->x86_capability, 0, sizeof(c->x86_capability)); memset(&c->cpuid, 0, sizeof(c->cpuid)); c->extended_cpuid_level =3D 0; =20 @@ -1959,7 +1958,6 @@ static void identify_cpu(struct cpuinfo_x86 *c) c->x86_virt_bits =3D 32; #endif c->x86_cache_alignment =3D c->x86_clflush_size; - memset(&c->x86_capability, 0, sizeof(c->x86_capability)); memset(&c->cpuid, 0, sizeof(c->cpuid)); #ifdef CONFIG_X86_VMX_FEATURE_NAMES memset(&c->vmx_capability, 0, sizeof(c->vmx_capability)); @@ -1987,9 +1985,6 @@ static void identify_cpu(struct cpuinfo_x86 *c) * features a certain CPU supports which CPUID doesn't * tell us, CPUID claiming incorrect flags, or other bugs, * we handle them here. - * - * At the end of this section, c->x86_capability better - * indicate the features this CPU genuinely supports! */ if (this_cpu->c_init) this_cpu->c_init(c); diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S index 6dcc27014641..7f38331ee083 100644 --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -41,7 +41,6 @@ #define X86_STEPPING new_cpu_data+CPUINFO_x86_stepping #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level -#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id #define X86_FEATUREFLAG new_cpu_data+CPUINFO_CPUID_0x1_EDX =20 @@ -263,7 +262,6 @@ SYM_FUNC_START(startup_32_smp) movb %al,X86_MODEL andb $0x0f,%cl # mask mask revision movb %cl,X86_STEPPING - movl %edx,X86_CAPABILITY movl %edx,X86_FEATUREFLAG =20 .Lis486: --=20 2.53.0 From nobody Thu Apr 2 18:53:50 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06039349B02 for ; Fri, 27 Mar 2026 02:22:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578166; cv=none; b=kTwJEjdIA9wHsaTPQk1/OtVqMS5MnL5+lY+3MZfW6dYltfNScfUYzpejBqnl9Y47Z6ZEdHYPWvG3pCLHI21EkC6+LKN935HbWYXD2BmfYqLuyhzbm6T2OGqUObjjmEg61SKVQHhhzAbgI7gRjJy6qt5uYWL+KBTSObOn8d4w8gg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774578166; c=relaxed/simple; bh=V37j0rs4TGKyYARlAleKL5dHag3KfmGVe/rCYIBvz2U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y3XlWvFCQTMUnwCC3l7vUOmkfcF3jtKrGpySuDwbArn5MVBeQ0i9/6PEQCfHI7+JPonxnD5661rm95a8jxGo2usoBQv/iVhfrG+3wUapC0WnUP0IHsp1AG9o3R9Fp9eZ5cjyS6XZz7G8EFVd1EaBsFmD7ECu2s1ZXP+pf7hoCHo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fslI8Zh+; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/AWgwIc7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fslI8Zh+"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/AWgwIc7" From: "Ahmed S. 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Peter Anvin" , Sean Christopherson , David Woodhouse , Peter Zijlstra , Christian Ludloff , Sohil Mehta , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v6 90/90] MAINTAINERS: Extend x86 CPUID DATABASE file coverage Date: Fri, 27 Mar 2026 03:16:44 +0100 Message-ID: <20260327021645.555257-91-darwi@linutronix.de> In-Reply-To: <20260327021645.555257-1-darwi@linutronix.de> References: <20260327021645.555257-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add arch/x86/include/asm/cpuid/ to the x86 CPUID DATABASE entry since the newly-added CPUID APIs are now at and . The auto generated x86-cpuid-db CPUID C99 bitfields header is also under that added folder. Add arch/x86/include/asm/cpufeature.h since it has the X86_FEATURE word names listing, along with the X86_FEATURE APIs, which are now both routed to the CPUID tables. Add arch/x86/include/asm/cpufeatures.h since it has the X86_FEATURE bit listings, where by now new feature bits should only be appended to; never modified in-place. Adding these files ensures that myself and the x86-cpuid mailing list are CCed on related patches. Signed-off-by: Ahmed S. Darwish --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8cb3b9fcface..6cd8d0e4fb99 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -28564,7 +28564,8 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org -F: arch/x86/include/asm/cpuid/leaf_types.h +F: arch/x86/include/asm/cpufeature*.h +F: arch/x86/include/asm/cpuid/ F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE --=20 2.53.0