From nobody Thu Apr 2 18:47:46 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C3753BED6E for ; Fri, 27 Mar 2026 10:22:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774606956; cv=none; b=f0A/skxqbhMc+NXV184j5LVCj8zXk4HBL/1Gw3C1GtY3HIdDTk3XXLNLMy3v41pewA+g9cEPsgyCRyhq/5U5SuGXp8p3oa4osdxkW+OLn0lf+qA7vpvsIDKYabRwWxFKcBU2YufA4igrMTjo6btDPmV7ZSY/5jpiCimoPcU3ako= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774606956; c=relaxed/simple; bh=eaeDuhTwVtvOUYbWOU6Pi8XJP6K+PPcBl3PTwjkGBnM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UJr4/8FRGH1y6cb3FxOX1/wvliOrXzmnje+PI3exmfmPVJsudT8WDioNekIvBuOTAdl2+iOonxZtNByBssQBC8n0vUyGwJ/8SD0+gXfNGGMjIWz+m9DJbbGjTGQ0FvKcNy+PMDab3yoo8kiNv9JoY6wwIqODkPBrMZZaXJM5a3A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=G/hbaY5V; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="G/hbaY5V" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 349B71E31; Fri, 27 Mar 2026 11:21:10 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1774606871; bh=eaeDuhTwVtvOUYbWOU6Pi8XJP6K+PPcBl3PTwjkGBnM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=G/hbaY5VUiOWhtpB0qCz0Kwh7M3oL3se9SeJ0fh+/cSAgl6FzQY5T3BeMua54Gyl1 2yx0sPZRY/dJ6ehXLl/9D833jiXOesH0rMngTmhcGFowFvomRsU9UaR2CjGFpsmaXx w4wbM6rBjpRRE4eFdAUgX0pD2rdA6HSaBwgDt330= From: Tomi Valkeinen Date: Fri, 27 Mar 2026 12:21:55 +0200 Subject: [PATCH v2 07/12] drm/bridge: tc358762: Update comment about the number of lanes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-tc358762-fixes-v2-7-3589d3c45f4a@ideasonboard.com> References: <20260327-tc358762-fixes-v2-0-3589d3c45f4a@ideasonboard.com> In-Reply-To: <20260327-tc358762-fixes-v2-0-3589d3c45f4a@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1121; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=eaeDuhTwVtvOUYbWOU6Pi8XJP6K+PPcBl3PTwjkGBnM=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBpxlpc06X2gdz9/il55MrCCRPBxBbZ+p9fQSZqP 5RqZ3j4CuWJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCacZaXAAKCRD6PaqMvJYe 9b7iEACbL2OHaGmQIj/peIL2x07AktnKO8Obzf7Q4y/F1ds3ofrzreYbaSBSrOFHl7TYik2/WDS 1GRLfKsckKrKOs1fhDgNPkP84/4x5FbMqPOrsMZz9SyQK4+Ac3HobldG5ctOld/AfJoLbY1CREA o/r94jYP5n+NhnjeOm0qbJa4PJnvwH208kEwfHR0oLYTS31niYFC492g256gAX8QGmMyg1cb7bF PaW/XXdPuBTcssVHirP8MSD/7uSehCI8zBUoUq84gqGOg+XrExjlah8aX0fhMLDNLoeW0jhAPf2 75JBBaoa6zHKQR8daQWOV7kXgdXZ2Wzbrsv2CO/ipnFJ2BeYZNvUT6YbP0JuJOjUAcvLajQ9k3r KLJpuF+poIbL+jF1EvspN0Zu56XFHQpqYH3wF7H5gT/8VJOfMEOsrnaD9L09MPCj5e4/RtXbfKH XfCPjzYE2IOuGozDPAS9aBOssmrh4qgY/yr51Y8ceVQBGgIDkHSF7Pzv2uGLczeUdo2A7V3gSof BrruEE6nhY3Ypw9LrxbVn6t79QsbPqrJpu5GVfOCE6TBIGwdRd7bqdBgXyjKUSfrc8ARJ25zDov pCumLfE2StVwuEh+kR9pQjoq+VXOYeyj2GyqizDmESZ3gM+iowRnI4Fo0Jq8AtMf5K2HF/tQrwR lQUMam5cfliL5Yw== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 Update comment about the number of lanes. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index cc1c5ff42cbd..9fb921b3fa0d 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -305,7 +305,14 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) ctx->dev =3D dev; ctx->pre_enabled =3D false; =20 - /* TODO: Find out how to get dual-lane mode working */ + /* + * When using DSI clk for pixel clock (only mode supported in the driver), + * the pclk is derived directly from the DSI byteclk via simple divider, + * which is either 2 or 3. + * The required divider can be calculated with bitspp / 8 / nlanes. Thus, + * for RGB888, only nlanes =3D 1 works as nlanes =3D 2 would require divi= der + * of 1.5. + */ dsi->lanes =3D 1; dsi->format =3D MIPI_DSI_FMT_RGB888; dsi->mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | --=20 2.43.0