From nobody Thu Apr 2 18:47:46 2026 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 833AA3B3BEC for ; Fri, 27 Mar 2026 10:22:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774606951; cv=none; b=CEEYiFlUoYva9ozzPFfRBgkHwMemkWO4JKMnYTeO1na/qJKPyazvNWDuLG843edv18lKsCsoh2BlR2BNeq91pXwrymo+R2Lqc2s+b/jk0kAIqPad516oxiJFrfFEyZ2AnqvgySjt8+G4bVYRqUnJmSQMv/92rn1S3ss7y8Ad9pM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774606951; c=relaxed/simple; bh=NuaGyo7S8VZSSZ/guEUo9cbKkXUB0xNZ7DHe3gckBAc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZTB3rwD5dxxtOIPDIQqESSB6fkQP2knD/dWb8TZOdC48vXmeMINdjnGFDdirVnibrJAoCYPSi0/6dtxMJlXA1xlrTRm5/FG9RAIAIoZX4EOhzI3SATzJ3zm2KNG9VYUym6MtZGs0QQNkoLwV7fRbzJn/dLy2z84gjnp5zcY0W3Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=Qh5RP1NG; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="Qh5RP1NG" Received: from [127.0.1.1] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 50A3A201C; Fri, 27 Mar 2026 11:21:06 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1774606867; bh=NuaGyo7S8VZSSZ/guEUo9cbKkXUB0xNZ7DHe3gckBAc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Qh5RP1NGPt9/hPI+Q1Sb9OZPS921Nw9rh/4ybE4Y+SB1795fCZuGyGzzBn8Pc9xUu pH1SYQh4UX62hl5uTCFhPeWweii4+l5Oqq3lq3FjJRf9+w2gG4NKQfy0Vbv+H/tuDv Xx+zI2QZhj9II8ieljGvEYCI1/uLW8oMHVWItTrc= From: Tomi Valkeinen Date: Fri, 27 Mar 2026 12:21:51 +0200 Subject: [PATCH v2 03/12] drm/bridge: tc358762: Improve LCDCTRL defines Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-tc358762-fixes-v2-3-3589d3c45f4a@ideasonboard.com> References: <20260327-tc358762-fixes-v2-0-3589d3c45f4a@ideasonboard.com> In-Reply-To: <20260327-tc358762-fixes-v2-0-3589d3c45f4a@ideasonboard.com> To: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson , Tomi Valkeinen X-Mailer: b4 0.15-dev-c25d1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3005; i=tomi.valkeinen@ideasonboard.com; h=from:subject:message-id; bh=NuaGyo7S8VZSSZ/guEUo9cbKkXUB0xNZ7DHe3gckBAc=; b=owEBbQKS/ZANAwAIAfo9qoy8lh71AcsmYgBpxlpaqEG2AEDHQCs6ZzihIgLoWocExJ+ySZsqY LtNRI+7y3uJAjMEAAEIAB0WIQTEOAw+ll79gQef86f6PaqMvJYe9QUCacZaWgAKCRD6PaqMvJYe 9S7iD/9duMg80Wt5V3hKIigUEmAxAOiZ1mQhlUQW9gpaB7Mx4ad/Q77z/rOcz7PVebgct43Lutz DWILjV7IxfNQq8WdZHaAn15JRjnRV2iViwqjjPlv8HKOB7qbhBi8lBOhkq+aysRgagcQRja4iVE mQ4cExx5ZR5drtKuHXH2TLZum2U+yNyzGP9zXDACMFAbATFI+Mx4GXFcmO6qRCniDV1pCsn+ZNy K9mpaxbmJV29nxgr5F8ydP97cS3kX0zKIEDbIv0hjV62jM3Z6KxIPIYhJVR7Ry3jzvBYyHK45MW I5KA5wbynCzrsbg1qk3yAYXmkNddlMqurByYvKIv/gK9faFeMLjbwfxRp8zPAyMq6MAChOw5ul8 GkVPuMyHeWIQ0dgcDCKSNR4XEZIMRNU5Y6DdxnZhjnL9TyXnM8jjW1OrV+SfwWiHax56HPYPyN2 yzw+XstOdldz+WzU1J6CZ7z77RF9k46H/DydLm5PbOuUwEpdAXNJv7hbtLJYLK2Cfbr4Giq1Ddv eq0bPSb4Zh4TIcuUFDqGD/tRnInDnNCdH1V91HN3oDT/P//e7ECOLDws63Fhs5tuK3ZmqQWhKSz gcxmxLhEXYnqwxMuLVz6fQyTjybq9y3rb1YGUl6U5K3cUfTIEmafA7gmGUTaEOZx/GSre5OFr+W y9ZPz3eMmpkxOrA== X-Developer-Key: i=tomi.valkeinen@ideasonboard.com; a=openpgp; fpr=C4380C3E965EFD81079FF3A7FA3DAA8CBC961EF5 LCDCTRL fields are quite wrong in the driver. Fix the field defines. A few notes about the wrong fields: LCDCTRL_VSDELAY(1) actually sets LCDCTRL_DCLK_POL LCDCTRL_UNK6 | LCDCTRL_VTGEN actually set LCDCTRL_PXLFORM_RGB888 LCDCTRL_RGB888 actually sets LCDCTRL_DPI_EN The total still resulted in a working display even if the defines were quite wrong. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/bridge/tc358762.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc3= 58762.c index 9a0b1f0c18f0..cbedffb7a705 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c @@ -46,17 +46,22 @@ #define DSI_LANEENABLE_L0EN BIT(1) #define DSI_LANEENABLE_L1EN BIT(2) =20 -/* LCDC/DPI Host Registers, based on guesswork that this matches TC358764 = */ +/* LCDC/DPI Registers */ #define LCDCTRL 0x0420 /* Video Path Control */ #define LCDCTRL_MSF BIT(0) /* Magic square in RGB666 */ -#define LCDCTRL_VTGEN BIT(4)/* Use chip clock for timing */ -#define LCDCTRL_UNK6 BIT(6) /* Unknown */ -#define LCDCTRL_EVTMODE BIT(5) /* Event mode */ -#define LCDCTRL_RGB888 BIT(8) /* RGB888 mode */ -#define LCDCTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ -#define LCDCTRL_DEPOL BIT(18) /* Polarity of DE signal */ -#define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ -#define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */ +#define LCDCTRL_VTGEN BIT(1) /* Use chip clock for timing */ +#define LCDCTRL_PXLFORM GENMASK_U32(6, 4) +#define LCDCTRL_PXLFORM_RGB666 0 /* x:R:G:B 6:8:8:8 */ +#define LCDCTRL_PXLFORM_RGB666_24 1 /* x:R:x:G:x:B 2:6:2:6:2:6 */ +#define LCDCTRL_PXLFORM_RGB565 2 /* x:R:G:B 8:5:6:5 */ +#define LCDCTRL_PXLFORM_RGB565_1 3 /* x:R:x:G:x:B 3:5:2:6:3:5 */ +#define LCDCTRL_PXLFORM_RGB565_2 4 /* x:R:x:G:x:B:x 2:5:3:6:2:5:1 */ +#define LCDCTRL_PXLFORM_RGB888 5 /* R:G:B 8:8:8 */ +#define LCDCTRL_DPI_EN BIT(8) +#define LCDCTRL_HSYNC_POL BIT(17) /* Polarity of HSYNC signal */ +#define LCDCTRL_DE_POL BIT(18) /* Polarity of DE signal */ +#define LCDCTRL_VSYNC_POL BIT(19) /* Polarity of VSYNC signal */ +#define LCDCTRL_DCLK_POL BIT(20) /* Polarity of pixel clock */ =20 /* SPI Master Registers */ #define SPICMR 0x0450 @@ -139,14 +144,16 @@ static int tc358762_init(struct tc358762 *ctx) =20 tc358762_write(ctx, SPICMR, 0x00); =20 - lcdctrl =3D LCDCTRL_VSDELAY(1) | LCDCTRL_RGB888 | - LCDCTRL_UNK6 | LCDCTRL_VTGEN; + lcdctrl =3D FIELD_PREP(LCDCTRL_PXLFORM, LCDCTRL_PXLFORM_RGB888) | + LCDCTRL_DPI_EN; + + lcdctrl |=3D LCDCTRL_DCLK_POL; =20 if (ctx->mode.flags & DRM_MODE_FLAG_NHSYNC) - lcdctrl |=3D LCDCTRL_HSPOL; + lcdctrl |=3D LCDCTRL_HSYNC_POL; =20 if (ctx->mode.flags & DRM_MODE_FLAG_NVSYNC) - lcdctrl |=3D LCDCTRL_VSPOL; + lcdctrl |=3D LCDCTRL_VSYNC_POL; =20 tc358762_write(ctx, LCDCTRL, lcdctrl); =20 --=20 2.43.0