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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:31 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:20 +0100 Subject: [PATCH v2 1/9] dt-bindings: display: msm-dsi-phy-7nm: document the Milos DSI PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-1-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=871; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=EVldcqfPHPh1FF7QDMATcvXChGeMKnSCWknhWuq45Jg=; b=7Xs0w2eewxL5CZRI6DTsd3patfJnGDWajpneO0Gb7M04cO2ebwe9xVRUTwB/8n4ryA6yQf4XM Wst+Ph1T2SSBnUcinUWrXd3lqAzF+0vVz4Pe5oq0O1dNKX+diUB1slP X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the DSI PHY on the Milos Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index b5a0c1461250..4bdec236734c 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -20,6 +20,7 @@ properties: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,kaanapali-dsi-phy-3nm + - qcom,milos-dsi-phy-4nm - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm --=20 2.53.0 From nobody Thu Apr 2 15:37:59 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABE35345CD8 for ; Fri, 27 Mar 2026 16:12:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774627956; cv=none; b=r1T1eQFyrOZ/TFSH7ZnhrTaPN83yrFGm41LZTo4OkSeMg7UhpqTinhoAnVmONrg9VxwHeOMnrsiSGT+rbtO7YTJs4rQTyq9ZoR4uloTiDcLqQ4OBsV5Em7KZP9YIQpmAJ4His30Ca+AdkQaUkEXiBQ+PEn+gCpjRhJ+f4QXHK+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774627956; c=relaxed/simple; bh=/iuE8Of7PxtUN21ThxuyRVaZpwkJ5NvVO+YKGCgqQ64=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ikEEyZSzqygr03rj094641Ifsv1AhSCClIn5eCqT9HBxKyzPMAV9mTv3iEEn3X3s6rokSWPa5f35OKvEf9etE5bZZl8GaJfliwEs24la1kZsaD6GgkjSA8w+7YJwZvERTJfTwkq5ZqgWaAFYMeard0Dz+gE0ulQk5YPmX0j9acM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=I0olmsWo; arc=none smtp.client-ip=209.85.218.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="I0olmsWo" Received: by mail-ej1-f54.google.com with SMTP id a640c23a62f3a-b93698bb57aso425033566b.0 for ; Fri, 27 Mar 2026 09:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1774627953; x=1775232753; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nMi8pPc1nu1OwZY0Xf/EDRaYl50oxCMJcLrOAypEPLo=; b=I0olmsWoxpRstCu65hD6A96pnIQoLAgUICUYl8cPWFFInW84P1BbJvpl1MPxPnt7+u BexgOiQ36XOJaG7smjtrD6hJeMs1sb5NhOBukp0eAld1Kjq3upW7kc66eSKzvulg3wRk tgcXvCsb0PPuPntDyzPazArt68HGJuMG/jrC2KBVj2R4y5EhdZLB6pt+eW5NniEMCCQt 4a5fCjVF9iCAR/MSCS9RGjO4vV49iJVPrULDuXrHl3bGb3lUaFB5w5nZxVLGGrVH7LlP qatvBxzPb3LF6R/td1zw3/hJ9Uacu7ISidcxi/3jQjBt+kizPQxFefjb7V6jGrjDeMsC kfXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774627953; x=1775232753; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=nMi8pPc1nu1OwZY0Xf/EDRaYl50oxCMJcLrOAypEPLo=; b=S/R5bzom8j46WQhABM6szt+XbyUvb4tmbq4826WtEuS8S99+1zU+N/ZdHCsiOZC9gV aW6G5VKXgQi8CA0Sp4XJ1mni6cyQJ5bipSXRvXrJpoDLeYb2ui4XuNicPbPq4NaHU9PO 7AFnGYc3zOreyw6Iqts/Xq3JnGjLlcIBmXDuMeNZBo2xtitftE86j4psI610di6LZHdV 19tBNl58YoICBYSdTt5WtqlojJtgFcwljCrTi9gC9IePvD9lcIWoIucf8vXy21AotLhZ +L3ZWf2bpmztZixTsOy4ZhF6QBe5MPgH36BeQmIzgVEvaynsEFScc+bD1rE7fvmiaRIb oAyQ== X-Forwarded-Encrypted: i=1; AJvYcCXjjI3EOUhkKoHqVXKyKG5yMazTYhl6/mWW127K3BKXIhwbT7kZzbSF7jhgai343lPYbhTy8XQdOd1XAo4=@vger.kernel.org X-Gm-Message-State: AOJu0YxJ2n1ULfCI7SSnKo++ZhhhZCLs/6s7bGk7fc+VCXMD7TxjHngq OI8Hqi92bOfm3qyKzWNstIvzGL02020tsCMNvFRnC5FKH+/NuYwi9TFvGgooujOrmwE= X-Gm-Gg: ATEYQzyV54RGVuLTDX8WloOA0M0kzsSCgwJ26YWeshO4I4ELGNjhsikACsU50P9EyIY J0JXjAbAkpJ7vNyUaMAXSmKUmaDNvE+e84XVZIIs38lxGWY+q2+qKHMLlhLKF6XbAGVtdVx8kgM L3T7jQiK/VSvM/l73wfFieBtHimB/HGmsoBISBkH4xxh+Onnh8sysSJzswaljzEJeqmlSRm165F cJF7wro5QvkUsKHAS6UJf4WdvnWuvRD1qrw/F4+rdQApeo68viYEuKM6fjSyc4+S2kqJOiYBRp2 9WOrqXb6XeaQs1avqEXy+JLBLnnlRCuFvzES32q2nGLpbVap3wXI+FiLxNQD5CSKPTwDZ+Rvnr9 s/vRMssG34PDtRGyPl0E07RPuNlHBkgrl3ZuwEezHnA7HjEKU4UvvNTUU8pDTVGhxeiTlNCqGme yCj3RS46LCuZNpvSpHXE31gxcI+xHoOzQdPHlfuZq4hVy6eLwqtHG3TIvFDWQgwHAeiXLhl+rU/ GD0cg== X-Received: by 2002:a17:907:1c0d:b0:b88:58e5:86ff with SMTP id a640c23a62f3a-b9b51647766mr196269266b.0.1774627952962; Fri, 27 Mar 2026 09:12:32 -0700 (PDT) Received: from [172.16.220.101] (144-178-202-139.static.ef-service.nl. [144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:32 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:21 +0100 Subject: [PATCH v2 2/9] dt-bindings: display: msm-dsi-controller-main: document the Milos DSI Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-2-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=1141; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=/iuE8Of7PxtUN21ThxuyRVaZpwkJ5NvVO+YKGCgqQ64=; b=kINHrIcgMlj9z546raEXwcP6A0Lzrq1gQjA0FLzEM+5Rx5oXlRJ2E4maAJbpBS6QhgEJ6hZFp rLOVKD1c/CuAO+zU1Y1Cz+Jhso56+ar/zysDEdXku742owa567YKbMK X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the DSI Controller on the Milos Platform. Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2= ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index a24fcb914418..dbc0613e427e 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -16,6 +16,7 @@ properties: - enum: - qcom,apq8064-dsi-ctrl - qcom,kaanapali-dsi-ctrl + - qcom,milos-dsi-ctrl - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl @@ -339,6 +340,7 @@ allOf: compatible: contains: enum: + - qcom,milos-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sa8775p-dsi-ctrl - qcom,sar2130p-dsi-ctrl --=20 2.53.0 From nobody Thu Apr 2 15:37:59 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E74F6347513 for ; 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Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index dccac525d202..9da981639ddb 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -18,6 +18,7 @@ properties: - qcom,eliza-dpu - qcom,glymur-dpu - qcom,kaanapali-dpu + - qcom,milos-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu --=20 2.53.0 From nobody Thu Apr 2 15:37:59 2026 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E4D6F347FE2 for ; Fri, 27 Mar 2026 16:12:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774627960; cv=none; b=DbH21Tl75nkT/URqOS4JzmyzGG42JcE6Pk34LI859DzLEZghvLQYWPs0QrR7Mw/+5F6oJIRZmbIfFY9ni1+UDWHHoZ+hryFWOtGIUX+ZynxKESd7enJYtB8pPrkI/XQFaBOG3qP0e8fLWedI5Vbf6HYQi8EjLpxQXj+0nA+vgxE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774627960; c=relaxed/simple; bh=KtUn5G2UTlEzF/yc8/MAeH8lYJexJkFm284OdZOtjsA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L6rnEvCxDLE3tZLtwZpLGe+vWGDKrk9uzLMA5UH1HZusUTb0dvnkreBgrYafkqEof1HZb69F+DEGHoSloUIZyf/0AzDaWcdZklWipdUscVnDJJC5BDPFCgsJqH9U+CpwRMduARpvSkXvskL4n5RfkulkzFMmBLWbarcf6gf4kek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=VrD/aJIW; arc=none smtp.client-ip=209.85.218.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="VrD/aJIW" Received: by mail-ej1-f47.google.com with SMTP id a640c23a62f3a-b9358dd7f79so414363766b.1 for ; Fri, 27 Mar 2026 09:12:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1774627955; x=1775232755; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Dq7FZmaEKFcQHlwC/6geG17+uu+aaA5ZxCfFTQLxT+c=; b=VrD/aJIWqP9BmTi/wYTjfLhIFf1S60MDFEICeTv2ULEjxV5/nS4a8Q/oSCZ79nZLwc 8IM81A3W5nEXbHejsUVQ13ECYwNO364GcH8tjuCqz81NwWV+vt+jYBQyFaVwtWDMoqqj 73eHv3gJIePgjfHPGilDZ/mSNvcRo5sLG7QzrhxYk0UIi5Rgvs7wOiQai8RKfZp+LCgl bLAW5rDsQyca3swEMt8zVP1i8y78uYBJZx4YyDrgFoz/lgVur3jBE4ZLTR1R6CwamzUn NZt+GdVyWnxZAjv/BPhnYC9p3skfdvIb0DCCtJfOD4TiO98lTJPk6IFI/VAdMVEUa3g8 +PJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774627955; x=1775232755; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Dq7FZmaEKFcQHlwC/6geG17+uu+aaA5ZxCfFTQLxT+c=; b=YC6WQ5B3oEWfKdWjY0n6y5SFcgGBOm22+AzDDCbhlc/4bAof27vDsVeeZk0GGGKAoj lAPAIujq+xf9/2eRpsfgwax8XhpVYisSItChyr54yS34uCy1gmLZE3fQ9G30ZtxPOaHM ifkLp1KglXVmaLr14UMuy8lguEj6g1YQLW8IX0j27ULXqijYebVFXiw96sZORx9zEIp/ 45YRwEpSfyxC5NPm84IQQFSTf/BfFnxNuJ2IpNuvRgwqIaJXms5hvGQpXcPL9z/yQEw1 r3v5VEMphKjVaegK42zooJj+t5QPfQD0bdl/Suap4e2PFUrPzG09v/EvOId/MFMbjC17 pE2g== X-Forwarded-Encrypted: i=1; AJvYcCUliV973OSzLdS/Nvj8SiXP1C7eyT+NCzbetyksmWU9xoCecORxnAjd7xy3ZUIktrYTBSqXN6l6xewynqg=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6N+CYaDFqIKJj97amOTw9Q6a9UJbb3G7ZJW7yFU3fb0OlbNNq pIZSDKgvtQBdKtzScR7kH4lQbfJc3YkInL3zO+DNIntyztiUwgGDL2wZusqL/LYYidY= X-Gm-Gg: ATEYQzyzNZcBhzTTED7wFV1cRmnDiTtcNnLiV81Dq9pZytENv43gIA1f91+/6lbRb4W fy0QMpy08MnYmGwRNt1HwKzdXymPVtw9D4z9vMhfnDK935uVXoRY0AYIOvMTuGWw8HfNW9p6ufS bWGqhffRl5k7XmO8o6XidgD8844rOQ8nzautenGEhvMac7xOlofQkOnwBz3oFdvcMxmGw3fiTSv MnHtEj0z35XRA6ttoOgVhHce3OQDV71SuGWownHVjdTj1uYntLeIFUEpnxaeNacPntXnpuKv1m9 r2KFQ3RSQdTijZJgxwswVE8qtLsEsR33elK1uCToDqNHWug5MQbyIQkKIZsCt4FFLcMLRGnUxrK hbKoPT3pBt1A3q9xXwkCEeToOpznIpdRXIi6dBjJbzrgRp8qqODbWfMGYyZOdL34s0YXURh8qYk 0WJgbJ57UMCYHhYz3A8eDpXeC5LaSXMLAVla2rIewpM8cQbP2FtTYbx6oOmvoHfaPh79Svo1qG7 cAa1w== X-Received: by 2002:a17:907:94c2:b0:b97:bc6b:7f21 with SMTP id a640c23a62f3a-b9b4fa1aee7mr205959666b.0.1774627955130; Fri, 27 Mar 2026 09:12:35 -0700 (PDT) Received: from [172.16.220.101] (144-178-202-139.static.ef-service.nl. [144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:34 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:23 +0100 Subject: [PATCH v2 4/9] dt-bindings: display: msm: document the Milos Mobile Display Subsystem Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-4-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=9238; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=KtUn5G2UTlEzF/yc8/MAeH8lYJexJkFm284OdZOtjsA=; b=XRBDJr+T4inivP4pCestBgyjauRIBd5h9gxsYU7Sc+onWf6YvnD0LQUjqAApSV7jl/whtAR4E eTvFPG0+Te6Co++eRkdMlIQz0g81A6TkBr87kCD7dNRLZzUBawgg1LF X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Mobile Display Subsystem (MDSS) on the Milos SoC. Signed-off-by: Luca Weiss --- .../bindings/display/msm/qcom,milos-mdss.yaml | 283 +++++++++++++++++= ++++ 1 file changed, 283 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml new file mode 100644 index 000000000000..0fb66b4b2742 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml @@ -0,0 +1,283 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos Display MDSS + +maintainers: + - Luca Weiss + +description: + Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks = like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,milos-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + items: + - const: qcom,milos-dsi-ctrl + - const: qcom,mdss-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,milos-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ON= LY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_= ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,milos-dpu"; + reg =3D <0x0ae01000 0x8f000>, + <0x0aeb0000 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz =3D /bits/ 64 <342000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz =3D /bits/ 64 <402000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz =3D /bits/ 64 <535000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz =3D /bits/ 64 <630000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0ae94000 0x1000>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,milos-dsi-phy-4nm"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x300>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:35 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:24 +0100 Subject: [PATCH v2 5/9] soc: qcom: ubwc: Add config for Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-5-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=1658; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=5cRqSrO9TWRQUaD7bTpD1ZxLquZmqnEMTYi63NVSawg=; b=aIVcCFwLleXDR6BbWbAVLdZGSgSQE3T0zkh07vYu6x6K/HU3SUHpaustvo0IrxX3T00BKLHOA f+oyhjM/FIkCWLIqvrDlNpWYSCHXcofk+OrlUQkx6J2XtUJlVtSdlnu X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Describe the Universal Bandwidth Compression (UBWC) configuration for the Milos SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss --- drivers/soc/qcom/ubwc_config.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 3fe47d8f0f63..1551f270afce 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -37,6 +37,17 @@ static const struct qcom_ubwc_cfg_data kaanapali_data = =3D { .macrotile_mode =3D true, }; =20 +static const struct qcom_ubwc_cfg_data milos_data =3D { + .ubwc_enc_version =3D UBWC_4_0, + .ubwc_dec_version =3D UBWC_4_0, + .ubwc_swizzle =3D UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 14 for LP_DDR4 */ + .highest_bank_bit =3D 15, + .macrotile_mode =3D true, +}; + static const struct qcom_ubwc_cfg_data msm8937_data =3D { .ubwc_enc_version =3D UBWC_1_0, .ubwc_dec_version =3D UBWC_1_0, @@ -247,6 +258,7 @@ static const struct of_device_id qcom_ubwc_configs[] __= maybe_unused =3D { { .compatible =3D "qcom,kaanapali", .data =3D &kaanapali_data, }, { .compatible =3D "qcom,glymur", .data =3D &glymur_data}, { .compatible =3D "qcom,mahua", .data =3D &glymur_data }, + { .compatible =3D "qcom,milos", .data =3D &milos_data }, { .compatible =3D "qcom,msm8226", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8916", .data =3D &no_ubwc_data }, { .compatible =3D "qcom,msm8917", .data =3D &no_ubwc_data }, --=20 2.53.0 From nobody Thu Apr 2 15:37:59 2026 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4469334AB0D for ; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:37 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:25 +0100 Subject: [PATCH v2 6/9] drm/msm/dsi: add support for DSI-PHY on Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-6-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss , Dmitry Baryshkov X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=2987; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=MNrAIbdMcQ69eUABsCEhZ1TvMsJSWiKNRpYtVmTWOy8=; b=5SR/5qTBYNIDCGL8cuTNXwvhzYkYevnNbG5tqBVj6DaWvC5VwQFqUBefrvK3PQwf37OLko88/ 49lWJuZx0jPD32kD0ipHchOJxdTUSFwUd9ONcju8pYJK36i70aOoZXK X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add DSI PHY support for the Milos platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 23 +++++++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index c59375aaae19..1fb3899b88bf 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -571,6 +571,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_5nm_8350_cfgs }, { .compatible =3D "qcom,sm8450-dsi-phy-5nm", .data =3D &dsi_phy_5nm_8450_cfgs }, + { .compatible =3D "qcom,milos-dsi-phy-4nm", + .data =3D &dsi_phy_4nm_milos_cfgs }, { .compatible =3D "qcom,sm8550-dsi-phy-4nm", .data =3D &dsi_phy_4nm_8550_cfgs }, { .compatible =3D "qcom,sm8650-dsi-phy-4nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index c01784ca38ed..21a59d66e8dc 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -61,6 +61,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8775p_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 8f4b03713f25..984a66085dfb 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -1436,6 +1436,29 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_sar2130p_cf= gs =3D { .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, }; =20 +const struct msm_dsi_phy_cfg dsi_phy_4nm_milos_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000 }, + .num_dsi_phy =3D 1, + .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, +}; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:38 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:26 +0100 Subject: [PATCH v2 7/9] drm/msm: mdss: Add Milos support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-7-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=1279; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=toygxQND4Dvsy39S8g07OI0f5dr6V9bZ0QRD2HmiADE=; b=MTo0qnVzdsDxWJw6LPXjTeAFhO1XjHbxDt9eTdhNKswtYL3oWLKUwMh414oCixoltSCdD3INv Ta4gVCK2Mt8Cy4DLoMIVZZLGJiG+ZtoSJ01hm9y9sRRduDaP2HNEDo9 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add support for MDSS on Milos. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss --- drivers/gpu/drm/msm/msm_mdss.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 90c3fa0681a0..754ceef38717 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -550,6 +550,10 @@ static void mdss_remove(struct platform_device *pdev) msm_mdss_destroy(mdss); } =20 +static const struct msm_mdss_data data_14k =3D { + .reg_bus_bw =3D 14000, +}; + static const struct msm_mdss_data data_57k =3D { .reg_bus_bw =3D 57000, }; @@ -571,6 +575,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,eliza-mdss", .data =3D &data_57k }, { .compatible =3D "qcom,glymur-mdss", .data =3D &data_57k }, { .compatible =3D "qcom,kaanapali-mdss", .data =3D &data_57k }, + { .compatible =3D "qcom,milos-mdss", .data =3D &data_14k }, { .compatible =3D "qcom,msm8998-mdss", .data =3D &data_76k8 }, { .compatible =3D "qcom,qcm2290-mdss", .data =3D &data_76k8 }, { .compatible =3D "qcom,qcs8300-mdss", .data =3D &data_74k }, --=20 2.53.0 From nobody Thu Apr 2 15:37:59 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8766E34F24B for ; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:39 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:27 +0100 Subject: [PATCH v2 8/9] drm/msm/dpu: Add Milos support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-8-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=12018; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=iKsxeLMALhkJyLMhTvLyLfN9d/jMx3vnocKrUpXfqKI=; b=T/vsj5cUTIyUBz+q1KpOW1hiA1qpYu5VrGB+gfQ9oOjH4Izzt8gb3W3MicCEne/xqWOXeogno EuBa6ed9FuWCLuv8qnV8mbejXBDlWCZlAPd8BS6cqFBh+nia6yAoLIK X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add definitions for the display hardware used on the Qualcomm Milos platform. Signed-off-by: Luca Weiss --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h | 279 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 310 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h new file mode 100644 index 000000000000..1aa8aea4e352 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_2_milos.h @@ -0,0 +1,279 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2026, Luca Weiss + */ + +#ifndef _DPU_10_2_MILOS_H +#define _DPU_10_2_MILOS_H + +static const struct dpu_caps milos_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0x7, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg milos_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg milos_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, +}; + +static const struct dpu_sspp_cfg milos_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_3, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg milos_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .features =3D MIXER_MSM8998_MASK, + .sblk =3D &sdm845_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + }, +}; + +static const struct dpu_dspp_cfg milos_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .sblk =3D &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg milos_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + }, +}; + +static const struct dpu_merge_3d_cfg milos_merge_3d[] =3D { + { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg milos_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x6, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &milos_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x6, + .features =3D BIT(DPU_DSC_NATIVE_42x_EN), + .sblk =3D &milos_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg milos_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg milos_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x8, + }, +}; + +static const struct dpu_intf_cfg milos_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x300, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x300, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x300, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg milos_perf_data =3D { + .max_bw_low =3D 7100000, + .max_bw_high =3D 9800000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 1600000, + .min_prefill_lines =3D 40, + /* FIXME: lut tables */ + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xff00, 0xfff0, 0x0fff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version milos_mdss_ver =3D { + .core_major_ver =3D 10, + .core_minor_ver =3D 2, +}; + +const struct dpu_mdss_cfg dpu_milos_cfg =3D { + .mdss_ver =3D &milos_mdss_ver, + .caps =3D &milos_dpu_caps, + .mdp =3D &milos_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(milos_ctl), + .ctl =3D milos_ctl, + .sspp_count =3D ARRAY_SIZE(milos_sspp), + .sspp =3D milos_sspp, + .mixer_count =3D ARRAY_SIZE(milos_lm), + .mixer =3D milos_lm, + .dspp_count =3D ARRAY_SIZE(milos_dspp), + .dspp =3D milos_dspp, + .pingpong_count =3D ARRAY_SIZE(milos_pp), + .pingpong =3D milos_pp, + .dsc_count =3D ARRAY_SIZE(milos_dsc), + .dsc =3D milos_dsc, + .merge_3d_count =3D ARRAY_SIZE(milos_merge_3d), + .merge_3d =3D milos_merge_3d, + .wb_count =3D ARRAY_SIZE(milos_wb), + .wb =3D milos_wb, + .cwb_count =3D ARRAY_SIZE(milos_cwb), + .cwb =3D milos_cwb, + .intf_count =3D ARRAY_SIZE(milos_intf), + .intf =3D milos_intf, + .vbif =3D &milos_vbif, + .perf =3D &milos_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index bb4fd5fa4b22..2e10add84fd7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -454,6 +454,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 =3D { .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x10}, }; =20 +static const struct dpu_dsc_sub_blks milos_dsc_sblk_0 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x100, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF00, .len =3D 0x80}, +}; + +static const struct dpu_dsc_sub_blks milos_dsc_sblk_1 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x200, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x80}, +}; + static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 =3D { .enc =3D {.name =3D "enc", .base =3D 0x100, .len =3D 0x100}, .ctl =3D {.name =3D "ctl", .base =3D 0xF00, .len =3D 0x24}, @@ -513,6 +523,23 @@ static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot= _rdwr_cfg[] =3D { }, }; =20 +static const struct dpu_vbif_cfg milos_vbif =3D { + .len =3D 0x1074, + .features =3D BIT(DPU_VBIF_QOS_REMAP), + .xin_halt_timeout =3D 0x4000, + .qos_rp_remap_size =3D 0x40, + .qos_rt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_rt_pri_lvl), + .priority_lvl =3D sdm845_rt_pri_lvl, + }, + .qos_nrt_tbl =3D { + .npriority_lvl =3D ARRAY_SIZE(sdm845_nrt_pri_lvl), + .priority_lvl =3D sdm845_nrt_pri_lvl, + }, + .memtype_count =3D 16, + .memtype =3D {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, +}; + static const struct dpu_vbif_cfg msm8996_vbif =3D { .len =3D 0x1040, .default_ot_rd_limit =3D 32, @@ -754,6 +781,8 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_10_2_milos.h" + #include "catalog/dpu_12_0_sm8750.h" #include "catalog/dpu_12_2_glymur.h" #include "catalog/dpu_12_4_eliza.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index ba04ac24d5a9..f45faf87333e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -766,6 +766,7 @@ struct dpu_mdss_cfg { extern const struct dpu_mdss_cfg dpu_eliza_cfg; extern const struct dpu_mdss_cfg dpu_glymur_cfg; extern const struct dpu_mdss_cfg dpu_kaanapali_cfg; +extern const struct dpu_mdss_cfg dpu_milos_cfg; extern const struct dpu_mdss_cfg dpu_msm8917_cfg; extern const struct dpu_mdss_cfg dpu_msm8937_cfg; extern const struct dpu_mdss_cfg dpu_msm8953_cfg; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 35f7af4743d7..7c37bd51f934 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1483,6 +1483,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,eliza-dpu", .data =3D &dpu_eliza_cfg, }, { .compatible =3D "qcom,glymur-dpu", .data =3D &dpu_glymur_cfg, }, { .compatible =3D "qcom,kaanapali-dpu", .data =3D &dpu_kaanapali_cfg, }, + { .compatible =3D "qcom,milos-dpu", .data =3D &dpu_milos_cfg, }, { .compatible =3D "qcom,msm8917-mdp5", .data =3D &dpu_msm8917_cfg, }, { .compatible =3D "qcom,msm8937-mdp5", .data =3D &dpu_msm8937_cfg, }, { .compatible =3D "qcom,msm8953-mdp5", .data =3D &dpu_msm8953_cfg, }, --=20 2.53.0 From nobody Thu Apr 2 15:37:59 2026 Received: from mail-ed1-f47.google.com (mail-ed1-f47.google.com [209.85.208.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBCBD3537C0 for ; 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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b9b20265cc0sm273518366b.15.2026.03.27.09.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 09:12:40 -0700 (PDT) From: Luca Weiss Date: Fri, 27 Mar 2026 17:12:28 +0100 Subject: [PATCH v2 9/9] arm64: dts: qcom: milos: Add display (MDSS) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-milos-mdss-v2-9-bc586683f5ca@fairphone.com> References: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> In-Reply-To: <20260327-milos-mdss-v2-0-bc586683f5ca@fairphone.com> To: Bjorn Andersson , Konrad Dybcio , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jonathan Marek , Krishna Manikandan , Neil Armstrong , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774627949; l=6556; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=OuRa4QGyn4gLjseaQdBVxKJCgJKE3/e1JsoCMaIDUuc=; b=kR8CwCxCbJ0lmNsaT1AKtyANCK1Dy7nFNBHhR/iQxUTagFiNkuNe0HM/iqXYzgP119NX+5Pg5 nsQ9392nUdgB3Ej/8+a3FjWzWzgNrxqEVHzTCBdhImqGnQTC8YKoLNc X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add device nodes for display: MDSS, DPU, DSI and DSI PHY. DisplayPort is not added for now. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/milos.dtsi | 211 ++++++++++++++++++++++++++++++++= +++- 1 file changed, 209 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 67f8ef4d524a..c1be2f43dbb8 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -3,6 +3,7 @@ * Copyright (c) 2025, Luca Weiss */ =20 +#include #include #include #include @@ -1860,6 +1861,212 @@ camcc: clock-controller@adb0000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@ae00000 { + compatible =3D "qcom,milos-mdss"; + reg =3D <0x0 0x0ae00000 0x0 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + power-domains =3D <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus =3D <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible =3D "qcom,milos-dpu"; + reg =3D <0x0 0x0ae01000 0x0 0x8f000>, + <0x0 0x0aeb0000 0x0 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-200000000 { + opp-hz =3D /bits/ 64 <200000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz =3D /bits/ 64 <342000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz =3D /bits/ 64 <402000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz =3D /bits/ 64 <535000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz =3D /bits/ 64 <630000000>; + required-opps =3D <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible =3D "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x0ae94000 0x0 0x1000>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,milos-dsi-phy-4nm"; + reg =3D <0x0 0x0ae95000 0x0 0x200>, + <0x0 0x0ae95200 0x0 0x300>, + <0x0 0x0ae95500 0x0 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible =3D "qcom,milos-dispcc"; reg =3D <0x0 0x0af00000 0x0 0x20000>; @@ -1868,8 +2075,8 @@ dispcc: clock-controller@af00000 { <&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, /* dsi0_phy_pll_out_byteclk */ - <0>, /* dsi0_phy_pll_out_dsiclk */ + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, /* dp0_phy_pll_link_clk */ <0>; /* dp0_phy_pll_vco_div_clk */ =20 --=20 2.53.0