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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:26 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:31:59 -0400 Subject: [PATCH v8 4/8] clk: divider: test: introduce additional test case for parent rate change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-4-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5710; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=bG1tTDaW55SQc5UPS13lHzafvfk0/Nz3KkwUNwECLZE=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3ba/riMdKGAhOCVhm/ArB/0jK8JcfTiK3/8TdbDf4 7vs8J+ajlIWBjEuBlkxRZYluUYFEamrbO/d0WSBmcPKBDKEgYtTACbibcDwT3O70GrG5JULWp6F iX7MSP51S+PpFB+f9R6sq0rO3ef8X8DIsNDkqNvts+6fUrLnurZ+lGNXamg+andpzdo/868pxep 95gYA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case where the parent clk rate is changed to a rate that's acceptable to both children, however the sibling clk rate is affected. The tests in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree should end up with the state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz However, child2 ends up with it's parent rate due to the way the clk core currently handles rate changes. parent 96 MHz / \ child1 child2 32 MHz 96 MHz ^^^^^^ Incorrect. Should be 24 MHz. Let's document this behavior with a kunit test since some boards are unknowingly dependent on this behavior. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk-divider_test.c | 70 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index 0991bd865da03c1e42f154b25a7f1b5760dff3c5..f1ba15f3646ae501c940b82f052= 2eeee7831492a 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -59,6 +59,26 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +static int clk_dummy_div_lcm_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *parent_hw =3D clk_hw_get_parent(hw); + + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && req->best_parent_rat= e < req->rate) + return -EINVAL; + + req->best_parent_rate =3D clk_hw_get_children_lcm(parent_hw, hw, req->rat= e); + req->best_parent_hw =3D parent_hw; + + return divider_determine_rate(hw, req, NULL, CLK_DUMMY_DIV_WIDTH, CLK_DUM= MY_DIV_FLAGS); +} + +static const struct clk_ops clk_dummy_div_lcm_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .determine_rate =3D clk_dummy_div_lcm_determine_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + struct clk_rate_change_divider_context { struct clk_dummy_context parent; struct clk_dummy_div child1, child2; @@ -83,6 +103,18 @@ clk_rate_change_divider_test_regular_ops_params[] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_regular_ops, clk_rate_change_divider_test_regular_ops_params, desc) =20 +static const struct clk_rate_change_divider_test_param +clk_rate_change_divider_test_lcm_ops_v1_params[] =3D { + { + .desc =3D "lcm_ops_v1", + .ops =3D &clk_dummy_div_lcm_ops, + .extra_child_flags =3D 0, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_lcm_ops_v1, + clk_rate_change_divider_test_lcm_ops_v1_params, desc) + static int clk_rate_change_divider_test_init(struct kunit *test) { const struct clk_rate_change_divider_test_param *param =3D test->param_va= lue; @@ -184,11 +216,49 @@ static void clk_test_rate_change_divider_2_v1(struct = kunit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is also affected. This preserves existing behavior in the = clk + * core that some drivers may be unknowingly dependent on. This test + * demonstrates that even if the clk provider picks a parent rate that's + * suitable for both children, the child's rate change also affects the + * sibling's rate with the v1 rate negotiation logic. + */ +static void clk_test_rate_change_divider_3_v1(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based coordinated rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz, and child2 at 24 MHz. + * However, the clk core by default will clobber the sibling clk rate, + * so the sibling gets the parent rate of 96 MHz. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + static struct kunit_case clk_rate_change_divider_cases[] =3D { KUNIT_CASE_PARAM(clk_test_rate_change_divider_1, clk_rate_change_divider_test_regular_ops_gen_params), KUNIT_CASE_PARAM(clk_test_rate_change_divider_2_v1, clk_rate_change_divider_test_regular_ops_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_divider_3_v1, + clk_rate_change_divider_test_lcm_ops_v1_gen_params), {} }; =20 --=20 2.53.0