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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:21 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:31:56 -0400 Subject: [PATCH v8 1/8] clk: test: export clk_dummy_rate_ops and clk_dummy_context() for other tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-1-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2985; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=jd//XrLlu9aP2VdC9ECV4WESWkR9R53GBlDDdRxDkag=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3bblPL3zyScOR7epigcDNM00+RnvSLld+8K/ntl8d 3CltpN/RykLgxgXg6yYIsuSXKOCiNRVtvfuaLLAzGFlAhnCwMUpABOp/MDwP1HIbnpS576Sy2Uv 9jt+u/6qYN6iLRv9LiwyWcsuvv6SZyPDH75vE9Xv7Pr6vo13ncMbKaFTog9O2r4tEGVfe/eUyOs eVSYA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Expose clk_dummy_rate_ops and struct clk_dummy_context so that they can be used for other clk kunit tests. This export will be used by the upcoming clk-divider test suite. For consistency with clk-fixed-rate_test.c and drivers/clk/clk-gate_test.c, the divider tests will be setup as it's own separate kernel module. The file kunit/clk.h now contains a struct clk_hw embedded by value. If kunit/clk.h is included before linux/clk-provider.h, then this will yield a compiler error since it won't know the size of struct clk_hw. Let's also go ahead and include clk-provider.h since it's a dependency here, and this lets us drop the 'struct clk' and 'struct clk_hw' at the top that are no longer needed. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 9 +++------ include/kunit/clk.h | 11 +++++++++-- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index a268d7b5d4cb28ec1f029f828c31107f8e130556..b286297bb902a0c6c8a0469d0f7= 85009416ba9a5 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 #include "kunit_clk_assigned_rates.h" #include "clk_parent_data_test.h" @@ -25,11 +26,6 @@ static const struct clk_ops empty_clk_ops =3D { }; #define DUMMY_CLOCK_RATE_1 (142 * 1000 * 1000) #define DUMMY_CLOCK_RATE_2 (242 * 1000 * 1000) =20 -struct clk_dummy_context { - struct clk_hw hw; - unsigned long rate; -}; - static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -96,11 +92,12 @@ static u8 clk_dummy_single_get_parent(struct clk_hw *hw) return 0; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:23 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:31:57 -0400 Subject: [PATCH v8 2/8] clk: divider: introduce divider kunit tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-2-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10856; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=+oyzTK+Lzg1CH5uGIexIXBHcxdz6QmRjhgU0olx27d8=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3bZTT55xze3tG0NGh9DbS81ep1ZeMrzsbljyad43H tvHUYtVOkpZGMS4GGTFFFmW5BoVRKSusr13R5MFZg4rE8gQBi5OAZjIPzWGf9oHG9Y0T7Z3uund brAvjDdc6fUVNR4rdbPZWWvfLvIL/sLIsEWg/vcH1qcHXr7+UN0hf3DSnzf7frOf+TWNPZftaY/ QLnYA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Introduce some kunit tests for the generic clk-divider.c implementation. This test suite demonstrates the current behavior of how a clock can unknowingly change the rate of it's siblings. Some boards are unknowingly dependent on this behavior, and per discussions at the 2025 Linux Plumbers Conference in Tokyo, we can't break the existing behavior. So let's add kunit tests with the current behavior so that we can be made aware if that functionality changes in the future. The tests in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. For consistency with clk-fixed-rate_test.c and drivers/clk/clk-gate_test.c, the divider tests are setup as it's own separate kernel module. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/.kunitconfig | 1 + drivers/clk/Kconfig | 7 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-divider_test.c | 212 +++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 221 insertions(+) diff --git a/drivers/clk/.kunitconfig b/drivers/clk/.kunitconfig index 8a0ea41934a2100e1bb1521ce3ad490baec76ec2..ea05b9a28c8000c647c76c4adf8= 13da97c500ab6 100644 --- a/drivers/clk/.kunitconfig +++ b/drivers/clk/.kunitconfig @@ -4,6 +4,7 @@ CONFIG_OF=3Dy CONFIG_OF_OVERLAY=3Dy CONFIG_COMMON_CLK=3Dy CONFIG_CLK_KUNIT_TEST=3Dy +CONFIG_CLK_DIVIDER_KUNIT_TEST=3Dy CONFIG_CLK_FIXED_RATE_KUNIT_TEST=3Dy CONFIG_CLK_GATE_KUNIT_TEST=3Dy CONFIG_CLK_FD_KUNIT_TEST=3Dy diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 8cc300b90b5fd9fb38ce94fcb1098810c3f52c36..ba4af56949e39249652fc414eb2= 3b44aee1d37f5 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -550,6 +550,13 @@ config CLK_KUNIT_TEST help Kunit tests for the common clock framework. =20 +config CLK_DIVIDER_KUNIT_TEST + tristate "Basic divider clk type KUnit test" if !KUNIT_ALL_TESTS + depends on KUNIT && CLK_KUNIT_TEST + default KUNIT_ALL_TESTS + help + KUnit tests for the basic divider clk type. + config CLK_FIXED_RATE_KUNIT_TEST tristate "Basic fixed rate clk type KUnit test" if !KUNIT_ALL_TESTS depends on KUNIT diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f52cf3ac64fcce7e20f3fd91f837c5096375521a..f11d37cb09423b914d7653fa4c3= fa17370430aa7 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ clk-test-y :=3D clk_test.o \ kunit_clk_hw_get_dev_of_node.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-divider.o +obj-$(CONFIG_CLK_DIVIDER_KUNIT_TEST) +=3D clk-divider_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-rate.o obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) +=3D clk-fixed-rate-test.o diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c new file mode 100644 index 0000000000000000000000000000000000000000..0991bd865da03c1e42f154b25a7= f1b5760dff3c5 --- /dev/null +++ b/drivers/clk/clk-divider_test.c @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Kunit tests for clk divider + */ +#include +#include +#include +#include + +#include +#include + +/* 4 ought to be enough for anybody */ +#define CLK_DUMMY_DIV_WIDTH 4 +#define CLK_DUMMY_DIV_FLAGS (CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ROUND_CLO= SEST) + +struct clk_dummy_div { + struct clk_hw hw; + unsigned int div; +}; + +static unsigned long clk_dummy_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + return divider_recalc_rate(hw, parent_rate, div->div, NULL, + CLK_DUMMY_DIV_FLAGS, CLK_DUMMY_DIV_WIDTH); +} + +static int clk_dummy_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && req->best_parent_rat= e < req->rate) + return -EINVAL; + + return divider_determine_rate(hw, req, NULL, CLK_DUMMY_DIV_WIDTH, CLK_DUM= MY_DIV_FLAGS); +} + +static int clk_dummy_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + int ret; + + ret =3D divider_get_val(rate, parent_rate, NULL, CLK_DUMMY_DIV_WIDTH, + CLK_DUMMY_DIV_FLAGS); + if (ret < 0) + return ret; + + div->div =3D ret; + + return 0; +} + +static const struct clk_ops clk_dummy_div_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .determine_rate =3D clk_dummy_div_determine_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + +struct clk_rate_change_divider_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1, child2; + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +struct clk_rate_change_divider_test_param { + const char *desc; + const struct clk_ops *ops; + unsigned int extra_child_flags; +}; + +static const struct clk_rate_change_divider_test_param +clk_rate_change_divider_test_regular_ops_params[] =3D { + { + .desc =3D "regular_ops", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D 0, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_regular_ops, + clk_rate_change_divider_test_regular_ops_params, desc) + +static int clk_rate_change_divider_test_init(struct kunit *test) +{ + const struct clk_rate_change_divider_test_param *param =3D test->param_va= lue; + struct clk_rate_change_divider_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D 24 * HZ_PER_MHZ; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, + param->ops, + CLK_SET_RATE_PARENT | param->extra_child_flags); + ctx->child1.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, + param->ops, + CLK_SET_RATE_PARENT | param->extra_child_flags); + ctx->child2.div =3D 1; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->parent_clk =3D clk_hw_get_clk_prepared_enabled_kunit(test, &ctx->par= ent.hw, __func__); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->parent_clk); + + ctx->child1_clk =3D clk_hw_get_clk_prepared_enabled_kunit(test, &ctx->chi= ld1.hw, __func__); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->child1_clk); + + ctx->child2_clk =3D clk_hw_get_clk_prepared_enabled_kunit(test, &ctx->chi= ld2.hw, __func__); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx->child2_clk); + + return 0; +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT set + * and one requests a rate compatible with the existing parent rate, the p= arent and + * sibling rates are not affected. + */ +static void clk_test_rate_change_divider_1(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + + ret =3D clk_set_rate(ctx->child1_clk, 6 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 6 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 4); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is also affected. This preserves existing behavior in the = clk + * core that some drivers may be unknowingly dependent on. + */ +static void clk_test_rate_change_divider_2_v1(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * The last sibling rate change is the one that was successful, and + * wins. The parent, and two children are all changed to 32 MHz. This + * keeps the long-standing behavior of the clk core that some drivers + * may be unknowingly dependent on. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); +} + +static struct kunit_case clk_rate_change_divider_cases[] =3D { + KUNIT_CASE_PARAM(clk_test_rate_change_divider_1, + clk_rate_change_divider_test_regular_ops_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_divider_2_v1, + clk_rate_change_divider_test_regular_ops_gen_params), + {} +}; + +/* + * Test suite that creates a parent with two divider-only children, and + * documents the behavior of what happens to the sibling clock when one ch= ild + * changes its rate. + */ +static struct kunit_suite clk_rate_change_divider_test_suite =3D { + .name =3D "clk-rate-change-divider", + .init =3D clk_rate_change_divider_test_init, + .test_cases =3D clk_rate_change_divider_cases, +}; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:25 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:31:58 -0400 Subject: [PATCH v8 3/8] clk: introduce new helper clk_hw_get_children_lcm() to calculate LCM of all child rates Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-3-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3927; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=zZuXuYzRXV1Ky5Xhgp7rZ3YFui3eWbaiq3f7MTmQQc0=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3bYrWtjNd2nJh47cbSui93pPnLazdunJyznJv31rX 0YJ9ZZP7yhlYRDjYpAVU2RZkmtUEJG6yvbeHU0WmDmsTCBDGLg4BWAiS1wZ/gpd7dWOydvk5Se5 YcfCjZuLHGRkvM9wu63qfSrF6O4mdp7hr3DMgYVaKzXVH0e1Fa/ac26Sikxc8q75qc/sIy0XpK3 NZAIA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Introduce a new helper that recursively walks through all children and their descendants, calculating the lowest common multiple (LCM) of their rates. For the requesting child, it uses the requested rate; for other enabled children, it uses their current rate. This is useful for determining what parent rate can satisfy all children through simple integer dividers. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk.c | 54 ++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/clk-provider.h | 2 ++ 2 files changed, 56 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 47093cda9df32223c1120c3710261296027c4cd3..bb602c07df9a2b523a72e1e05cc= 3a27956e7198b 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -838,6 +839,59 @@ void clk_hw_set_rate_range(struct clk_hw *hw, unsigned= long min_rate, } EXPORT_SYMBOL_GPL(clk_hw_set_rate_range); =20 +/** + * clk_hw_get_children_lcm - Calculate LCM of all children's rates recursi= vely + * @hw: The parent clock hardware + * @requesting_hw: The child clock that is requesting a rate change (can b= e NULL) + * @requesting_rate: The target rate for the requesting clock + * + * This helper recursively walks through all children and their descendant= s, + * calculating the lowest common multiple (LCM) of their rates. For the + * requesting child, it uses the requested rate; for other enabled childre= n, it + * uses their current rate. This is useful for determining what parent rat= e can + * satisfy all children through simple integer dividers. + * + * Returns: The LCM of all non-zero rates found in the subtree, or 0 if no= valid rates. + */ +unsigned long clk_hw_get_children_lcm(struct clk_hw *hw, struct clk_hw *re= questing_hw, + unsigned long requesting_rate) +{ + unsigned long lcm_rate =3D 0; + unsigned long child_rate; + struct clk_core *child; + + lockdep_assert_held(&prepare_lock); + + hlist_for_each_entry(child, &hw->core->children, child_node) { + /* Use requesting rate for the requesting child, current rate for others= */ + if (child->hw =3D=3D requesting_hw) { + child_rate =3D requesting_rate; + } else { + if (!clk_hw_is_enabled(child->hw)) + continue; + + child_rate =3D clk_hw_get_rate(child->hw); + } + + if (child_rate =3D=3D 0) + continue; + + if (lcm_rate =3D=3D 0) + lcm_rate =3D child_rate; + else + lcm_rate =3D lcm(lcm_rate, child_rate); + + /* Recursively get LCM of this child's children */ + child_rate =3D clk_hw_get_children_lcm(child->hw, requesting_hw, + requesting_rate); + if (child_rate > 0) + lcm_rate =3D lcm(lcm_rate, child_rate); + } + + return lcm_rate; +} +EXPORT_SYMBOL_GPL(clk_hw_get_children_lcm); + /* * __clk_mux_determine_rate - clk_ops::determine_rate implementation for a= mux type clk * @hw: mux type clk to determine rate on diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 630705a47129453c241f1b1755f2c2f2a7ed8f77..2699b9759e13d0c1f0b54f4fa4f= 7f7bdd42e8dde 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1430,6 +1430,8 @@ void clk_hw_get_rate_range(struct clk_hw *hw, unsigne= d long *min_rate, unsigned long *max_rate); void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate, unsigned long max_rate); +unsigned long clk_hw_get_children_lcm(struct clk_hw *hw, struct clk_hw *re= questing_hw, + unsigned long requesting_rate); =20 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src) { --=20 2.53.0 From nobody Thu Apr 2 14:08:19 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFA3D386C3E for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:26 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:31:59 -0400 Subject: [PATCH v8 4/8] clk: divider: test: introduce additional test case for parent rate change Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-4-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5710; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=bG1tTDaW55SQc5UPS13lHzafvfk0/Nz3KkwUNwECLZE=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3ba/riMdKGAhOCVhm/ArB/0jK8JcfTiK3/8TdbDf4 7vs8J+ajlIWBjEuBlkxRZYluUYFEamrbO/d0WSBmcPKBDKEgYtTACbibcDwT3O70GrG5JULWp6F iX7MSP51S+PpFB+f9R6sq0rO3ef8X8DIsNDkqNvts+6fUrLnurZ+lGNXamg+andpzdo/868pxep 95gYA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case where the parent clk rate is changed to a rate that's acceptable to both children, however the sibling clk rate is affected. The tests in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree should end up with the state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz However, child2 ends up with it's parent rate due to the way the clk core currently handles rate changes. parent 96 MHz / \ child1 child2 32 MHz 96 MHz ^^^^^^ Incorrect. Should be 24 MHz. Let's document this behavior with a kunit test since some boards are unknowingly dependent on this behavior. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk-divider_test.c | 70 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index 0991bd865da03c1e42f154b25a7f1b5760dff3c5..f1ba15f3646ae501c940b82f052= 2eeee7831492a 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -59,6 +59,26 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +static int clk_dummy_div_lcm_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_hw *parent_hw =3D clk_hw_get_parent(hw); + + if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && req->best_parent_rat= e < req->rate) + return -EINVAL; + + req->best_parent_rate =3D clk_hw_get_children_lcm(parent_hw, hw, req->rat= e); + req->best_parent_hw =3D parent_hw; + + return divider_determine_rate(hw, req, NULL, CLK_DUMMY_DIV_WIDTH, CLK_DUM= MY_DIV_FLAGS); +} + +static const struct clk_ops clk_dummy_div_lcm_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .determine_rate =3D clk_dummy_div_lcm_determine_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + struct clk_rate_change_divider_context { struct clk_dummy_context parent; struct clk_dummy_div child1, child2; @@ -83,6 +103,18 @@ clk_rate_change_divider_test_regular_ops_params[] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_regular_ops, clk_rate_change_divider_test_regular_ops_params, desc) =20 +static const struct clk_rate_change_divider_test_param +clk_rate_change_divider_test_lcm_ops_v1_params[] =3D { + { + .desc =3D "lcm_ops_v1", + .ops =3D &clk_dummy_div_lcm_ops, + .extra_child_flags =3D 0, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_lcm_ops_v1, + clk_rate_change_divider_test_lcm_ops_v1_params, desc) + static int clk_rate_change_divider_test_init(struct kunit *test) { const struct clk_rate_change_divider_test_param *param =3D test->param_va= lue; @@ -184,11 +216,49 @@ static void clk_test_rate_change_divider_2_v1(struct = kunit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is also affected. This preserves existing behavior in the = clk + * core that some drivers may be unknowingly dependent on. This test + * demonstrates that even if the clk provider picks a parent rate that's + * suitable for both children, the child's rate change also affects the + * sibling's rate with the v1 rate negotiation logic. + */ +static void clk_test_rate_change_divider_3_v1(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based coordinated rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz, and child2 at 24 MHz. + * However, the clk core by default will clobber the sibling clk rate, + * so the sibling gets the parent rate of 96 MHz. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:28 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:32:00 -0400 Subject: [PATCH v8 5/8] clk: introduce new flag CLK_V2_RATE_NEGOTIATION for sensitive clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-5-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7264; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=/tQL4+ZIoUSIasZYpJHwSdSiMqSkhfJfugUapZTcEGE=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3Xawefnt69eDv4N+Sh7c9WdyQ5C9Oaua5f2gB4t2M 136cOXG3I5SFgYxLgZZMUWWJblGBRGpq2zv3dFkgZnDygQyhIGLUwAmsrie4Tdr1M5HjGZvOw6X a59daieev8zAxFDiPlfulsqZZ0wU/YwY/vDlTJxat/vvDk9+17xI7lWZxnc3nNt9cPXq1I2xe81 Yt7EDAA== X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 As demonstrated by the kunit tests, clk_calc_subtree() in the clk core can overwrite a sibling clk with the parent rate. Clocks that are used for some subsystems like DRM and sound are particularly sensitive to this issue. I consider this to be a logic bug in the clk subsystem, however this functionality has existed since the clk core was introduced with commit b2476490ef11 ("clk: introduce the common clock framework"), and some boards are unknowingly dependent on this behavior. Let's add support for a v2 rate negotiation logic that addresses the logic error. Clks can opt into this new behavior by adding the flag CLK_V2_RATE_NEGOTIATION. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk.c | 60 ++++++++++++++++++++++++++++++++++------= ---- include/linux/clk-provider.h | 3 +++ 2 files changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index bb602c07df9a2b523a72e1e05cc3a27956e7198b..46b3c4c596043abff0be2552fee= 09c4ce2f15dfb 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -892,6 +892,33 @@ unsigned long clk_hw_get_children_lcm(struct clk_hw *h= w, struct clk_hw *requesti } EXPORT_SYMBOL_GPL(clk_hw_get_children_lcm); =20 +/** + * clk_has_v2_rate_negotiation - Check if a clk should use v2 rate negotia= tion + * @core: The clock core to check + * + * This function recursively checks if the clk or any of its descendants h= ave + * the CLK_V2_RATE_NEGOTIATION flag set. + * + * Returns: true if the v2 logic should be used; false otherwise + */ +bool clk_has_v2_rate_negotiation(const struct clk_core *core) +{ + struct clk_core *child; + + lockdep_assert_held(&prepare_lock); + + if (core->flags & CLK_V2_RATE_NEGOTIATION) + return true; + + hlist_for_each_entry(child, &core->children, child_node) { + if (clk_has_v2_rate_negotiation(child)) + return true; + } + + return false; +} +EXPORT_SYMBOL_GPL(clk_has_v2_rate_negotiation); + /* * __clk_mux_determine_rate - clk_ops::determine_rate implementation for a= mux type clk * @hw: mux type clk to determine rate on @@ -2299,7 +2326,8 @@ static int __clk_speculate_rates(struct clk_core *cor= e, } =20 static void clk_calc_subtree(struct clk_core *core, unsigned long new_rate, - struct clk_core *new_parent, u8 p_index) + struct clk_core *new_parent, u8 p_index, + struct clk_core *initiating_clk) { struct clk_core *child; =20 @@ -2312,8 +2340,12 @@ static void clk_calc_subtree(struct clk_core *core, = unsigned long new_rate, new_parent->new_child =3D core; =20 hlist_for_each_entry(child, &core->children, child_node) { - child->new_rate =3D clk_recalc(child, new_rate); - clk_calc_subtree(child, child->new_rate, NULL, 0); + if (child !=3D initiating_clk && clk_has_v2_rate_negotiation(child)) + child->new_rate =3D child->rate; + else + child->new_rate =3D clk_recalc(child, new_rate); + + clk_calc_subtree(child, child->new_rate, NULL, 0, initiating_clk); } } =20 @@ -2322,7 +2354,8 @@ static void clk_calc_subtree(struct clk_core *core, u= nsigned long new_rate, * changed. */ static struct clk_core *clk_calc_new_rates(struct clk_core *core, - unsigned long rate) + unsigned long rate, + struct clk_core *initiating_clk) { struct clk_core *top =3D core; struct clk_core *old_parent, *parent; @@ -2370,7 +2403,7 @@ static struct clk_core *clk_calc_new_rates(struct clk= _core *core, return NULL; } else { /* pass-through clock with adjustable parent */ - top =3D clk_calc_new_rates(parent, rate); + top =3D clk_calc_new_rates(parent, rate, initiating_clk); new_rate =3D parent->new_rate; goto out; } @@ -2395,10 +2428,10 @@ static struct clk_core *clk_calc_new_rates(struct c= lk_core *core, =20 if ((core->flags & CLK_SET_RATE_PARENT) && parent && best_parent_rate !=3D parent->rate) - top =3D clk_calc_new_rates(parent, best_parent_rate); + top =3D clk_calc_new_rates(parent, best_parent_rate, initiating_clk); =20 out: - clk_calc_subtree(core, new_rate, parent, p_index); + clk_calc_subtree(core, new_rate, parent, p_index, initiating_clk); =20 return top; } @@ -2446,7 +2479,7 @@ static struct clk_core *clk_propagate_rate_change(str= uct clk_core *core, * walk down a subtree and set the new rates notifying the rate * change on the way */ -static void clk_change_rate(struct clk_core *core) +static void clk_change_rate(struct clk_core *core, struct clk_core *initia= ting_clk) { struct clk_core *child; struct hlist_node *tmp; @@ -2515,7 +2548,7 @@ static void clk_change_rate(struct clk_core *core) __clk_notify(core, POST_RATE_CHANGE, old_rate, core->rate); =20 if (core->flags & CLK_RECALC_NEW_RATES) - (void)clk_calc_new_rates(core, core->new_rate); + (void)clk_calc_new_rates(core, core->new_rate, initiating_clk); =20 /* * Use safe iteration, as change_rate can actually swap parents @@ -2525,12 +2558,12 @@ static void clk_change_rate(struct clk_core *core) /* Skip children who will be reparented to another clock */ if (child->new_parent && child->new_parent !=3D core) continue; - clk_change_rate(child); + clk_change_rate(child, initiating_clk); } =20 /* handle the new child who might not be in core->children yet */ if (core->new_child) - clk_change_rate(core->new_child); + clk_change_rate(core->new_child, initiating_clk); =20 clk_pm_runtime_put(core); } @@ -2586,7 +2619,7 @@ static int clk_core_set_rate_nolock(struct clk_core *= core, return -EBUSY; =20 /* calculate new rates and get the topmost changed clock */ - top =3D clk_calc_new_rates(core, req_rate); + top =3D clk_calc_new_rates(core, req_rate, core); if (!top) return -EINVAL; =20 @@ -2605,7 +2638,7 @@ static int clk_core_set_rate_nolock(struct clk_core *= core, } =20 /* change the rates */ - clk_change_rate(top); + clk_change_rate(top, core); =20 core->req_rate =3D req_rate; err: @@ -3592,6 +3625,7 @@ static const struct { ENTRY(CLK_IS_CRITICAL), ENTRY(CLK_OPS_PARENT_ENABLE), ENTRY(CLK_DUTY_CYCLE_PARENT), + ENTRY(CLK_V2_RATE_NEGOTIATION), #undef ENTRY }; =20 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2699b9759e13d0c1f0b54f4fa4f7f7bdd42e8dde..e0fc0bd347e5920e999ac96dbed= 9fc247f9443fa 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -32,6 +32,8 @@ #define CLK_OPS_PARENT_ENABLE BIT(12) /* duty cycle call may be forwarded to the parent clock */ #define CLK_DUTY_CYCLE_PARENT BIT(13) +/* clock participates in v2 rate negotiation */ +#define CLK_V2_RATE_NEGOTIATION BIT(14) =20 struct clk; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:29 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:32:01 -0400 Subject: [PATCH v8 6/8] clk: divider: enable optional support for v2 rate negotiation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-6-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1850; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=gXVpbmRUrHdkNzhTN3R4KUVLypWKOnrMf6+semS15g4=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3XaoFFYW9lDr0J64RWUVb4tm48O/K9dllm+aV51l6 iI/zaGwo5SFQYyLQVZMkWVJrlFBROoq23t3NFlg5rAygQxh4OIUgIn0ZzD8lY1bbiRvx1pQfYGl ZwVrktyKEO5XbMop97eHZTvetU25wsjwor1gZ5qy8PaHurndx3xYXb88lXU4XD3fMO/0nWP7p95 mBwA= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 If the v2 rate negotiation logic is enabled in this portion of the clk subtree, then use the Lowest Common Multiple (LCM) of all of the child rates to determine what the parent rate should be. Make this change for clk_divider_bestdiv (used by clk_divider_determine_rate), and divider_ro_determine_rate. Note that the v2 rate negotiation logic is disabled by default, unless a clk in this portion of the subtree has the flag CLK_V2_RATE_NEGOTIATION. This change was tested on a Thinkpad x13s laptop. Some clks used this new code, however this needs to be tested on more real systems. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk-divider.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index 45e7ebde4a8b4d6572aa9d867a6f12f6caf8aae4..713f3c0baccb13bfb32581a5517= da21720b34961 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -315,6 +315,21 @@ static int clk_divider_bestdiv(struct clk_hw *hw, stru= ct clk_hw *parent, return bestdiv; } =20 + if (parent && clk_has_v2_rate_negotiation(parent->core)) { + unsigned long lcm_rate; + + lcm_rate =3D clk_hw_get_children_lcm(parent, hw, rate); + if (lcm_rate > 0) { + /* Validate and use what the parent can actually provide */ + lcm_rate =3D clk_hw_round_rate(parent, lcm_rate); + *best_parent_rate =3D lcm_rate; + bestdiv =3D _div_round(table, lcm_rate, rate, flags); + bestdiv =3D bestdiv =3D=3D 0 ? 1 : bestdiv; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:31 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:32:02 -0400 Subject: [PATCH v8 7/8] clk: divider: test: introduce additional test case showing v2 rate change + LCM parent Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-7-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4963; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=RGguDxs0mpixqcCPoxM/eD7hdhypb/MfsPjPm5+1CyE=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3XZ8V+pxWX/lDFF1hWf/tpc23uz1VNu63E5XsDX5q G/qozqxjlIWBjEuBlkxRZYluUYFEamrbO/d0WSBmcPKBDKEgYtTACbyzJXhf+lN57V2UoveTTyT 73b3THNNQw7nPpYZzYGJR96XH1/lIM3wi2nPg3L55yLvtxtMbnu2K6TugxvPy+KwSp6spktKUU/ 7mAE= X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Add a test case that uses the clk divider with the v2 rate negotiation logic, plus the Lowest Common Multiple (LCM) to calculate the optimal parent rate. The test ensures that the parent clk rate is set to a rate that's acceptable to both children, and the sibling clock is not affected. The test in this commit use the following simplified clk tree with the initial state: parent 24 MHz / \ child1 child2 24 MHz 24 MHz child1 and child2 both divider-only clocks that have CLK_SET_RATE_PARENT set, and the parent is capable of achieving any rate. child1 requests 32 MHz, and the tree ends up with the correct state: parent 96 MHz / \ child1 child2 32 MHz 24 MHz Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk-divider_test.c | 54 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index f1ba15f3646ae501c940b82f0522eeee7831492a..b55c822dfff018452f0a3acd4ad= 7ccec6f1259d4 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -115,6 +115,18 @@ clk_rate_change_divider_test_lcm_ops_v1_params[] =3D { KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_lcm_ops_v1, clk_rate_change_divider_test_lcm_ops_v1_params, desc) =20 +static const struct clk_rate_change_divider_test_param +clk_rate_change_divider_test_regular_ops_v2_params[] =3D { + { + .desc =3D "regular_ops_v2", + .ops =3D &clk_dummy_div_ops, + .extra_child_flags =3D CLK_V2_RATE_NEGOTIATION, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_rate_change_divider_test_regular_ops_v2, + clk_rate_change_divider_test_regular_ops_v2_params, desc) + static int clk_rate_change_divider_test_init(struct kunit *test) { const struct clk_rate_change_divider_test_param *param =3D test->param_va= lue; @@ -183,6 +195,11 @@ static void clk_test_rate_change_divider_1(struct kuni= t *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +static inline bool __clk_has_v2_negotiation(struct clk *clk) +{ + return clk_hw_get_flags(__clk_get_hw(clk)) & CLK_V2_RATE_NEGOTIATION; +} + /* * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT * set and one requests a rate incompatible with the existing parent rate,= the @@ -252,6 +269,39 @@ static void clk_test_rate_change_divider_3_v1(struct k= unit *test) KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); } =20 +/* + * Test that, for a parent with two divider-only children with CLK_SET_RAT= E_PARENT + * set and one requests a rate incompatible with the existing parent rate,= the + * sibling rate is not affected, and maintains it's rate when the v2 rate + * negotiation logic is used. + */ +static void clk_test_rate_change_divider_4_v2(struct kunit *test) +{ + struct clk_rate_change_divider_context *ctx =3D test->priv; + int ret; + + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->parent_clk), 24 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child1_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); + KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + KUNIT_ASSERT_TRUE(test, __clk_has_v2_negotiation(ctx->child1_clk)); + KUNIT_ASSERT_TRUE(test, __clk_has_v2_negotiation(ctx->child2_clk)); + + ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + /* + * With LCM-based parent + v2 rate changes, the parent should be at + * 96 MHz (LCM of 32 and 24), child1 at 32 MHz, and child2 at 24 MHz. + */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), 96 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), 32 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 3); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 4); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-50bb2c678e9sm2037551cf.6.2026.03.27.12.32.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Mar 2026 12:32:33 -0700 (PDT) From: Brian Masney Date: Fri, 27 Mar 2026 15:32:03 -0400 Subject: [PATCH v8 8/8] clk: divider: test: mark some tests as supporting only v1 negotiation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-clk-scaling-v8-8-86cd0aba3c5f@redhat.com> References: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> In-Reply-To: <20260327-clk-scaling-v8-0-86cd0aba3c5f@redhat.com> To: Michael Turquette , Stephen Boyd , Maxime Ripard , Alberto Ruiz , Brendan Higgins , David Gow , Rae Moar Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, kunit-dev@googlegroups.com, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2823; i=bmasney@redhat.com; s=20250903; h=from:subject:message-id; bh=6+2kBP0xFMlyP7Rqf4y/vpPGQhqSzW8u5Cx4E55/a6I=; b=owGbwMvMwCW2/dJd9di6A+2Mp9WSGDKP3XaK2NLdx2Ugd9FG46zFttpNfQH3G/Vtzj+auNB1b cSR/W0CHaUsDGJcDLJiiixLco0KIlJX2d67o8kCM4eVCWQIAxenAEwkxZuR4Z1U9auiv38O3d02 O9fZo3DqhruMAQ9KTJxcdTcwKa9+fpmR4ezTjYt17+2Z+LzTfuKuj/7fTnyT8/fiemN2p2pjMYe ZNxMA X-Developer-Key: i=bmasney@redhat.com; a=openpgp; fpr=A46D32705865AA3DDEDC2904B7D2DD275D7EC087 Mark the tests that only support v1 negotiation to make it clear exactly which behavior is under test. Link: https://lore.kernel.org/linux-clk/aUSWU7UymULCXOeF@redhat.com/ Link: https://lpc.events/event/19/contributions/2152/ Signed-off-by: Brian Masney --- drivers/clk/clk-divider_test.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index b55c822dfff018452f0a3acd4ad7ccec6f1259d4..e985b19a2b5ea4b8e7a1ba78631= f7ba3a19f625b 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -59,6 +59,15 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +/* + * clk-divider.c has support for v2 rate negotiation, and setting the pare= nt + * based on the LCM, however we need to be able to test just setting the p= arent + * rate based on the LCM, and not set the v2 rate negotiation flag. This i= s to + * demonstrate existing behavior in the clk core when a parent rate that's + * suitable for all children is selected, a sibling will still have its ra= te + * negatively affected. Some boards may be unknowingly dependent on this + * behavior, and we want to ensure this behavior stays the same. + */ static int clk_dummy_div_lcm_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) { @@ -184,6 +193,7 @@ static void clk_test_rate_change_divider_1(struct kunit= *test) KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + /* This test is expected to work with both v1 and v2 rate negotiation. */ =20 ret =3D clk_set_rate(ctx->child1_clk, 6 * HZ_PER_MHZ); KUNIT_ASSERT_EQ(test, ret, 0); @@ -216,6 +226,8 @@ static void clk_test_rate_change_divider_2_v1(struct ku= nit *test) KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + KUNIT_ASSERT_FALSE(test, __clk_has_v2_negotiation(ctx->child1_clk)); + KUNIT_ASSERT_FALSE(test, __clk_has_v2_negotiation(ctx->child2_clk)); =20 ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); KUNIT_ASSERT_EQ(test, ret, 0); @@ -252,6 +264,8 @@ static void clk_test_rate_change_divider_3_v1(struct ku= nit *test) KUNIT_EXPECT_EQ(test, ctx->child1.div, 1); KUNIT_ASSERT_EQ(test, clk_get_rate(ctx->child2_clk), 24 * HZ_PER_MHZ); KUNIT_EXPECT_EQ(test, ctx->child2.div, 1); + KUNIT_ASSERT_FALSE(test, __clk_has_v2_negotiation(ctx->child1_clk)); + KUNIT_ASSERT_FALSE(test, __clk_has_v2_negotiation(ctx->child2_clk)); =20 ret =3D clk_set_rate(ctx->child1_clk, 32 * HZ_PER_MHZ); KUNIT_ASSERT_EQ(test, ret, 0); --=20 2.53.0