From nobody Thu Apr 2 20:09:07 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B4052135C5 for ; Fri, 27 Mar 2026 00:15:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774570511; cv=none; b=kVDPRbual+shxqnSDvWls8JCLSY8vByrIzqGlVir7zD/LZOevsy2A3bBdTpu8tG2mRZa30r3jTP+KSL2SYzvlwsmJO3XllnGVijOA3a6ZJhCTBqkEa4vuV7my+Bf5flGOblsgMKeq7Hrlqhp6/osWTCDPo9nMuB3ZHw5ckILOnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774570511; c=relaxed/simple; bh=M9qFPBPHvOVkzFgb15PLQYpEYj0jbBPh3xPS4yjPqmw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=B7QNrPGMLQ/lSLefr/+4ZoULKXRgawS00CN1TZJ75+XOP06sUBDTAWQiXiTj6f2GhBJ4l6MuTjnID83kluZpwWRqxMZTZVx5JNbuVbDIpbX5pt0w3fKOSzU6luSsrXkqn7CFzhhEmjuyU29stdJlSEW70fGVa/0P8fYlhOKLgkw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YCd9dkAp; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=jcfLB3KI; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YCd9dkAp"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="jcfLB3KI" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62QKYSkw519106 for ; Fri, 27 Mar 2026 00:15:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= xXqAWNz0JnVqrMWKQ5HyyfU+1Bz5ahMZW6TXdTM85Uc=; b=YCd9dkApvJLtvNnP e35VRUe12AqIjkWdybT71XzaTa4iV5WbDm47ihqQocIWoMVg6HEO7WGDXqv6BEPw 6qlg+6tMZbtBrrGugopvE2e6UWXMQ24/Qlfx6flrnbnwypcrqLdoddrQR/CbMxi+ 1NzU+EtbxRi9HgqUncrxPAJ8GkTEL7a7t8YZIZr93j791i514cMlQYVMFF63rODO aZygboPYGYOzIqJSSKUCpbcf8N10oE8mVcugsHKaxzFM2DBIbRbbfSvg6LQEflOp /RSaLJzLSUrGl8wGLgHgrlrnVRs8WL5/biwOYCV+F2nLsMFs8eE+sjJZI97NFDmK 5uRA4Q== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4d5bxv0h4j-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 27 Mar 2026 00:15:08 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-358e95e81aeso4830429a91.0 for ; Thu, 26 Mar 2026 17:15:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1774570508; x=1775175308; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xXqAWNz0JnVqrMWKQ5HyyfU+1Bz5ahMZW6TXdTM85Uc=; b=jcfLB3KIxoGsRXS1Nbhg9osNsaIlEp/5n7kHnPAFficIjxEF3C7LiJqH0XwRVDYCFv GTX6qQnTfzLdf8xn3hc/4lSyWMpmXkgOj/NJT0pQioB1wjhj+hwtXv8MXpK40iJaf0li 9BVbUL19nxHSA6q6B2Jd4Su2ui1A0P1Xz5d9NHOZM6Dk2tewEJzWsP0aX4SRkDbrlmoq fFdMZYCQ2L+ts/+at/Kb2dldSNiUVBgKnuP3NJtUhwsFL4pa+jSu78urg2zzmSlVLrJB 7WU5ah3HZDuXONzvW56MHEvQdINhJHa2964sT0vA+jMov7hsnGFTVYAlkLUXotFtZCmg 6HzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1774570508; x=1775175308; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=xXqAWNz0JnVqrMWKQ5HyyfU+1Bz5ahMZW6TXdTM85Uc=; b=rS9bKYXsFcT04esyzYIW+cO2n3YlTCCiRs6achAIObGIb9Vz6pdW56QBmKThhVAkMq fCMwPFPusFIRRRwzBoPt8ctE/STJNdl/ezR/MpcmkRjkK6ZNisblx8rV8HkYY3YlfQXn X5GFXzBPIJmh+J2piW182Ibmu6FpE7+MGejFWgvQ8RDGBruoBmkRlPXhSLVsSTqArdHd I/g+isHb/OCRSs9E1+JLE1WmFxqgzjUcM0Ze4f+FRsiarfL/ebfQJr9184+1QPPLklPx 21YjrN4b3fJCGGjPxiF4iYNB3iy1dgUGiJgQN9m8RRbUterslUMoM1JXKt64ituO8uBd BPMw== X-Forwarded-Encrypted: i=1; AJvYcCU/Zm+lqDcNjUWr1UShEPh4Ltf64MJs6ru6ESzM3/m7zLP1XkGuYWh48wT6EL6ocfsS9VPYcWSiSpojAyw=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9bbvDO9j6RRipdDVZulGOBCW/T5d9x2ldE+CUinnoiAYeu7+n kv62bRwMdfzDAu+gw2n2XupBM0GQHt7H8jtEXrSx6jDYfkDqmn9nQahsMBjZgHjnvk7mJYVEAg1 mVJ1E5f/ayW5KZ1WpSV0UwREr3RJjcbiEv2LEWXAr1PVmSj4NaEk3gmgHN+Txjrn2NRtH1FXw48 c= X-Gm-Gg: ATEYQzwJfxQo6EMGfMgeh/pm9ddF0NYDLrmswLfrFfWlKH0oUxr8JWaZYxhccGXK43Y DfTTu9Bos0DT49e77LT5Qr/Vwqua4bRY0pStKsdkYIeVaDNwGzDZylyTtXQTjC6NDbs5AjY+6w5 BulXF0Mzg1L0l4sH0hkaZ09qXD0kudgVNDeLaxxKORbcnYTC7X1uofmIQOz8ewvASCMQVlNvn5g /uiPmOy2Fa9E2mWtSSSnjkuu3/yeYPdPUiaZVp/bUdcCtPgq2sI0t2/gCHQvroVnNfNVMD2nr0l yZ6NbDiOiQt2s4jjAM1b67gbstgFDKDlq6hu5QwqOMyEZ4f0HGWhplJ3TrzlB7Y5Wc+Aj9iwrCp bDrYjNJisiqFL6DqfXZ1nqTpPXheCdnbZ/iypJAp6bqntJQ== X-Received: by 2002:a17:90b:380d:b0:35c:d98:d684 with SMTP id 98e67ed59e1d1-35c2ff07d39mr491419a91.6.1774570507891; Thu, 26 Mar 2026 17:15:07 -0700 (PDT) X-Received: by 2002:a17:90b:380d:b0:35c:d98:d684 with SMTP id 98e67ed59e1d1-35c2ff07d39mr491362a91.6.1774570507239; Thu, 26 Mar 2026 17:15:07 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35c2ec799eesm163155a91.10.2026.03.26.17.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 17:15:06 -0700 (PDT) From: Akhil P Oommen Date: Fri, 27 Mar 2026 05:43:55 +0530 Subject: [PATCH v2 06/17] drm/msm/a6xx: Fix gpu init from secure world Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260327-a8xx-gpu-batch2-v2-6-2b53c38d2101@oss.qualcomm.com> References: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> In-Reply-To: <20260327-a8xx-gpu-batch2-v2-0-2b53c38d2101@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Antonino Maniscalco , Connor Abbott , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1774570466; l=8051; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=M9qFPBPHvOVkzFgb15PLQYpEYj0jbBPh3xPS4yjPqmw=; b=QpWl3tj4DUArud0yv+weIy4uWXcGZXZ1GwP1HTdHRcJEBFK548SJIEqz2Cx/OfHB8A4aAYN5+ H7DD88YxRzJCRpERzZXYJBtL9XIpJ+IQuBSCRXMHiMAZVkmzHaJh6do X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Authority-Analysis: v=2.4 cv=A99h/qWG c=1 sm=1 tr=0 ts=69c5cc0c cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=_DJ2r0yCx7h-TLoshVgA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-ORIG-GUID: WFXC_2Wc47MgJhUCdun2ZPJwLxWC7xcV X-Proofpoint-GUID: WFXC_2Wc47MgJhUCdun2ZPJwLxWC7xcV X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzI3MDAwMCBTYWx0ZWRfX8eZb+asGi3DN 4WMsOyZqBameOiOFs/g8hzEQnXo9W9h5Vtih4hLcbaGF2A9loSXlGsX+M2cq9hGMSQprk/qCkRq RVAwya8pZGRP32XXr+wAoZuRttYuWFpUg3QovVYGl5T8+g8OVQ9VlTpnJc1GLXEDtQ8PKdZCxHS s0EnsaDFVBKq8d5wcR6m3kDqcFd84NbU0UktEFpmBWohVi6Ik7HajJvzpPzryOn2MSp+JS3rBLW Cr6r9IFNCMf13gP/v8lj1t33lU+gD25UH5Y9GyIk3QuZUKefBJJoT8DCowafFgtzD2swYroyDjx ESHZqu9HZ3bcy+GtrReRiLu1ndHINyR3Mw6PGxRNGFwXsxEHeD0JHvoAl0Xfe+1DwlmiKbrjNnv qLS13+Sz6aQBzHbdrtpKYhXnE78I1sSIY1wl0q/BGHMguQvjLYZCAFqUDVcvoKa+Nv3Lh5K9+gT S94GLmmEsgBQdQHzdcg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-26_04,2026-03-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603270000 A7XX_GEN2 and newer GPUs requires initialization of few configurations related to features/power from secure world. The SCM call to do this should be triggered after GDSC and clocks are enabled. So, keep this sequence to a6xx_gmu_resume instead of the probe. Also, simplify the error handling in a6xx_gmu_resume() using 'goto' labels. Fixes: 14b27d5df3ea ("drm/msm/a7xx: Initialize a750 "software fuse"") Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 93 +++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 2 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 59 ---------------------- 3 files changed, 80 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.c index b41dbca1ebc6..1b44b9e21ad8 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -3,6 +3,7 @@ =20 #include #include +#include #include #include #include @@ -1191,6 +1192,65 @@ static void a6xx_gmu_set_initial_bw(struct msm_gpu *= gpu, struct a6xx_gmu *gmu) dev_pm_opp_put(gpu_opp); } =20 +static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu) +{ + struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; + struct msm_gpu *gpu =3D &adreno_gpu->base; + struct a6xx_gmu *gmu =3D &a6xx_gpu->gmu; + u32 fuse_val; + int ret; + + if (test_bit(GMU_STATUS_SECURE_INIT, &gmu->status)) + return 0; + + if (adreno_is_a750(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { + /* + * Assume that if qcom scm isn't available, that whatever + * replacement allows writing the fuse register ourselves. + * Users of alternative firmware need to make sure this + * register is writeable or indicate that it's not somehow. + * Print a warning because if you mess this up you're about to + * crash horribly. + */ + if (!qcom_scm_is_available()) { + dev_warn_once(gpu->dev->dev, + "SCM is not available, poking fuse register\n"); + a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, + A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | + A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | + A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); + adreno_gpu->has_ray_tracing =3D true; + goto done; + } + + ret =3D qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | + QCOM_SCM_GPU_TSENSE_EN_REQ); + if (ret) { + dev_warn_once(gpu->dev->dev, + "SCM call failed\n"); + return ret; + } + + /* + * On A7XX_GEN3 and newer, raytracing may be disabled by the + * firmware, find out whether that's the case. The scm call + * above sets the fuse register. + */ + fuse_val =3D a6xx_llc_read(a6xx_gpu, + REG_A7XX_CX_MISC_SW_FUSE_VALUE); + adreno_gpu->has_ray_tracing =3D + !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); + } else if (adreno_is_a740(adreno_gpu)) { + /* Raytracing is always enabled on a740 */ + adreno_gpu->has_ray_tracing =3D true; + } + +done: + set_bit(GMU_STATUS_SECURE_INIT, &gmu->status); + return 0; +} + + int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; @@ -1219,11 +1279,12 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) clk_set_rate(gmu->hub_clk, adreno_is_a740_family(adreno_gpu) ? 200000000 : 150000000); ret =3D clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); - if (ret) { - pm_runtime_put(gmu->gxpd); - pm_runtime_put(gmu->dev); - return ret; - } + if (ret) + goto rpm_put; + + ret =3D a6xx_gmu_secure_init(a6xx_gpu); + if (ret) + goto disable_clk; =20 /* Read the slice info on A8x GPUs */ a8xx_gpu_get_slice_info(gpu); @@ -1253,11 +1314,11 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) =20 ret =3D a6xx_gmu_fw_start(gmu, status); if (ret) - goto out; + goto disable_irq; =20 ret =3D a6xx_hfi_start(gmu, status); if (ret) - goto out; + goto disable_irq; =20 /* * Turn on the GMU firmware fault interrupt after we know the boot @@ -1270,14 +1331,16 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Set the GPU to the current freq */ a6xx_gmu_set_initial_freq(gpu, gmu); =20 -out: - /* On failure, shut down the GMU to leave it in a good state */ - if (ret) { - disable_irq(gmu->gmu_irq); - a6xx_rpmh_stop(gmu); - pm_runtime_put(gmu->gxpd); - pm_runtime_put(gmu->dev); - } + return 0; + +disable_irq: + disable_irq(gmu->gmu_irq); + a6xx_rpmh_stop(gmu); +disable_clk: + clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); +rpm_put: + pm_runtime_put(gmu->gxpd); + pm_runtime_put(gmu->dev); =20 return ret; } diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/ad= reno/a6xx_gmu.h index 9f09daf45ab2..0cd8ae1b4f5c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h @@ -130,6 +130,8 @@ struct a6xx_gmu { #define GMU_STATUS_PDC_SLEEP 1 /* To track Perfcounter OOB set status */ #define GMU_STATUS_OOB_PERF_SET 2 +/* To track whether secure world init was done */ +#define GMU_STATUS_SECURE_INIT 3 unsigned long status; }; =20 diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c index 8718919c7e19..5cddfc03828f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -10,7 +10,6 @@ =20 #include #include -#include #include #include =20 @@ -2160,56 +2159,6 @@ static void a6xx_llc_slices_init(struct platform_dev= ice *pdev, a6xx_gpu->llc_mmio =3D ERR_PTR(-EINVAL); } =20 -static int a7xx_cx_mem_init(struct a6xx_gpu *a6xx_gpu) -{ - struct adreno_gpu *adreno_gpu =3D &a6xx_gpu->base; - struct msm_gpu *gpu =3D &adreno_gpu->base; - u32 fuse_val; - int ret; - - if (adreno_is_a750(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { - /* - * Assume that if qcom scm isn't available, that whatever - * replacement allows writing the fuse register ourselves. - * Users of alternative firmware need to make sure this - * register is writeable or indicate that it's not somehow. - * Print a warning because if you mess this up you're about to - * crash horribly. - */ - if (!qcom_scm_is_available()) { - dev_warn_once(gpu->dev->dev, - "SCM is not available, poking fuse register\n"); - a6xx_llc_write(a6xx_gpu, REG_A7XX_CX_MISC_SW_FUSE_VALUE, - A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING | - A7XX_CX_MISC_SW_FUSE_VALUE_FASTBLEND | - A7XX_CX_MISC_SW_FUSE_VALUE_LPAC); - adreno_gpu->has_ray_tracing =3D true; - return 0; - } - - ret =3D qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | - QCOM_SCM_GPU_TSENSE_EN_REQ); - if (ret) - return ret; - - /* - * On A7XX_GEN3 and newer, raytracing may be disabled by the - * firmware, find out whether that's the case. The scm call - * above sets the fuse register. - */ - fuse_val =3D a6xx_llc_read(a6xx_gpu, - REG_A7XX_CX_MISC_SW_FUSE_VALUE); - adreno_gpu->has_ray_tracing =3D - !!(fuse_val & A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING); - } else if (adreno_is_a740(adreno_gpu)) { - /* Raytracing is always enabled on a740 */ - adreno_gpu->has_ray_tracing =3D true; - } - - return 0; -} - - #define GBIF_CLIENT_HALT_MASK BIT(0) #define GBIF_ARB_HALT_MASK BIT(1) #define VBIF_XIN_HALT_CTRL0_MASK GENMASK(3, 0) @@ -2705,14 +2654,6 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_devi= ce *dev) return ERR_PTR(ret); } =20 - if (adreno_is_a7xx(adreno_gpu) || adreno_is_a8xx(adreno_gpu)) { - ret =3D a7xx_cx_mem_init(a6xx_gpu); - if (ret) { - a6xx_destroy(&(a6xx_gpu->base.base)); - return ERR_PTR(ret); - } - } - adreno_gpu->uche_trap_base =3D 0x1fffffffff000ull; =20 msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu, --=20 2.51.0